include/net/pfe_eth/pfe/cbus/hif.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2015-2016 Freescale Semiconductor, Inc.
   4  * Copyright 2017 NXP
   5  */
   6
   7 #ifndef _HIF_H_
   8 #define _HIF_H_
   9
  10 /*
  11  * @file hif.h.
  12  * hif - PFE hif block control and status register.
  13  * Mapped on CBUS and accessible from all PE's and ARM.
  14  */
  15 #define HIF_VERSION             (HIF_BASE_ADDR + 0x00)
  16 #define HIF_TX_CTRL             (HIF_BASE_ADDR + 0x04)
  17 #define HIF_TX_CURR_BD_ADDR     (HIF_BASE_ADDR + 0x08)
  18 #define HIF_TX_ALLOC            (HIF_BASE_ADDR + 0x0c)
  19 #define HIF_TX_BDP_ADDR         (HIF_BASE_ADDR + 0x10)
  20 #define HIF_TX_STATUS           (HIF_BASE_ADDR + 0x14)
  21 #define HIF_RX_CTRL             (HIF_BASE_ADDR + 0x20)
  22 #define HIF_RX_BDP_ADDR         (HIF_BASE_ADDR + 0x24)
  23 #define HIF_RX_STATUS           (HIF_BASE_ADDR + 0x30)
  24 #define HIF_INT_SRC             (HIF_BASE_ADDR + 0x34)
  25 #define HIF_INT_ENABLE          (HIF_BASE_ADDR + 0x38)
  26 #define HIF_POLL_CTRL           (HIF_BASE_ADDR + 0x3c)
  27 #define HIF_RX_CURR_BD_ADDR     (HIF_BASE_ADDR + 0x40)
  28 #define HIF_RX_ALLOC            (HIF_BASE_ADDR + 0x44)
  29 #define HIF_TX_DMA_STATUS       (HIF_BASE_ADDR + 0x48)
  30 #define HIF_RX_DMA_STATUS       (HIF_BASE_ADDR + 0x4c)
  31 #define HIF_INT_COAL            (HIF_BASE_ADDR + 0x50)
  32 #define HIF_AXI_CTRL            (HIF_BASE_ADDR + 0x54)
  33
  34 /* HIF_TX_CTRL bits */
  35 #define HIF_CTRL_DMA_EN                 BIT(0)
  36 #define HIF_CTRL_BDP_POLL_CTRL_EN       BIT(1)
  37 #define HIF_CTRL_BDP_CH_START_WSTB      BIT(2)
  38
  39 /* HIF_RX_STATUS bits */
  40 #define BDP_CSR_RX_DMA_ACTV     BIT(16)
  41
  42 /* HIF_INT_ENABLE bits */
  43 #define HIF_INT_EN              BIT(0)
  44 #define HIF_RXBD_INT_EN         BIT(1)
  45 #define HIF_RXPKT_INT_EN        BIT(2)
  46 #define HIF_TXBD_INT_EN         BIT(3)
  47 #define HIF_TXPKT_INT_EN        BIT(4)
  48
  49 /* HIF_POLL_CTRL bits*/
  50 #define HIF_RX_POLL_CTRL_CYCLE  0x0400
  51 #define HIF_TX_POLL_CTRL_CYCLE  0x0400
  52
  53 /* Buffer descriptor control bits */
  54 #define BD_CTRL_BUFLEN_MASK     (0xffff)
  55 #define BD_BUF_LEN(x)   (x & BD_CTRL_BUFLEN_MASK)
  56 #define BD_CTRL_CBD_INT_EN      BIT(16)
  57 #define BD_CTRL_PKT_INT_EN      BIT(17)
  58 #define BD_CTRL_LIFM            BIT(18)
  59 #define BD_CTRL_LAST_BD         BIT(19)
  60 #define BD_CTRL_DIR             BIT(20)
  61 #define BD_CTRL_PKT_XFER        BIT(24)
  62 #define BD_CTRL_DESC_EN         BIT(31)
  63 #define BD_CTRL_PARSE_DISABLE   BIT(25)
  64 #define BD_CTRL_BRFETCH_DISABLE BIT(26)
  65 #define BD_CTRL_RTFETCH_DISABLE BIT(27)
  66
  67 #endif /* _HIF_H_ */