1 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
3 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
5 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
8 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
10 2013-01-24 Nick Clifton <nickc@redhat.com>
12 * v850.h: Add e3v5 support.
14 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
16 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
18 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
20 * ppc.h (PPC_OPCODE_POWER8): New define.
21 (PPC_OPCODE_HTM): Likewise.
23 2013-01-10 Will Newton <will.newton@imgtec.com>
27 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
29 * cr16.h (make_instruction): Rename to cr16_make_instruction.
30 (match_opcode): Rename to cr16_match_opcode.
32 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
34 * mips.h: Add support for r5900 instructions including lq and sq.
36 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
38 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
39 (make_instruction,match_opcode): Added function prototypes.
40 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
42 2012-11-23 Alan Modra <amodra@gmail.com>
44 * ppc.h (ppc_parse_cpu): Update prototype.
46 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
48 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
49 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
51 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
53 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
55 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
57 * ia64.h (ia64_opnd): Add new operand types.
59 2012-08-21 David S. Miller <davem@davemloft.net>
61 * sparc.h (F3F4): New macro.
63 2012-08-13 Ian Bolton <ian.bolton@arm.com>
64 Laurent Desnogues <laurent.desnogues@arm.com>
65 Jim MacArthur <jim.macarthur@arm.com>
66 Marcus Shawcroft <marcus.shawcroft@arm.com>
67 Nigel Stephens <nigel.stephens@arm.com>
68 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
69 Richard Earnshaw <rearnsha@arm.com>
70 Sofiane Naci <sofiane.naci@arm.com>
71 Tejas Belagod <tejas.belagod@arm.com>
72 Yufeng Zhang <yufeng.zhang@arm.com>
74 * aarch64.h: New file.
76 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
77 Maciej W. Rozycki <macro@codesourcery.com>
79 * mips.h (mips_opcode): Add the exclusions field.
80 (OPCODE_IS_MEMBER): Remove macro.
81 (cpu_is_member): New inline function.
82 (opcode_is_member): Likewise.
84 2012-07-31 Chao-Ying Fu <fu@mips.com>
85 Catherine Moore <clm@codesourcery.com>
86 Maciej W. Rozycki <macro@codesourcery.com>
88 * mips.h: Document microMIPS DSP ASE usage.
89 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
90 microMIPS DSP ASE support.
91 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
92 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
93 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
94 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
95 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
96 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
97 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
99 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
101 * mips.h: Fix a typo in description.
103 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
105 * avr.h: (AVR_ISA_XCH): New define.
106 (AVR_ISA_XMEGA): Use it.
107 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
109 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
111 * m68hc11.h: Add XGate definitions.
112 (struct m68hc11_opcode): Add xg_mask field.
114 2012-05-14 Catherine Moore <clm@codesourcery.com>
115 Maciej W. Rozycki <macro@codesourcery.com>
116 Rhonda Wittels <rhonda@codesourcery.com>
118 * ppc.h (PPC_OPCODE_VLE): New definition.
119 (PPC_OP_SA): New macro.
120 (PPC_OP_SE_VLE): New macro.
121 (PPC_OP): Use a variable shift amount.
122 (powerpc_operand): Update comments.
123 (PPC_OPSHIFT_INV): New macro.
124 (PPC_OPERAND_CR): Replace with...
125 (PPC_OPERAND_CR_BIT): ...this and
126 (PPC_OPERAND_CR_REG): ...this.
129 2012-05-03 Sean Keys <skeys@ipdatasys.com>
131 * xgate.h: Header file for XGATE assembler.
133 2012-04-27 David S. Miller <davem@davemloft.net>
135 * sparc.h: Document new arg code' )' for crypto RS3
138 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
139 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
140 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
141 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
142 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
143 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
144 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
145 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
146 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
147 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
148 HWCAP_CBCOND, HWCAP_CRC32): New defines.
150 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
152 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
154 2012-02-27 Alan Modra <amodra@gmail.com>
156 * crx.h (cst4_map): Update declaration.
158 2012-02-25 Walter Lee <walt@tilera.com>
160 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
162 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
163 TILEPRO_OPC_LW_TLS_SN.
165 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
167 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
168 (XRELEASE_PREFIX_OPCODE): Likewise.
170 2011-12-08 Andrew Pinski <apinski@cavium.com>
171 Adam Nemet <anemet@caviumnetworks.com>
173 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
174 (INSN_OCTEON2): New macro.
175 (CPU_OCTEON2): New macro.
176 (OPCODE_IS_MEMBER): Add Octeon2.
178 2011-11-29 Andrew Pinski <apinski@cavium.com>
180 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
181 (INSN_OCTEONP): New macro.
182 (CPU_OCTEONP): New macro.
183 (OPCODE_IS_MEMBER): Add Octeon+.
184 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
186 2011-11-01 DJ Delorie <dj@redhat.com>
190 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
192 * mips.h: Fix a typo in description.
194 2011-09-21 David S. Miller <davem@davemloft.net>
196 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
197 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
198 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
199 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
201 2011-08-09 Chao-ying Fu <fu@mips.com>
202 Maciej W. Rozycki <macro@codesourcery.com>
204 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
205 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
206 (INSN_ASE_MASK): Add the MCU bit.
207 (INSN_MCU): New macro.
208 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
209 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
211 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
213 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
214 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
215 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
216 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
217 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
218 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
219 (INSN2_READ_GPR_MMN): Likewise.
220 (INSN2_READ_FPR_D): Change the bit used.
221 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
222 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
223 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
224 (INSN2_COND_BRANCH): Likewise.
225 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
226 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
227 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
228 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
229 (INSN2_MOD_GPR_MN): Likewise.
231 2011-08-05 David S. Miller <davem@davemloft.net>
233 * sparc.h: Document new format codes '4', '5', and '('.
234 (OPF_LOW4, RS3): New macros.
236 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
238 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
239 order of flags documented.
241 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
243 * mips.h: Clarify the description of microMIPS instruction
245 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
247 2011-07-24 Chao-ying Fu <fu@mips.com>
248 Maciej W. Rozycki <macro@codesourcery.com>
250 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
251 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
252 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
253 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
254 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
255 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
256 (OP_MASK_RS3, OP_SH_RS3): Likewise.
257 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
258 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
259 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
260 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
261 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
262 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
263 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
264 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
265 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
266 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
267 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
268 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
269 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
270 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
271 (INSN_WRITE_GPR_S): New macro.
272 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
273 (INSN2_READ_FPR_D): Likewise.
274 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
275 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
276 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
277 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
278 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
279 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
280 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
281 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
282 (CPU_MICROMIPS): New macro.
283 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
284 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
285 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
286 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
287 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
288 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
289 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
290 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
291 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
292 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
293 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
294 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
295 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
296 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
297 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
298 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
299 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
300 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
301 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
302 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
303 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
304 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
305 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
306 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
307 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
308 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
309 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
310 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
311 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
312 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
313 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
314 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
315 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
316 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
317 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
318 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
319 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
320 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
321 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
322 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
323 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
324 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
325 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
326 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
327 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
328 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
329 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
330 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
331 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
332 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
333 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
334 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
335 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
336 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
337 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
338 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
339 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
340 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
341 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
342 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
343 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
344 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
345 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
346 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
347 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
348 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
349 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
350 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
351 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
352 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
353 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
354 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
355 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
356 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
357 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
358 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
359 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
360 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
361 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
362 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
363 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
364 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
365 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
366 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
367 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
368 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
369 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
370 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
371 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
372 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
373 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
374 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
375 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
376 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
377 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
378 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
379 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
380 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
381 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
382 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
383 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
384 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
385 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
386 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
387 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
388 (micromips_opcodes): New declaration.
389 (bfd_micromips_num_opcodes): Likewise.
391 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
393 * mips.h (INSN_TRAP): Rename to...
394 (INSN_NO_DELAY_SLOT): ... this.
395 (INSN_SYNC): Remove macro.
397 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
399 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
400 a duplicate of AVR_ISA_SPM.
402 2011-07-01 Nick Clifton <nickc@redhat.com>
404 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
406 2011-06-18 Robin Getz <robin.getz@analog.com>
408 * bfin.h (is_macmod_signed): New func
410 2011-06-18 Mike Frysinger <vapier@gentoo.org>
412 * bfin.h (is_macmod_pmove): Add missing space before func args.
413 (is_macmod_hmove): Likewise.
415 2011-06-13 Walter Lee <walt@tilera.com>
417 * tilegx.h: New file.
418 * tilepro.h: New file.
420 2011-05-31 Paul Brook <paul@codesourcery.com>
422 * arm.h (ARM_ARCH_V7R_IDIV): Define.
424 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
426 * s390.h: Replace S390_OPERAND_REG_EVEN with
427 S390_OPERAND_REG_PAIR.
429 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
431 * s390.h: Add S390_OPCODE_REG_EVEN flag.
433 2011-04-18 Julian Brown <julian@codesourcery.com>
435 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
437 2011-04-11 Dan McDonald <dan@wellkeeper.com>
440 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
442 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
444 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
445 New instruction set flags.
446 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
448 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
450 * mips.h (M_PREF_AB): New enum value.
452 2011-02-12 Mike Frysinger <vapier@gentoo.org>
454 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
456 (is_macmod_pmove, is_macmod_hmove): New functions.
458 2011-02-11 Mike Frysinger <vapier@gentoo.org>
460 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
462 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
464 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
465 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
467 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
470 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
473 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
476 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
478 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
480 * mips.h: Update commentary after last commit.
482 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
484 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
485 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
486 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
488 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
490 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
492 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
494 * mips.h: Fix previous commit.
496 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
498 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
499 (INSN_LOONGSON_3A): Clear bit 31.
501 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
504 * arm.h (ARM_AEXT_V6M_ONLY): New define.
505 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
506 (ARM_ARCH_V6M_ONLY): New define.
508 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
510 * mips.h (INSN_LOONGSON_3A): Defined.
511 (CPU_LOONGSON_3A): Defined.
512 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
514 2010-10-09 Matt Rice <ratmice@gmail.com>
516 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
517 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
519 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
521 * arm.h (ARM_EXT_VIRT): New define.
522 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
523 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
526 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
528 * arm.h (ARM_AEXT_ADIV): New define.
529 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
531 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
533 * arm.h (ARM_EXT_OS): New define.
534 (ARM_AEXT_V6SM): Likewise.
535 (ARM_ARCH_V6SM): Likewise.
537 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
539 * arm.h (ARM_EXT_MP): Add.
540 (ARM_ARCH_V7A_MP): Likewise.
542 2010-09-22 Mike Frysinger <vapier@gentoo.org>
544 * bfin.h: Declare pseudoChr structs/defines.
546 2010-09-21 Mike Frysinger <vapier@gentoo.org>
548 * bfin.h: Strip trailing whitespace.
550 2010-07-29 DJ Delorie <dj@redhat.com>
552 * rx.h (RX_Operand_Type): Add TwoReg.
553 (RX_Opcode_ID): Remove ediv and ediv2.
555 2010-07-27 DJ Delorie <dj@redhat.com>
557 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
559 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
560 Ina Pandit <ina.pandit@kpitcummins.com>
562 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
563 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
564 PROCESSOR_V850E2_ALL.
565 Remove PROCESSOR_V850EA support.
566 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
567 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
568 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
569 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
570 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
571 V850_OPERAND_PERCENT.
572 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
574 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
577 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
579 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
580 (MIPS16_INSN_BRANCH): Rename to...
581 (MIPS16_INSN_COND_BRANCH): ... this.
583 2010-07-03 Alan Modra <amodra@gmail.com>
585 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
586 Renumber other PPC_OPCODE defines.
588 2010-07-03 Alan Modra <amodra@gmail.com>
590 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
592 2010-06-29 Alan Modra <amodra@gmail.com>
594 * maxq.h: Delete file.
596 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
598 * ppc.h (PPC_OPCODE_E500): Define.
600 2010-05-26 Catherine Moore <clm@codesourcery.com>
602 * opcode/mips.h (INSN_MIPS16): Remove.
604 2010-04-21 Joseph Myers <joseph@codesourcery.com>
606 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
608 2010-04-15 Nick Clifton <nickc@redhat.com>
610 * alpha.h: Update copyright notice to use GPLv3.
616 * convex.h: Likewise.
630 * m68hc11.h: Likewise.
636 * mn10200.h: Likewise.
637 * mn10300.h: Likewise.
638 * msp430.h: Likewise.
649 * score-datadep.h: Likewise.
650 * score-inst.h: Likewise.
652 * spu-insns.h: Likewise.
656 * tic54x.h: Likewise.
661 2010-03-25 Joseph Myers <joseph@codesourcery.com>
663 * tic6x-control-registers.h, tic6x-insn-formats.h,
664 tic6x-opcode-table.h, tic6x.h: New.
666 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
668 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
670 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
672 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
674 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
676 * ia64.h (ia64_find_opcode): Remove argument name.
677 (ia64_find_next_opcode): Likewise.
678 (ia64_dis_opcode): Likewise.
679 (ia64_free_opcode): Likewise.
680 (ia64_find_dependency): Likewise.
682 2009-11-22 Doug Evans <dje@sebabeach.org>
684 * cgen.h: Include bfd_stdint.h.
685 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
687 2009-11-18 Paul Brook <paul@codesourcery.com>
689 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
691 2009-11-17 Paul Brook <paul@codesourcery.com>
692 Daniel Jacobowitz <dan@codesourcery.com>
694 * arm.h (ARM_EXT_V6_DSP): Define.
695 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
696 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
698 2009-11-04 DJ Delorie <dj@redhat.com>
700 * rx.h (rx_decode_opcode) (mvtipl): Add.
701 (mvtcp, mvfcp, opecp): Remove.
703 2009-11-02 Paul Brook <paul@codesourcery.com>
705 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
706 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
707 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
708 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
709 FPU_ARCH_NEON_VFP_V4): Define.
711 2009-10-23 Doug Evans <dje@sebabeach.org>
713 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
714 * cgen.h: Update. Improve multi-inclusion macro name.
716 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
718 * ppc.h (PPC_OPCODE_476): Define.
720 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
722 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
724 2009-09-29 DJ Delorie <dj@redhat.com>
728 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
730 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
732 2009-09-21 Ben Elliston <bje@au.ibm.com>
734 * ppc.h (PPC_OPCODE_PPCA2): New.
736 2009-09-05 Martin Thuresson <martin@mtme.org>
738 * ia64.h (struct ia64_operand): Renamed member class to op_class.
740 2009-08-29 Martin Thuresson <martin@mtme.org>
742 * tic30.h (template): Rename type template to
743 insn_template. Updated code to use new name.
744 * tic54x.h (template): Rename type template to
747 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
749 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
751 2009-06-11 Anthony Green <green@moxielogic.com>
753 * moxie.h (MOXIE_F3_PCREL): Define.
754 (moxie_form3_opc_info): Grow.
756 2009-06-06 Anthony Green <green@moxielogic.com>
758 * moxie.h (MOXIE_F1_M): Define.
760 2009-04-15 Anthony Green <green@moxielogic.com>
764 2009-04-06 DJ Delorie <dj@redhat.com>
766 * h8300.h: Add relaxation attributes to MOVA opcodes.
768 2009-03-10 Alan Modra <amodra@bigpond.net.au>
770 * ppc.h (ppc_parse_cpu): Declare.
772 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
774 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
775 and _IMM11 for mbitclr and mbitset.
776 * score-datadep.h: Update dependency information.
778 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
780 * ppc.h (PPC_OPCODE_POWER7): New.
782 2009-02-06 Doug Evans <dje@google.com>
784 * i386.h: Add comment regarding sse* insns and prefixes.
786 2009-02-03 Sandip Matte <sandip@rmicorp.com>
788 * mips.h (INSN_XLR): Define.
789 (INSN_CHIP_MASK): Update.
791 (OPCODE_IS_MEMBER): Update.
792 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
794 2009-01-28 Doug Evans <dje@google.com>
796 * opcode/i386.h: Add multiple inclusion protection.
797 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
798 (EDI_REG_NUM): New macros.
799 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
800 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
801 (REX_PREFIX_P): New macro.
803 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
805 * ppc.h (struct powerpc_opcode): New field "deprecated".
806 (PPC_OPCODE_NOPOWER4): Delete.
808 2008-11-28 Joshua Kinard <kumba@gentoo.org>
810 * mips.h: Define CPU_R14000, CPU_R16000.
811 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
813 2008-11-18 Catherine Moore <clm@codesourcery.com>
815 * arm.h (FPU_NEON_FP16): New.
816 (FPU_ARCH_NEON_FP16): New.
818 2008-11-06 Chao-ying Fu <fu@mips.com>
820 * mips.h: Doucument '1' for 5-bit sync type.
822 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
824 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
827 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
829 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
831 2008-07-30 Michael J. Eager <eager@eagercon.com>
833 * ppc.h (PPC_OPCODE_405): Define.
834 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
836 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
838 * ppc.h (ppc_cpu_t): New typedef.
839 (struct powerpc_opcode <flags>): Use it.
840 (struct powerpc_operand <insert, extract>): Likewise.
841 (struct powerpc_macro <flags>): Likewise.
843 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
845 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
846 Update comment before MIPS16 field descriptors to mention MIPS16.
847 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
849 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
850 New bit masks and shift counts for cins and exts.
852 * mips.h: Document new field descriptors +Q.
853 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
855 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
857 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
858 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
860 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
862 * ppc.h: (PPC_OPCODE_E500MC): New.
864 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
866 * i386.h (MAX_OPERANDS): Set to 5.
867 (MAX_MNEM_SIZE): Changed to 20.
869 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
871 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
873 2008-03-09 Paul Brook <paul@codesourcery.com>
875 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
877 2008-03-04 Paul Brook <paul@codesourcery.com>
879 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
880 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
881 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
883 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
884 Nick Clifton <nickc@redhat.com>
887 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
888 with a 32-bit displacement but without the top bit of the 4th byte
891 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
893 * cr16.h (cr16_num_optab): Declared.
895 2008-02-14 Hakan Ardo <hakan@debian.org>
898 * avr.h (AVR_ISA_2xxe): Define.
900 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
902 * mips.h: Update copyright.
903 (INSN_CHIP_MASK): New macro.
904 (INSN_OCTEON): New macro.
905 (CPU_OCTEON): New macro.
906 (OPCODE_IS_MEMBER): Handle Octeon instructions.
908 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
910 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
912 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
914 * avr.h (AVR_ISA_USB162): Add new opcode set.
915 (AVR_ISA_AVR3): Likewise.
917 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
919 * mips.h (INSN_LOONGSON_2E): New.
920 (INSN_LOONGSON_2F): New.
921 (CPU_LOONGSON_2E): New.
922 (CPU_LOONGSON_2F): New.
923 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
925 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
927 * mips.h (INSN_ISA*): Redefine certain values as an
928 enumeration. Update comments.
929 (mips_isa_table): New.
930 (ISA_MIPS*): Redefine to match enumeration.
931 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
934 2007-08-08 Ben Elliston <bje@au.ibm.com>
936 * ppc.h (PPC_OPCODE_PPCPS): New.
938 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
940 * m68k.h: Document j K & E.
942 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
944 * cr16.h: New file for CR16 target.
946 2007-05-02 Alan Modra <amodra@bigpond.net.au>
948 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
950 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
952 * m68k.h (mcfisa_c): New.
953 (mcfusp, mcf_mask): Adjust.
955 2007-04-20 Alan Modra <amodra@bigpond.net.au>
957 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
958 (num_powerpc_operands): Declare.
959 (PPC_OPERAND_SIGNED et al): Redefine as hex.
960 (PPC_OPERAND_PLUS1): Define.
962 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
964 * i386.h (REX_MODE64): Renamed to ...
966 (REX_EXTX): Renamed to ...
968 (REX_EXTY): Renamed to ...
970 (REX_EXTZ): Renamed to ...
973 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
975 * i386.h: Add entries from config/tc-i386.h and move tables
976 to opcodes/i386-opc.h.
978 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
980 * i386.h (FloatDR): Removed.
981 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
983 2007-03-01 Alan Modra <amodra@bigpond.net.au>
985 * spu-insns.h: Add soma double-float insns.
987 2007-02-20 Thiemo Seufer <ths@mips.com>
988 Chao-Ying Fu <fu@mips.com>
990 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
991 (INSN_DSPR2): Add flag for DSP R2 instructions.
992 (M_BALIGN): New macro.
994 2007-02-14 Alan Modra <amodra@bigpond.net.au>
996 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
997 and Seg3ShortFrom with Shortform.
999 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1002 * i386.h (i386_optab): Put the real "test" before the pseudo
1005 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1007 * m68k.h (m68010up): OR fido_a.
1009 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1011 * m68k.h (fido_a): New.
1013 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1015 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1016 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1019 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1021 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1023 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1025 * score-inst.h (enum score_insn_type): Add Insn_internal.
1027 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1028 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1029 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1030 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1031 Alan Modra <amodra@bigpond.net.au>
1033 * spu-insns.h: New file.
1036 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1038 * ppc.h (PPC_OPCODE_CELL): Define.
1040 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1042 * i386.h : Modify opcode to support for the change in POPCNT opcode
1043 in amdfam10 architecture.
1045 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1047 * i386.h: Replace CpuMNI with CpuSSSE3.
1049 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1050 Joseph Myers <joseph@codesourcery.com>
1051 Ian Lance Taylor <ian@wasabisystems.com>
1052 Ben Elliston <bje@wasabisystems.com>
1054 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1056 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1058 * score-datadep.h: New file.
1059 * score-inst.h: New file.
1061 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1063 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1064 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1065 movdq2q and movq2dq.
1067 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1068 Michael Meissner <michael.meissner@amd.com>
1070 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1072 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1074 * i386.h (i386_optab): Add "nop" with memory reference.
1076 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1078 * i386.h (i386_optab): Update comment for 64bit NOP.
1080 2006-06-06 Ben Elliston <bje@au.ibm.com>
1081 Anton Blanchard <anton@samba.org>
1083 * ppc.h (PPC_OPCODE_POWER6): Define.
1086 2006-06-05 Thiemo Seufer <ths@mips.com>
1088 * mips.h: Improve description of MT flags.
1090 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1092 * m68k.h (mcf_mask): Define.
1094 2006-05-05 Thiemo Seufer <ths@mips.com>
1095 David Ung <davidu@mips.com>
1097 * mips.h (enum): Add macro M_CACHE_AB.
1099 2006-05-04 Thiemo Seufer <ths@mips.com>
1100 Nigel Stephens <nigel@mips.com>
1101 David Ung <davidu@mips.com>
1103 * mips.h: Add INSN_SMARTMIPS define.
1105 2006-04-30 Thiemo Seufer <ths@mips.com>
1106 David Ung <davidu@mips.com>
1108 * mips.h: Defines udi bits and masks. Add description of
1109 characters which may appear in the args field of udi
1112 2006-04-26 Thiemo Seufer <ths@networkno.de>
1114 * mips.h: Improve comments describing the bitfield instruction
1117 2006-04-26 Julian Brown <julian@codesourcery.com>
1119 * arm.h (FPU_VFP_EXT_V3): Define constant.
1120 (FPU_NEON_EXT_V1): Likewise.
1121 (FPU_VFP_HARD): Update.
1122 (FPU_VFP_V3): Define macro.
1123 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1125 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1127 * avr.h (AVR_ISA_PWMx): New.
1129 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1131 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1132 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1133 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1134 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1135 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1137 2006-03-10 Paul Brook <paul@codesourcery.com>
1139 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1141 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1143 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1144 first. Correct mask of bb "B" opcode.
1146 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1148 * i386.h (i386_optab): Support Intel Merom New Instructions.
1150 2006-02-24 Paul Brook <paul@codesourcery.com>
1152 * arm.h: Add V7 feature bits.
1154 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1156 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1158 2006-01-31 Paul Brook <paul@codesourcery.com>
1159 Richard Earnshaw <rearnsha@arm.com>
1161 * arm.h: Use ARM_CPU_FEATURE.
1162 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1163 (arm_feature_set): Change to a structure.
1164 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1165 ARM_FEATURE): New macros.
1167 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1169 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1170 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1171 (ADD_PC_INCR_OPCODE): Don't define.
1173 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1176 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1178 2005-11-14 David Ung <davidu@mips.com>
1180 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1181 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1182 save/restore encoding of the args field.
1184 2005-10-28 Dave Brolley <brolley@redhat.com>
1186 Contribute the following changes:
1187 2005-02-16 Dave Brolley <brolley@redhat.com>
1189 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1190 cgen_isa_mask_* to cgen_bitset_*.
1193 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1195 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1196 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1197 (CGEN_CPU_TABLE): Make isas a ponter.
1199 2003-09-29 Dave Brolley <brolley@redhat.com>
1201 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1202 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1203 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1205 2002-12-13 Dave Brolley <brolley@redhat.com>
1207 * cgen.h (symcat.h): #include it.
1208 (cgen-bitset.h): #include it.
1209 (CGEN_ATTR_VALUE_TYPE): Now a union.
1210 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1211 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1212 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1213 * cgen-bitset.h: New file.
1215 2005-09-30 Catherine Moore <clm@cm00re.com>
1219 2005-10-24 Jan Beulich <jbeulich@novell.com>
1221 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1224 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1226 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1227 Add FLAG_STRICT to pa10 ftest opcode.
1229 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1231 * hppa.h (pa_opcodes): Remove lha entries.
1233 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1235 * hppa.h (FLAG_STRICT): Revise comment.
1236 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1237 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1240 2005-09-30 Catherine Moore <clm@cm00re.com>
1244 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1246 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1248 2005-09-06 Chao-ying Fu <fu@mips.com>
1250 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1251 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1253 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1254 (INSN_ASE_MASK): Update to include INSN_MT.
1255 (INSN_MT): New define for MT ASE.
1257 2005-08-25 Chao-ying Fu <fu@mips.com>
1259 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1260 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1261 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1262 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1263 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1264 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1266 (INSN_DSP): New define for DSP ASE.
1268 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1272 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1274 * ppc.h (PPC_OPCODE_E300): Define.
1276 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1278 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1280 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1283 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1286 2005-07-27 Jan Beulich <jbeulich@novell.com>
1288 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1289 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1290 Add movq-s as 64-bit variants of movd-s.
1292 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1294 * hppa.h: Fix punctuation in comment.
1296 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1297 implicit space-register addressing. Set space-register bits on opcodes
1298 using implicit space-register addressing. Add various missing pa20
1299 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1300 space-register addressing. Use "fE" instead of "fe" in various
1303 2005-07-18 Jan Beulich <jbeulich@novell.com>
1305 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1307 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1309 * i386.h (i386_optab): Support Intel VMX Instructions.
1311 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1313 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1315 2005-07-05 Jan Beulich <jbeulich@novell.com>
1317 * i386.h (i386_optab): Add new insns.
1319 2005-07-01 Nick Clifton <nickc@redhat.com>
1321 * sparc.h: Add typedefs to structure declarations.
1323 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1326 * i386.h (i386_optab): Update comments for 64bit addressing on
1327 mov. Allow 64bit addressing for mov and movq.
1329 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1331 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1332 respectively, in various floating-point load and store patterns.
1334 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1336 * hppa.h (FLAG_STRICT): Correct comment.
1337 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1338 PA 2.0 mneumonics when equivalent. Entries with cache control
1339 completers now require PA 1.1. Adjust whitespace.
1341 2005-05-19 Anton Blanchard <anton@samba.org>
1343 * ppc.h (PPC_OPCODE_POWER5): Define.
1345 2005-05-10 Nick Clifton <nickc@redhat.com>
1347 * Update the address and phone number of the FSF organization in
1348 the GPL notices in the following files:
1349 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1350 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1351 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1352 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1353 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1354 tic54x.h, tic80.h, v850.h, vax.h
1356 2005-05-09 Jan Beulich <jbeulich@novell.com>
1358 * i386.h (i386_optab): Add ht and hnt.
1360 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1362 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1363 Add xcrypt-ctr. Provide aliases without hyphens.
1365 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1367 Moved from ../ChangeLog
1369 2005-04-12 Paul Brook <paul@codesourcery.com>
1370 * m88k.h: Rename psr macros to avoid conflicts.
1372 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1373 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1374 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1375 and ARM_ARCH_V6ZKT2.
1377 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1378 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1379 Remove redundant instruction types.
1380 (struct argument): X_op - new field.
1381 (struct cst4_entry): Remove.
1382 (no_op_insn): Declare.
1384 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1385 * crx.h (enum argtype): Rename types, remove unused types.
1387 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1388 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1389 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1390 (enum operand_type): Rearrange operands, edit comments.
1391 replace us<N> with ui<N> for unsigned immediate.
1392 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1393 displacements (respectively).
1394 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1395 (instruction type): Add NO_TYPE_INS.
1396 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1397 (operand_entry): New field - 'flags'.
1398 (operand flags): New.
1400 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1401 * crx.h (operand_type): Remove redundant types i3, i4,
1403 Add new unsigned immediate types us3, us4, us5, us16.
1405 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1407 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1408 adjust them accordingly.
1410 2005-04-01 Jan Beulich <jbeulich@novell.com>
1412 * i386.h (i386_optab): Add rdtscp.
1414 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1416 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1417 between memory and segment register. Allow movq for moving between
1418 general-purpose register and segment register.
1420 2005-02-09 Jan Beulich <jbeulich@novell.com>
1423 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1424 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1427 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1429 * m68k.h (m68008, m68ec030, m68882): Remove.
1431 (cpu_m68k, cpu_cf): New.
1432 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1433 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1435 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1437 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1438 * cgen.h (enum cgen_parse_operand_type): Add
1439 CGEN_PARSE_OPERAND_SYMBOLIC.
1441 2005-01-21 Fred Fish <fnf@specifixinc.com>
1443 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1444 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1445 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1447 2005-01-19 Fred Fish <fnf@specifixinc.com>
1449 * mips.h (struct mips_opcode): Add new pinfo2 member.
1450 (INSN_ALIAS): New define for opcode table entries that are
1451 specific instances of another entry, such as 'move' for an 'or'
1452 with a zero operand.
1453 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1454 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1456 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1458 * mips.h (CPU_RM9000): Define.
1459 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1461 2004-11-25 Jan Beulich <jbeulich@novell.com>
1463 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1464 to/from test registers are illegal in 64-bit mode. Add missing
1465 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1466 (previously one had to explicitly encode a rex64 prefix). Re-enable
1467 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1468 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1470 2004-11-23 Jan Beulich <jbeulich@novell.com>
1472 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1473 available only with SSE2. Change the MMX additions introduced by SSE
1474 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1475 instructions by their now designated identifier (since combining i686
1476 and 3DNow! does not really imply 3DNow!A).
1478 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1480 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1481 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1483 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1484 Vineet Sharma <vineets@noida.hcltech.com>
1486 * maxq.h: New file: Disassembly information for the maxq port.
1488 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1490 * i386.h (i386_optab): Put back "movzb".
1492 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1494 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1495 comments. Remove member cris_ver_sim. Add members
1496 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1497 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1498 (struct cris_support_reg, struct cris_cond15): New types.
1499 (cris_conds15): Declare.
1500 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1501 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1502 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1503 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1504 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1505 SIZE_FIELD_UNSIGNED.
1507 2004-11-04 Jan Beulich <jbeulich@novell.com>
1509 * i386.h (sldx_Suf): Remove.
1510 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1511 (q_FP): Define, implying no REX64.
1512 (x_FP, sl_FP): Imply FloatMF.
1513 (i386_optab): Split reg and mem forms of moving from segment registers
1514 so that the memory forms can ignore the 16-/32-bit operand size
1515 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1516 all non-floating-point instructions. Unite 32- and 64-bit forms of
1517 movsx, movzx, and movd. Adjust floating point operations for the above
1518 changes to the *FP macros. Add DefaultSize to floating point control
1519 insns operating on larger memory ranges. Remove left over comments
1520 hinting at certain insns being Intel-syntax ones where the ones
1521 actually meant are already gone.
1523 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1525 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1528 2004-09-30 Paul Brook <paul@codesourcery.com>
1530 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1531 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1533 2004-09-11 Theodore A. Roth <troth@openavr.org>
1535 * avr.h: Add support for
1536 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1538 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1540 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1542 2004-08-24 Dmitry Diky <diwil@spec.ru>
1544 * msp430.h (msp430_opc): Add new instructions.
1545 (msp430_rcodes): Declare new instructions.
1546 (msp430_hcodes): Likewise..
1548 2004-08-13 Nick Clifton <nickc@redhat.com>
1551 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1554 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1556 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1558 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1560 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1562 2004-07-21 Jan Beulich <jbeulich@novell.com>
1564 * i386.h: Adjust instruction descriptions to better match the
1567 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1569 * arm.h: Remove all old content. Replace with architecture defines
1570 from gas/config/tc-arm.c.
1572 2004-07-09 Andreas Schwab <schwab@suse.de>
1574 * m68k.h: Fix comment.
1576 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1580 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1582 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1584 2004-05-24 Peter Barada <peter@the-baradas.com>
1586 * m68k.h: Add 'size' to m68k_opcode.
1588 2004-05-05 Peter Barada <peter@the-baradas.com>
1590 * m68k.h: Switch from ColdFire chip name to core variant.
1592 2004-04-22 Peter Barada <peter@the-baradas.com>
1594 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1595 descriptions for new EMAC cases.
1596 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1597 handle Motorola MAC syntax.
1598 Allow disassembly of ColdFire V4e object files.
1600 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1602 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1604 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1606 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1608 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1610 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1612 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1614 * i386.h (i386_optab): Added xstore/xcrypt insns.
1616 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1618 * h8300.h (32bit ldc/stc): Add relaxing support.
1620 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1622 * h8300.h (BITOP): Pass MEMRELAX flag.
1624 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1626 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1629 For older changes see ChangeLog-9103
1631 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1633 Copying and distribution of this file, with or without modification,
1634 are permitted in any medium without royalty provided the copyright
1635 notice and this notice are preserved.
1641 version-control: never