1 /* mips.h. Mips opcode list for GDB, the GNU debugger.
2 Copyright (C) 1993-2025 Free Software Foundation, Inc.
3 Contributed by Ralph Campbell and OSF
4 Commented and modified by Ian Lance Taylor, Cygnus Support
6 This file is part of GDB, GAS, and the GNU binutils.
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version 3,
11 or (at your option) any later version.
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING3. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
32 /* These are bit masks and shift counts to use to access the various
33 fields of an instruction. To retrieve the X field of an
34 instruction, use the expression
35 (i >> OP_SH_X) & OP_MASK_X
36 To set the same field (to j), use
37 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
39 Make sure you use fields that are appropriate for the instruction,
42 The 'i' format uses OP, RS, RT and IMMEDIATE.
44 The 'j' format uses OP and TARGET.
46 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
48 The 'b' format uses OP, RS, RT and DELTA.
50 The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
52 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
54 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
55 breakpoint instruction are not defined; Kane says the breakpoint
56 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
57 only use ten bits). An optional two-operand form of break/sdbbp
58 allows the lower ten bits to be set too, and MIPS32 and later
59 architectures allow 20 bits to be set with a single operand for
60 the sdbbp instruction (using CODE20).
62 The syscall instruction uses CODE20.
64 The general coprocessor instructions use COPZ. */
66 #define OP_MASK_OP 0x3f
68 #define OP_MASK_RS 0x1f
70 #define OP_MASK_BCC 0x7
72 #define OP_MASK_RT 0x1f
74 #define OP_MASK_RD 0x1f
76 #define OP_MASK_IMMEDIATE 0xffff
77 #define OP_SH_IMMEDIATE 0
79 /* Values in the 'VSEL' field. */
80 #define MDMX_FMTSEL_IMM_QH 0x1d
81 #define MDMX_FMTSEL_IMM_OB 0x1e
82 #define MDMX_FMTSEL_VEC_QH 0x15
83 #define MDMX_FMTSEL_VEC_OB 0x16
85 /* Enumerates the various types of MIPS operand. */
86 enum mips_operand_type
{
87 /* Described by mips_int_operand. */
90 /* Described by mips_mapped_int_operand. */
93 /* Described by mips_msb_operand. */
96 /* Described by mips_reg_operand. */
99 /* Like OP_REG, but can be omitted if the register is the same as the
103 /* Described by mips_reg_pair_operand. */
106 /* Described by mips_pcrel_operand. */
109 /* A performance register. The field is 5 bits in size, but the supported
110 values are much more restricted. */
113 /* The final operand in a microMIPS ADDIUSP instruction. It mostly acts
114 as a normal 9-bit signed offset that is multiplied by four, but there
115 are four special cases:
123 /* The target of a (D)CLO or (D)CLZ instruction. The operand spans two
124 5-bit register fields, both of which must be set to the destination
128 /* A register list for a microMIPS LWM or SWM instruction. The operand
129 size determines whether the 16-bit or 32-bit encoding is required. */
132 /* The register list for an emulated MIPS16 ENTRY or EXIT instruction. */
135 /* The register list and frame size for a MIPS16 SAVE or RESTORE
137 OP_SAVE_RESTORE_LIST
,
139 /* A 10-bit field VVVVVNNNNN used for octobyte and quadhalf instructions:
143 0EEE0 8 copies of $vN[E], OB format
144 0EE01 4 copies of $vN[E], QH format
145 10110 all 8 elements of $vN, OB format
146 10101 all 4 elements of $vN, QH format
147 11110 8 copies of immediate N, OB format
148 11101 4 copies of immediate N, QH format. */
151 /* A register operand that must match the destination register. */
154 /* A register operand that must match the previous register. */
157 /* $pc, which has no encoding in the architectural instruction. */
160 /* $28, which has no encoding in the MIPS16e architectural instruction. */
163 /* A 4-bit XYZW channel mask or 2-bit XYZW index; the size determines
167 /* Like OP_VU0_SUFFIX, but used when the operand's value has already
168 been set. Any suffix used here must match the previous value. */
171 /* An index selected by an integer, e.g. [1]. */
174 /* An index selected by a register, e.g. [$2]. */
177 /* The operand spans two 5-bit register fields, both of which must be set to
178 the source register. */
181 /* Described by mips_prev_operand. */
184 /* A register operand that must not be zero. */
188 /* Enumerates the types of MIPS register. */
189 enum mips_reg_operand_type
{
190 /* General registers $0-$31. Software names like $at can also be used. */
193 /* Floating-point registers $f0-$f31. */
196 /* Coprocessor condition code registers $cc0-$cc7. FPU condition codes
197 can also be written $fcc0-$fcc7. */
200 /* FPRs used in a vector capacity. They can be written $f0-$f31
201 or $v0-$v31, although the latter form is not used for the VR5400
202 vector instructions. */
205 /* DSP accumulator registers $ac0-$ac3. */
208 /* Coprocessor registers $0-$31. Mnemonic names like c0_cause can
209 also be used in some contexts. */
212 /* Coprocessor control registers $0-$31. Mnemonic names like c1_fcsr can
213 also be used in some contexts. */
216 /* Hardware registers $0-$31. Mnemonic names like hwr_cpunum can
217 also be used in some contexts. */
220 /* Floating-point registers $vf0-$vf31. */
223 /* Integer registers $vi0-$vi31. */
226 /* R5900 VU0 registers $I, $Q, $R and $ACC. */
232 /* MSA registers $w0-$w31. */
235 /* MSA control registers $0-$31. */
239 /* Base class for all operands. */
242 /* The type of the operand. */
243 enum mips_operand_type type
;
245 /* The operand occupies SIZE bits of the instruction, starting at LSB. */
250 /* Describes an integer operand with a regular encoding pattern. */
251 struct mips_int_operand
253 struct mips_operand root
;
255 /* The low ROOT.SIZE bits of MAX_VAL encodes (MAX_VAL + BIAS) << SHIFT.
256 The cyclically previous field value encodes 1 << SHIFT less than that,
259 - for { { T, 4, L }, 14, 0, 0 }, field values 0...14 encode themselves,
262 - { { T, 8, L }, 127, 0, 2 } is a normal signed 8-bit operand that is
263 shifted left two places.
265 - { { T, 3, L }, 8, 0, 0 } is a normal unsigned 3-bit operand except
268 - { { ... }, 0, 1, 3 } means that N encodes (N + 1) << 3. */
269 unsigned int max_val
;
273 /* True if the operand should be printed as hex rather than decimal. */
277 /* Uses a lookup table to describe a small integer operand. */
278 struct mips_mapped_int_operand
280 struct mips_operand root
;
282 /* Maps each encoding value to the integer that it represents. */
285 /* True if the operand should be printed as hex rather than decimal. */
289 /* An operand that encodes the most significant bit position of a bitfield.
290 Given a bitfield that spans bits [MSB, LSB], some operands of this type
291 encode MSB directly while others encode MSB - LSB. Each operand of this
292 type is preceded by an integer operand that specifies LSB.
294 The assembly form varies between instructions. For some instructions,
295 such as EXT, the operand is written as the bitfield size. For others,
296 such as EXTS, it is written in raw MSB - LSB form. */
297 struct mips_msb_operand
299 struct mips_operand root
;
301 /* The assembly-level operand encoded by a field value of 0. */
304 /* True if the operand encodes MSB directly, false if it encodes
308 /* The maximum value of MSB + 1. */
312 /* Describes a single register operand. */
313 struct mips_reg_operand
315 struct mips_operand root
;
317 /* The type of register. */
318 enum mips_reg_operand_type reg_type
;
320 /* If nonnull, REG_MAP[N] gives the register associated with encoding N,
321 otherwise the encoding is the same as the register number. */
322 const unsigned char *reg_map
;
325 /* Describes an operand that which must match a condition based on the
327 struct mips_check_prev_operand
329 struct mips_operand root
;
331 bool greater_than_ok
;
337 /* Describes an operand that encodes a pair of registers. */
338 struct mips_reg_pair_operand
340 struct mips_operand root
;
342 /* The type of register. */
343 enum mips_reg_operand_type reg_type
;
345 /* Encoding N represents REG1_MAP[N], REG2_MAP[N]. */
346 unsigned char *reg1_map
;
347 unsigned char *reg2_map
;
350 /* Describes an operand that is calculated relative to a base PC.
351 The base PC is usually the address of the following instruction,
352 but the rules for MIPS16 instructions like ADDIUPC are more complicated. */
353 struct mips_pcrel_operand
355 /* Encodes the offset. */
356 struct mips_int_operand root
;
358 /* The low ALIGN_LOG2 bits of the base PC are cleared to give PC',
359 which is then added to the offset encoded by ROOT. */
360 unsigned int align_log2
: 8;
362 /* If INCLUDE_ISA_BIT, the ISA bit of the original base PC is then
363 reinstated. This is true for jumps and branches and false for
364 PC-relative data instructions. */
365 unsigned int include_isa_bit
: 1;
367 /* If FLIP_ISA_BIT, the ISA bit of the result is inverted.
368 This is true for JALX and false otherwise. */
369 unsigned int flip_isa_bit
: 1;
372 /* Return true if the assembly syntax allows OPERAND to be omitted. */
375 mips_optional_operand_p (const struct mips_operand
*operand
)
377 return (operand
->type
== OP_OPTIONAL_REG
378 || operand
->type
== OP_REPEAT_PREV_REG
);
381 /* Return a version of INSN in which the field specified by OPERAND
384 static inline unsigned int
385 mips_insert_operand (const struct mips_operand
*operand
, unsigned int insn
,
390 mask
= (1 << operand
->size
) - 1;
391 insn
&= ~(mask
<< operand
->lsb
);
392 insn
|= (uval
& mask
) << operand
->lsb
;
396 /* Extract OPERAND from instruction INSN. */
398 static inline unsigned int
399 mips_extract_operand (const struct mips_operand
*operand
, unsigned int insn
)
401 return (insn
>> operand
->lsb
) & ((1 << operand
->size
) - 1);
404 /* UVAL is the value encoded by OPERAND. Return it in signed form. */
407 mips_signed_operand (const struct mips_operand
*operand
, unsigned int uval
)
409 unsigned int sign_bit
, mask
;
411 mask
= (1 << operand
->size
) - 1;
412 sign_bit
= 1 << (operand
->size
- 1);
413 return ((uval
+ sign_bit
) & mask
) - sign_bit
;
416 /* Return the integer that OPERAND encodes as UVAL. */
419 mips_decode_int_operand (const struct mips_int_operand
*operand
,
422 uval
|= (operand
->max_val
- uval
) & -(1 << operand
->root
.size
);
423 uval
+= operand
->bias
;
424 uval
<<= operand
->shift
;
428 /* Return the maximum value that can be encoded by OPERAND. */
431 mips_int_operand_max (const struct mips_int_operand
*operand
)
433 return (operand
->max_val
+ operand
->bias
) << operand
->shift
;
436 /* Return the minimum value that can be encoded by OPERAND. */
439 mips_int_operand_min (const struct mips_int_operand
*operand
)
443 mask
= (1 << operand
->root
.size
) - 1;
444 return mips_int_operand_max (operand
) - (mask
<< operand
->shift
);
447 /* Return the register that OPERAND encodes as UVAL. */
450 mips_decode_reg_operand (const struct mips_reg_operand
*operand
,
453 if (operand
->reg_map
)
454 uval
= operand
->reg_map
[uval
];
458 /* PC-relative operand OPERAND has value UVAL and is relative to BASE_PC.
459 Return the address that it encodes. */
461 static inline bfd_vma
462 mips_decode_pcrel_operand (const struct mips_pcrel_operand
*operand
,
463 bfd_vma base_pc
, unsigned int uval
)
467 addr
= base_pc
& -(1 << operand
->align_log2
);
468 addr
+= mips_decode_int_operand (&operand
->root
, uval
);
469 if (operand
->include_isa_bit
)
471 if (operand
->flip_isa_bit
)
476 /* This structure holds information for a particular instruction. */
480 /* The name of the instruction. */
482 /* A string describing the arguments for this instruction. */
484 /* The basic opcode for the instruction. When assembling, this
485 opcode is modified by the arguments to produce the actual opcode
486 that is used. If pinfo is INSN_MACRO, then this is 0. */
488 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
489 relevant portions of the opcode when disassembling. If the
490 actual opcode anded with the match field equals the opcode field,
491 then we have found the correct instruction. If pinfo is
492 INSN_MACRO, then this field is the macro identifier. */
494 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
495 of bits describing the instruction, notably any relevant hazard
498 /* A collection of additional bits describing the instruction. */
499 unsigned long pinfo2
;
500 /* A collection of bits describing the instruction sets of which this
501 instruction or macro is a member. */
502 unsigned long membership
;
503 /* A collection of bits describing the ASE of which this instruction
504 or macro is a member. */
506 /* A collection of bits describing the instruction sets of which this
507 instruction or macro is not a member. */
508 unsigned long exclusions
;
511 /* Return true if MO is an instruction that requires 32-bit encoding. */
514 mips_opcode_32bit_p (const struct mips_opcode
*mo
)
516 return mo
->mask
>> 16 != 0;
519 /* These are the characters which may appear in the args field of a
520 regular MIPS instruction. They appear in the order in which the fields
521 appear when the instruction is used. Commas and parentheses in the
522 args string are ignored when assembling, and written into the output
525 "1" 5-bit SYNC type at bit 6.
526 "<" 5-bit shift amount at bit 6 (SHAMT).
527 ">" Shift amount between 32 and 63, stored after subtracting 32, at bit 6
529 "a" 26-bit target address at bit 0 (TARGET).
530 "+i" Likewise, but flips bit 0.
531 "b" 5-bit base register at bit 21 (RS).
532 "c" 10-bit breakpoint code at bit 16.
533 "d" 5-bit destination register at bit 11 (RD).
534 "h" 5-bit PREFX hint at bit 11.
535 "i" 16-bit unsigned immediate at bit 0 (IMMEDIATE).
536 "j" 16-bit signed immediate at bit 0 (DELTA).
537 "k" 5-bit CACHE opcode in target register position at bit 16.
538 "o" 16-bit signed offset at bit 0 (DELTA).
539 "p" 16-bit PC relative branch target address at bit 0 (DELTA).
540 "q" 10-bit extra breakpoint code at bit 6.
541 "r" 5-bit same register used as both source and target at bit 21 (RS).
542 "s" 5-bit source register at bit 21 (RS).
543 "t" 5-bit target register at bit 16 (RT).
544 "u" 16-bit upper 16 bits of address at bit 0 (IMMEDIATE).
545 "v" 5-bit same register used as both source and destination at bit 21 (RS).
546 "w" 5-bit same register used as both target and destination at bit 16 (RT).
547 "U" 5-bit same destination register at both bit 11 and 16 (both RD and RT)
548 (used by CLO and CLZ).
549 "C" 25-bit coprocessor function code at bit 0.
550 "B" 20-bit syscall/breakpoint function code at bit 6.
551 "J" 19-bit WAIT function code at bit 6.
552 "x" Accept and ignore register name.
553 "z" Must be zero register.
554 "K" 5-bit Hardware Register (RDHWR instruction) at bit 11 (RD).
555 "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position at bit 6,
556 which becomes LSB (SHAMT).
557 Enforces: 0 <= pos < 32.
558 "+B" 5-bit INS/DINS size at bit 11, which becomes MSB.
559 Requires that "+A" or "+E" occur first to set position.
560 Enforces: 0 < (pos+size) <= 32.
561 "+C" 5-bit EXT/DEXT size at bit 11, which becomes MSBD.
562 Requires that "+A" or "+E" occur first to set position.
563 Enforces: 0 < (pos+size) <= 32.
564 (Also used by DEXT w/ different limits, but limits for
565 that are checked by the M_DEXT macro.)
566 "+E" 5-bit DINSU/DEXTU position at bit 6, which becomes LSB-32 (SHAMT).
567 Enforces: 32 <= pos < 64.
568 "+F" 5-bit DINSM/DINSU size at bit 11, which becomes MSB-32.
569 Requires that "+A" or "+E" occur first to set position.
570 Enforces: 32 < (pos+size) <= 64.
571 "+G" 5-bit DEXTM size at bit 11, which becomes MSBD-32.
572 Requires that "+A" or "+E" occur first to set position.
573 Enforces: 32 < (pos+size) <= 64.
574 "+H" 5-bit DEXTU size at bit 11, which becomes MSBD.
575 Requires that "+A" or "+E" occur first to set position.
576 Enforces: 32 < (pos+size) <= 64.
578 Floating point instructions:
579 "D" 5-bit destination register at bit 6 (FD).
580 "M" 3-bit compare condition code at bit 8 (only used for mips4 and up).
581 "N" 3-bit branch condition code at bit 18 (only used for mips4 and up).
582 "S" 5-bit fs source 1 register at bit 11 (FS).
583 "T" 5-bit ft source 2 register at bit 16 (FT).
584 "R" 5-bit fr source 3 register at bit 21 (FR).
585 "V" 5-bit same register used as floating source and destination at bit 11
587 "W" 5-bit same register used as floating target and destination at bit 16
590 Coprocessor instructions:
591 "E" 5-bit target register at bit 16 (RT).
592 "G" 5-bit destination register at bit 11 (RD).
593 "H" 3-bit sel field for (D)MTC* and (D)MFC* at bit 0.
594 "P" 5-bit performance-monitor register at bit 1.
595 "e" 3-bit vector register byte specifier at bit 22.
596 "g" 5-bit control destination register at bit 11 (RD).
597 "%" 3-bit immediate vr5400 vector alignment operand at bit 21.
600 "A" General 32-bit expression.
601 "I" 32-bit immediate (value placed in imm_expr).
602 "F" 64-bit floating point constant in .rdata.
603 "L" 64-bit floating point constant in .lit8.
604 "f" 32-bit floating point constant.
605 "l" 32-bit floating point constant in .lit4.
607 MDMX and VR5400 instruction operands (note that while these use the
608 FP register fields, the MDMX instructions accept both $fN and $vN names
610 "O" 3-bit alignment offset at bit 21.
611 "Q" 10-bit vector/scalar/immediate source at bit 16.
612 "X" 5-bit destination register at bit 6 (FD).
613 "Y" 5-bit source register at bit 11 (FS).
614 "Z" 5-bit source register at bit 16 (FT).
616 R5900 VU0 Macromode instructions:
617 "+5" 5-bit floating point register at bit 6 (FD).
618 "+6" 5-bit floating point register at bit 11 (FS).
619 "+7" 5-bit floating point register at bit 16 (FT).
620 "+8" 5-bit integer register at bit 6 (FD).
621 "+9" 5-bit integer register at bit 11 (FS).
622 "+0" 5-bit integer register at bit 16 (FT).
623 "+K" Match an existing 4-bit channel mask starting at bit 21.
624 "+L" 2-bit channel index starting at bit 21.
625 "+M" 2-bit channel index starting at bit 23.
626 "+N" Match an existing 2-bit channel index starting at bit 0.
627 "+f" 15-bit immediate for VCALLMS at bit 6.
628 "+g" 5-bit signed immediate for VIADDI at bit 6.
629 "+m" $ACC register (syntax only).
630 "+q" $Q register (syntax only).
631 "+r" $R register (syntax only).
632 "+y" $I register (syntax only).
633 "#+" "++" decorator in ($reg++) sequence.
634 "#-" "--" decorator in (--$reg) sequence.
637 "2" 2-bit unsigned immediate for byte align at bit 11.
638 "3" 3-bit unsigned immediate at bit 21.
639 "4" 4-bit unsigned immediate at bit 21.
640 "5" 8-bit unsigned immediate at bit 16.
641 "6" 5-bit unsigned immediate at bit 21 (RS).
642 "7" 2-bit DSP accumulator register at bit 11.
643 "8" 6-bit unsigned immediate at bit 11.
644 "9" 2-bit DSP accumulator register at bit 21.
645 "0" 6-bit signed immediate at bit 20.
646 ":" 7-bit signed immediate at bit 19.
647 "'" 6-bit unsigned immediate at bit 16.
648 "@" 10-bit signed immediate at bit 16.
651 "!" 1-bit usermode flag at bit 5.
652 "$" 1-bit load high flag at bit 4.
653 "*" 2-bit DSP/SmartMIPS accumulator register at bit 18.
654 "&" 2-bit DSP/SmartMIPS accumulator register at bit 13.
655 "y" 5-bit control target register at bit 16 (RT).
658 "~" 12-bit offset at bit 0.
659 "\" 3-bit position for ASET and ACLR at bit 12.
662 "+J" 10-bit HYPCALL code at bit 11.
665 "+1" UDI immediate bits 6-10.
666 "+2" UDI immediate bits 6-15.
667 "+3" UDI immediate bits 6-20.
668 "+4" UDI immediate bits 6-25.
671 "+x" Bit index field of BBITx at bit 16.
672 Enforces: 0 <= index < 32.
673 "+X" Bit index field of BBITx aliasing BBITx32 at bit 16.
674 Matches if 32 <= index < 64, otherwise skips to next candidate.
675 "+p" Position field of CINS/CINS32/EXTS/EXTS32 at bit 6.
676 Enforces 0 <= pos < 32.
677 "+P" Position field of CINS/EXTS aliasing CINS32/EXTS32 at bit 6.
678 Matches if 32 <= pos < 64, otherwise skips to next candidate.
679 "+Q" Immediate field of SEQI/SNEI at bit 6.
680 Enforces -512 <= imm < 512.
681 "+s" Length-minus-one field of CINS32/EXTS32 at bit 11.
682 Requires MSB position of the field to be <= 31.
683 "+S" Length-minus-one field of CINS/EXTS at bit 11.
684 Requires MSB position of the field to be <= 63.
687 "+a" 8-bit signed offset at bit 6.
688 "+b" 8-bit signed offset at bit 3.
689 "+c" 9-bit signed offset at bit 6.
690 "+z" 5-bit rz register at bit 0.
691 "+Z" 5-bit fz register at bit 0.
694 "-m" Register list for SAVE/RESTORE instruction.
697 "+j" 9-bit signed offset at bit 7.
700 "+d" 5-bit MSA register at bit 6 (FD).
701 "+e" 5-bit MSA register at bit 11 (FS).
702 "+h" 5-bit MSA register at bit 16 (FT).
703 "+k" 5-bit GPR at bit 6.
704 "+l" 5-bit MSA control register at bit 6.
705 "+n" 5-bit MSA control register at bit 11.
706 "+o" 4-bit vector element index at bit 16.
707 "+u" 3-bit vector element index at bit 16.
708 "+v" 2-bit vector element index at bit 16.
709 "+w" 1-bit vector element index at bit 16.
710 "+T" (-512 .. 511) << 0 at bit 16.
711 "+U" (-512 .. 511) << 1 at bit 16.
712 "+V" (-512 .. 511) << 2 at bit 16.
713 "+W" (-512 .. 511) << 3 at bit 16.
714 "+~" 2-bit LSA/DLSA shift amount from 1 to 4 at bit 6.
715 "+!" 3-bit unsigned bit position at bit 16.
716 "+@" 4-bit unsigned bit position at bit 16.
717 "+#" 6-bit unsigned bit position at bit 16.
718 "+$" 5-bit unsigned immediate at bit 16.
719 "+%" 5-bit signed immediate at bit 16.
720 "+^" 10-bit signed immediate at bit 11.
721 "+&" 0 vector element index.
722 "+*" 5-bit register vector element index at bit 16.
723 "+|" 8-bit mask at bit 16.
726 "+:" 11-bit mask at bit 0.
727 "+'" 26-bit PC relative branch target address at bit 0.
728 "+"" 21-bit PC relative branch target address at bit 0.
729 "+;" 5-bit same register at both bit 16 and 21 (both RT and RS).
730 "+I" 2-bit unsigned bit position at bit 6.
731 "+O" 3-bit unsigned bit position at bit 6.
732 "+R" Must be program counter.
733 "-a" (-262144 .. 262143) << 2 at bit 0.
734 "-b" (-131072 .. 131071) << 3 at bit 0.
735 "-d" Same as destination register GP.
736 "-s" 5-bit source register at bit 21 (RS) not $0.
737 "-t" 5-bit target register at bit 16 (RT) not $0
738 "-u" 5-bit target register at bit 16 (RT) greater than RS.
739 "-v" 5-bit target register at bit 16 (RT) not $0 not RS.
740 "-w" 5-bit target register at bit 16 (RT) less than or equal to RS.
741 "-x" 5-bit source register at bit 21 (RS) greater than RT.
742 "-y" 5-bit source register at bit 21 (RS) not $0 less than RT.
743 "-A" Symbolic offset (-262144 .. 262143) << 2 at bit 0.
744 "-B" Symbolic offset (-131072 .. 131071) << 3 at bit 0.
747 "+\" 2-bit Global TLB invalidate type at bit 8.
750 "()" Parens surrounding optional value.
751 "," Separates operands.
752 "+" Start of extension sequence.
753 "-" Start of extension sequence.
755 Characters used so far, for quick reference when adding more:
757 "%[]<>(),+-:'@!#$*&\~"
758 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
759 "abcdef hijkl opqrstuvwxyz"
761 Extension character sequences used so far ("+" followed by the
762 following), for quick reference when adding more:
765 "ABC EFGHIJKLMNOPQRSTUVWX Z"
766 "abcdefghijklmnopqrs uvwxyz"
768 Extension character sequences used so far ("-" followed by the
769 following), for quick reference when adding more:
774 /* These are the bits which may be set in the pinfo field of an
775 instructions, if it is not equal to INSN_MACRO. */
777 /* Writes to operand number N. */
778 #define INSN_WRITE_SHIFT 0
779 #define INSN_WRITE_1 0x00000001
780 #define INSN_WRITE_2 0x00000002
781 #define INSN_WRITE_ALL 0x00000003
782 /* Reads from operand number N. */
783 #define INSN_READ_SHIFT 2
784 #define INSN_READ_1 0x00000004
785 #define INSN_READ_2 0x00000008
786 #define INSN_READ_3 0x00000010
787 #define INSN_READ_4 0x00000020
788 #define INSN_READ_ALL 0x0000003c
789 /* Modifies general purpose register 31. */
790 #define INSN_WRITE_GPR_31 0x00000040
791 /* Modifies coprocessor condition code. */
792 #define INSN_WRITE_COND_CODE 0x00000080
793 /* Reads coprocessor condition code. */
794 #define INSN_READ_COND_CODE 0x00000100
796 #define INSN_TLB 0x00000200
797 /* Reads coprocessor register other than floating point register. */
798 #define INSN_COP 0x00000400
799 /* Instruction loads value from memory. */
800 #define INSN_LOAD_MEMORY 0x00000800
801 /* Instruction loads value from coprocessor, (may require delay). */
802 #define INSN_LOAD_COPROC 0x00001000
803 /* Instruction has unconditional branch delay slot. */
804 #define INSN_UNCOND_BRANCH_DELAY 0x00002000
805 /* Instruction has conditional branch delay slot. */
806 #define INSN_COND_BRANCH_DELAY 0x00004000
807 /* Conditional branch likely: if branch not taken, insn nullified. */
808 #define INSN_COND_BRANCH_LIKELY 0x00008000
809 /* Moves to coprocessor register, (may require delay). */
810 #define INSN_COPROC_MOVE 0x00010000
811 /* Loads coprocessor register from memory, requiring delay. */
812 #define INSN_COPROC_MEMORY_DELAY 0x00020000
813 /* Reads the HI register. */
814 #define INSN_READ_HI 0x00040000
815 /* Reads the LO register. */
816 #define INSN_READ_LO 0x00080000
817 /* Modifies the HI register. */
818 #define INSN_WRITE_HI 0x00100000
819 /* Modifies the LO register. */
820 #define INSN_WRITE_LO 0x00200000
821 /* Not to be placed in a branch delay slot, either architecturally
822 or for ease of handling (such as with instructions that take a trap). */
823 #define INSN_NO_DELAY_SLOT 0x00400000
824 /* Instruction stores value into memory. */
825 #define INSN_STORE_MEMORY 0x00800000
826 /* Instruction uses single precision floating point. */
827 #define FP_S 0x01000000
828 /* Instruction uses double precision floating point. */
829 #define FP_D 0x02000000
830 /* Instruction is part of the tx39's integer multiply family. */
831 #define INSN_MULT 0x04000000
832 /* Reads general purpose register 24. */
833 #define INSN_READ_GPR_24 0x08000000
834 /* Writes to general purpose register 24. */
835 #define INSN_WRITE_GPR_24 0x10000000
836 /* A user-defined instruction. */
837 #define INSN_UDI 0x20000000
838 /* Instruction is actually a macro. It should be ignored by the
839 disassembler, and requires special treatment by the assembler. */
840 #define INSN_MACRO 0xffffffff
842 /* These are the bits which may be set in the pinfo2 field of an
845 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
846 #define INSN2_ALIAS 0x00000001
847 /* Instruction reads MDMX accumulator. */
848 #define INSN2_READ_MDMX_ACC 0x00000002
849 /* Instruction writes MDMX accumulator. */
850 #define INSN2_WRITE_MDMX_ACC 0x00000004
851 /* Macro uses single-precision floating-point instructions. This should
852 only be set for macros. For instructions, FP_S in pinfo carries the
854 #define INSN2_M_FP_S 0x00000008
855 /* Macro uses double-precision floating-point instructions. This should
856 only be set for macros. For instructions, FP_D in pinfo carries the
858 #define INSN2_M_FP_D 0x00000010
859 /* Instruction has a branch delay slot that requires a 16-bit instruction. */
860 #define INSN2_BRANCH_DELAY_16BIT 0x00000020
861 /* Instruction has a branch delay slot that requires a 32-bit instruction. */
862 #define INSN2_BRANCH_DELAY_32BIT 0x00000040
863 /* Writes to the stack pointer ($29). */
864 #define INSN2_WRITE_SP 0x00000080
865 /* Reads from the stack pointer ($29). */
866 #define INSN2_READ_SP 0x00000100
867 /* Reads the RA ($31) register. */
868 #define INSN2_READ_GPR_31 0x00000200
869 /* Reads the program counter ($pc). */
870 #define INSN2_READ_PC 0x00000400
871 /* Is an unconditional branch insn. */
872 #define INSN2_UNCOND_BRANCH 0x00000800
873 /* Is a conditional branch insn. */
874 #define INSN2_COND_BRANCH 0x00001000
875 /* Reads from $16. This is true of the MIPS16 0x6500 nop. */
876 #define INSN2_READ_GPR_16 0x00002000
877 /* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask. */
878 #define INSN2_VU0_CHANNEL_SUFFIX 0x00004000
879 /* Instruction has a forbidden slot. */
880 #define INSN2_FORBIDDEN_SLOT 0x00008000
881 /* Opcode table entry is for a short MIPS16 form only. An extended
882 encoding may still exist, but with a separate opcode table entry
883 required. In disassembly the presence of this flag in an otherwise
884 successful match against an extended instruction encoding inhibits
885 matching against any subsequent short table entry even if it does
886 not have this flag set. A table entry matching the full extended
887 encoding is needed or otherwise the final EXTEND entry will apply,
888 for the disassembly of the prefix only. */
889 #define INSN2_SHORT_ONLY 0x00010000
891 /* Masks used to mark instructions to indicate which MIPS ISA level
892 they were introduced in. INSN_ISA_MASK masks an enumeration that
893 specifies the base ISA level(s). The remainder of a 32-bit
894 word constructed using these macros is a bitmask of the remaining
895 INSN_* values below, as indicated by INSN_CHIP_MASK. */
897 #define INSN_ISA_MASK 0x0000001ful
899 /* We cannot start at zero due to ISA_UNKNOWN below. */
906 #define INSN_ISA32R2 7
907 #define INSN_ISA32R3 8
908 #define INSN_ISA32R5 9
909 #define INSN_ISA32R6 10
910 #define INSN_ISA64 11
911 #define INSN_ISA64R2 12
912 #define INSN_ISA64R3 13
913 #define INSN_ISA64R5 14
914 #define INSN_ISA64R6 15
915 /* Below this point the INSN_* values correspond to combinations of ISAs.
916 They are only for use in the opcodes table to indicate membership of
917 a combination of ISAs that cannot be expressed using the usual inclusion
918 ordering on the above INSN_* values. */
919 #define INSN_ISA3_32 16
920 #define INSN_ISA3_32R2 17
921 #define INSN_ISA4_32 18
922 #define INSN_ISA4_32R2 19
923 #define INSN_ISA5_32R2 20
925 /* The R6 definitions shown below state that they support all previous ISAs.
926 This is not actually true as some instructions are removed in R6.
927 The problem is that the removed instructions in R6 come from different
928 ISAs. One approach to solve this would be to describe in the membership
929 field of the opcode table the different ISAs an instruction belongs to.
930 This would require us to create a large amount of different ISA
931 combinations which is hard to manage. A cleaner approach (which is
932 implemented here) is to say that R6 is an extension of R5 and then to
933 deal with the removed instructions by adding instruction exclusions
934 for R6 in the opcode table. */
936 /* Bit INSN_ISA<X> - 1 of INSN_UPTO<Y> is set if ISA Y includes ISA X. */
938 #define ISAF(X) (1 << (INSN_ISA##X - 1))
939 #define INSN_UPTO1 ISAF(1)
940 #define INSN_UPTO2 INSN_UPTO1 | ISAF(2)
941 #define INSN_UPTO3 INSN_UPTO2 | ISAF(3) | ISAF(3_32) | ISAF(3_32R2)
942 #define INSN_UPTO4 INSN_UPTO3 | ISAF(4) | ISAF(4_32) | ISAF(4_32R2)
943 #define INSN_UPTO5 INSN_UPTO4 | ISAF(5) | ISAF(5_32R2)
944 #define INSN_UPTO32 INSN_UPTO2 | ISAF(32) | ISAF(3_32) | ISAF(4_32)
945 #define INSN_UPTO32R2 INSN_UPTO32 | ISAF(32R2) \
946 | ISAF(3_32R2) | ISAF(4_32R2) | ISAF(5_32R2)
947 #define INSN_UPTO32R3 INSN_UPTO32R2 | ISAF(32R3)
948 #define INSN_UPTO32R5 INSN_UPTO32R3 | ISAF(32R5)
949 #define INSN_UPTO32R6 INSN_UPTO32R5 | ISAF(32R6)
950 #define INSN_UPTO64 INSN_UPTO5 | ISAF(64) | ISAF(32)
951 #define INSN_UPTO64R2 INSN_UPTO64 | ISAF(64R2) | ISAF(32R2)
952 #define INSN_UPTO64R3 INSN_UPTO64R2 | ISAF(64R3) | ISAF(32R3)
953 #define INSN_UPTO64R5 INSN_UPTO64R3 | ISAF(64R5) | ISAF(32R5)
954 #define INSN_UPTO64R6 INSN_UPTO64R5 | ISAF(64R6) | ISAF(32R6)
956 /* The same information in table form: bit INSN_ISA<X> - 1 of index
957 INSN_UPTO<Y> - 1 is set if ISA Y includes ISA X. */
958 static const unsigned int mips_isa_table
[] = {
977 /* Masks used for Chip specific instructions. */
978 #define INSN_CHIP_MASK 0x01ffffe0
980 /* MIPS R4650 instruction. */
981 #define INSN_4650 0x00000020
982 /* LSI R4010 instruction. */
983 #define INSN_4010 0x00000040
984 /* NEC VR4100 instruction. */
985 #define INSN_4100 0x00000080
986 /* Toshiba R3900 instruction. */
987 #define INSN_3900 0x00000100
988 /* MIPS R10000 instruction. */
989 #define INSN_10000 0x00000200
990 /* Broadcom SB-1 instruction. */
991 #define INSN_SB1 0x00000400
992 /* NEC VR4111/VR4181 instruction. */
993 #define INSN_4111 0x00000800
994 /* NEC VR4120 instruction. */
995 #define INSN_4120 0x00001000
996 /* NEC VR5400 instruction. */
997 #define INSN_5400 0x00002000
998 /* NEC VR5500 instruction. */
999 #define INSN_5500 0x00004000
1000 /* MIPS R5900 instruction. */
1001 #define INSN_5900 0x00008000
1002 /* ST Microelectronics Loongson 2E. */
1003 #define INSN_LOONGSON_2E 0x00010000
1004 /* ST Microelectronics Loongson 2F. */
1005 #define INSN_LOONGSON_2F 0x00020000
1006 /* Cavium Networks Octeon instructions. */
1007 #define INSN_OCTEON 0x00040000
1008 #define INSN_OCTEONP 0x00080000
1009 #define INSN_OCTEON2 0x00100000
1010 #define INSN_OCTEON3 0x00200000
1011 /* RMI XLR instruction. */
1012 #define INSN_XLR 0x00400000
1013 /* Imagination interAptiv MR2. */
1014 #define INSN_INTERAPTIV_MR2 0x00800000
1015 /* Sony PSP Allegrex instruction. */
1016 #define INSN_ALLEGREX 0x01000000
1019 #define ASE_DSP 0x00000001
1020 #define ASE_DSP64 0x00000002
1022 #define ASE_DSPR2 0x00000004
1023 /* Enhanced VA Scheme */
1024 #define ASE_EVA 0x00000008
1025 /* MCU (MicroController) ASE */
1026 #define ASE_MCU 0x00000010
1028 #define ASE_MDMX 0x00000020
1030 #define ASE_MIPS3D 0x00000040
1032 #define ASE_MT 0x00000080
1034 #define ASE_SMARTMIPS 0x00000100
1035 /* Virtualization ASE */
1036 #define ASE_VIRT 0x00000200
1037 #define ASE_VIRT64 0x00000400
1039 #define ASE_MSA 0x00000800
1040 #define ASE_MSA64 0x00001000
1041 /* eXtended Physical Address (XPA) Extension. */
1042 #define ASE_XPA 0x00002000
1043 /* DSP R3 Module. */
1044 #define ASE_DSPR3 0x00004000
1046 #define ASE_MIPS16E2 0x00008000
1047 /* MIPS16e2 MT ASE instructions. */
1048 #define ASE_MIPS16E2_MT 0x00010000
1049 /* The Virtualization ASE has eXtended Physical Addressing (XPA)
1050 instructions which are only valid when both ASEs are enabled. */
1051 #define ASE_XPA_VIRT 0x00020000
1052 /* Cyclic redundancy check (CRC) ASE. */
1053 #define ASE_CRC 0x00040000
1054 #define ASE_CRC64 0x00080000
1055 /* Global INValidate Extension. */
1056 #define ASE_GINV 0x00100000
1057 /* Loongson MultiMedia extensions Instructions (MMI). */
1058 #define ASE_LOONGSON_MMI 0x00200000
1059 /* Loongson Content Address Memory (CAM). */
1060 #define ASE_LOONGSON_CAM 0x00400000
1061 /* Loongson EXTensions (EXT) instructions. */
1062 #define ASE_LOONGSON_EXT 0x00800000
1063 /* Loongson EXTensions R2 (EXT2) instructions. */
1064 #define ASE_LOONGSON_EXT2 0x01000000
1065 /* The Enhanced VA Scheme (EVA) extension has instructions which are
1066 only valid for the R6 ISA. */
1067 #define ASE_EVA_R6 0x02000000
1069 /* MIPS ISA defines, use instead of hardcoding ISA level. */
1071 #define ISA_UNKNOWN 0 /* Gas internal use. */
1072 #define ISA_MIPS1 INSN_ISA1
1073 #define ISA_MIPS2 INSN_ISA2
1074 #define ISA_MIPS3 INSN_ISA3
1075 #define ISA_MIPS4 INSN_ISA4
1076 #define ISA_MIPS5 INSN_ISA5
1078 #define ISA_MIPS32 INSN_ISA32
1079 #define ISA_MIPS64 INSN_ISA64
1081 #define ISA_MIPS32R2 INSN_ISA32R2
1082 #define ISA_MIPS32R3 INSN_ISA32R3
1083 #define ISA_MIPS32R5 INSN_ISA32R5
1084 #define ISA_MIPS64R2 INSN_ISA64R2
1085 #define ISA_MIPS64R3 INSN_ISA64R3
1086 #define ISA_MIPS64R5 INSN_ISA64R5
1088 #define ISA_MIPS32R6 INSN_ISA32R6
1089 #define ISA_MIPS64R6 INSN_ISA64R6
1091 /* CPU defines, use instead of hardcoding processor number. Keep this
1092 in sync with bfd/archures.c in order for machine selection to work. */
1093 #define CPU_UNKNOWN 0 /* Gas internal use. */
1094 #define CPU_R3000 3000
1095 #define CPU_R3900 3900
1096 #define CPU_R4000 4000
1097 #define CPU_R4010 4010
1098 #define CPU_VR4100 4100
1099 #define CPU_R4111 4111
1100 #define CPU_VR4120 4120
1101 #define CPU_R4300 4300
1102 #define CPU_R4400 4400
1103 #define CPU_R4600 4600
1104 #define CPU_R4650 4650
1105 #define CPU_R5000 5000
1106 #define CPU_VR5400 5400
1107 #define CPU_VR5500 5500
1108 #define CPU_R5900 5900
1109 #define CPU_R6000 6000
1110 #define CPU_RM7000 7000
1111 #define CPU_R8000 8000
1112 #define CPU_RM9000 9000
1113 #define CPU_R10000 10000
1114 #define CPU_R12000 12000
1115 #define CPU_R14000 14000
1116 #define CPU_R16000 16000
1117 #define CPU_MIPS16 16
1118 #define CPU_MIPS32 32
1119 #define CPU_MIPS32R2 33
1120 #define CPU_MIPS32R3 34
1121 #define CPU_MIPS32R5 36
1122 #define CPU_MIPS32R6 37
1124 #define CPU_MIPS64 64
1125 #define CPU_MIPS64R2 65
1126 #define CPU_MIPS64R3 66
1127 #define CPU_MIPS64R5 68
1128 #define CPU_MIPS64R6 69
1129 #define CPU_ALLEGREX 10111431 /* octal 'AL', 31. */
1130 #define CPU_SB1 12310201 /* octal 'SB', 01. */
1131 #define CPU_LOONGSON_2E 3001
1132 #define CPU_LOONGSON_2F 3002
1133 #define CPU_GS464 3003
1134 #define CPU_GS464E 3004
1135 #define CPU_GS264E 3005
1136 #define CPU_OCTEON 6501
1137 #define CPU_OCTEONP 6601
1138 #define CPU_OCTEON2 6502
1139 #define CPU_OCTEON3 6503
1140 #define CPU_XLR 887682 /* decimal 'XLR' */
1141 #define CPU_INTERAPTIV_MR2 736550 /* decimal 'IA2' */
1143 /* Return true if the given CPU is included in INSN_* mask MASK. */
1146 cpu_is_member (int cpu
, unsigned int mask
)
1153 return (mask
& INSN_4650
) != 0;
1156 return (mask
& INSN_4010
) != 0;
1159 return (mask
& INSN_4100
) != 0;
1162 return (mask
& INSN_3900
) != 0;
1168 return (mask
& INSN_10000
) != 0;
1171 return (mask
& INSN_SB1
) != 0;
1174 return (mask
& INSN_4111
) != 0;
1177 return (mask
& INSN_4120
) != 0;
1180 return (mask
& INSN_5400
) != 0;
1183 return (mask
& INSN_5500
) != 0;
1186 return (mask
& INSN_5900
) != 0;
1188 case CPU_LOONGSON_2E
:
1189 return (mask
& INSN_LOONGSON_2E
) != 0;
1191 case CPU_LOONGSON_2F
:
1192 return (mask
& INSN_LOONGSON_2F
) != 0;
1195 return (mask
& INSN_OCTEON
) != 0;
1198 return (mask
& INSN_OCTEONP
) != 0;
1201 return (mask
& INSN_OCTEON2
) != 0;
1204 return (mask
& INSN_OCTEON3
) != 0;
1207 return (mask
& INSN_XLR
) != 0;
1209 case CPU_INTERAPTIV_MR2
:
1210 return (mask
& INSN_INTERAPTIV_MR2
) != 0;
1213 return (mask
& INSN_ALLEGREX
) != 0;
1220 /* Return true if the given ISA is included in INSN_* mask MASK. */
1223 isa_is_member (int isa
, unsigned int mask
)
1225 isa
&= INSN_ISA_MASK
;
1226 mask
&= INSN_ISA_MASK
;
1234 if (((mips_isa_table
[isa
- 1] >> (mask
- 1)) & 1) == 0)
1240 /* Test for membership in an ISA including chip specific ISAs. INSN
1241 is pointer to an element of the opcode table; ISA is the specified
1242 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
1243 test, or zero if no CPU specific ISA test is desired. Return true
1244 if instruction INSN is available to the given ISA and CPU. */
1247 opcode_is_member (const struct mips_opcode
*insn
, int isa
, int ase
, int cpu
)
1249 /* Test for ISA level exclusion. */
1250 if (isa_is_member (isa
, insn
->exclusions
))
1253 /* Test for processor-specific exclusion. */
1254 if (cpu_is_member (cpu
, insn
->exclusions
))
1257 /* Test for ISA level compatibility. */
1258 if (isa_is_member (isa
, insn
->membership
))
1261 /* Test for ASE compatibility. */
1262 if ((ase
& insn
->ase
) != 0)
1265 /* Test for processor-specific extensions. */
1266 if (cpu_is_member (cpu
, insn
->membership
))
1272 /* This is a list of macro expanded instructions.
1274 _I appended means immediate
1275 _A appended means target address of a jump
1276 _AB appended means address with (possibly zero) base register
1277 _D appended means 64 bit floating point constant
1278 _S appended means 32 bit floating point constant. */
1537 /* The order of overloaded instructions matters. Label arguments and
1538 register arguments look the same. Instructions that can have either
1539 for arguments must apear in the correct order in this table for the
1540 assembler to pick the right one. In other words, entries with
1541 immediate operands must apear after the same instruction with
1544 Many instructions are short hand for other instructions (i.e., The
1545 jal <register> instruction is short for jalr <register>). */
1547 extern const struct mips_operand mips_vu0_channel_mask
;
1548 extern const struct mips_operand
*decode_mips_operand (const char *);
1549 extern const struct mips_opcode mips_builtin_opcodes
[];
1550 extern const int bfd_mips_num_builtin_opcodes
;
1551 extern struct mips_opcode
*mips_opcodes
;
1552 extern int bfd_mips_num_opcodes
;
1553 #define NUMOPCODES bfd_mips_num_opcodes
1556 /* The rest of this file adds definitions for the mips16 TinyRISC
1559 /* These are the bitmasks and shift counts used for the different
1560 fields in the instruction formats. Other than OP, no masks are
1561 provided for the fixed portions of an instruction, since they are
1564 The I format uses IMM11.
1566 The RI format uses RX and IMM8.
1568 The RR format uses RX, and RY.
1570 The RRI format uses RX, RY, and IMM5.
1572 The RRR format uses RX, RY, and RZ.
1574 The RRI_A format uses RX, RY, and IMM4.
1576 The SHIFT format uses RX, RY, and SHAMT.
1578 The I8 format uses IMM8.
1580 The I8_MOVR32 format uses RY and REGR32.
1582 The IR_MOV32R format uses REG32R and MOV32Z.
1584 The I64 format uses IMM8.
1586 The RI64 format uses RY and IMM5.
1589 #define MIPS16OP_MASK_RX 0x7
1590 #define MIPS16OP_SH_RX 8
1591 #define MIPS16OP_MASK_RY 0x7
1592 #define MIPS16OP_SH_RY 5
1593 #define MIPS16OP_MASK_RZ 0x7
1594 #define MIPS16OP_SH_RZ 2
1596 /* These are the characters which may appears in the args field of a
1597 MIPS16 instruction. They appear in the order in which the fields
1598 appear when the instruction is used. Commas and parentheses in the
1599 args string are ignored when assembling, and written into the output
1602 "y" 3-bit register at bit 5 (RY).
1603 "x" 3-bit register at bit 8 (RX).
1604 "z" 3-bit register at bit 2 (RZ).
1605 "Z" 3-bit register at bit 0 (MOV32Z).
1606 "v" 3-bit same register as source and destination at bit 8 (RX).
1607 "w" 3-bit same register as source and destination at bit 5 (RY).
1608 "." Zero register ($0).
1609 "S" Stack pointer ($sp or $29).
1610 "P" Program counter.
1611 "R" Return address register ($ra or $31).
1612 "X" 5-bit MIPS register at bit 0 (REGR32).
1613 "Y" 5-bit shuffled MIPS register at bit 3 (REG32R).
1614 "0" 5-bit ASMACRO p0 immediate.
1615 "1" 3-bit ASMACRO p1 immediate.
1616 "2" 3-bit ASMACRO p2 immediate.
1617 "3" 5-bit ASMACRO p3 immediate.
1618 "4" 3-bit ASMACRO p4 immediate.
1619 "6" 6-bit unsigned break code at bit 5.
1620 "a" 26-bit jump address.
1621 "i" Likewise, but flips bit 0.
1622 "e" 11-bit extension value.
1623 "l" Register list for ENTRY instruction.
1624 "L" Register list for EXIT instruction.
1625 ">" 5-bit SYNC code.
1626 "9" 9-bit signed immediate.
1627 "G" global pointer ($gp or $28).
1628 "N" 5-bit coprocessor register.
1629 "O" 3-bit sel field for MFC0/MTC0.
1630 "Q" 5-bit hardware register.
1631 "T" 5-bit CACHE opcode or PREF hint.
1632 "b" 5-bit INS/EXT position, which becomes LSB.
1633 Enforces: 0 <= pos < 32.
1634 "c" 5-bit INS size, which becomes MSB.
1635 Requires that "b" occurs first to set position.
1636 Enforces: 0 < (pos+size) <= 32.
1637 "d" 5-bit EXT size, which becomes MSBD.
1638 Requires that "b" occurs first to set position.
1639 Enforces: 0 < (pos+size) <= 32.
1640 "n" 2-bit immediate (1 .. 4).
1641 "o" 5-bit unsigned immediate * 16.
1643 "s" 3-bit ASMACRO select immediate.
1644 "u" 16-bit unsigned immediate.
1646 "I" An immediate value used for macros.
1648 The remaining codes may be extended. Except as otherwise noted,
1649 the full extended operand is a 16 bit signed value.
1650 "<" 3-bit unsigned shift count * 1 at bit 2 (SHAMT) (full 5-bit unsigned).
1651 "[" 3-bit unsigned shift count * 1 at bit 2 (SHAMT) (full 6-bit unsigned).
1652 "]" 3-bit unsigned shift count * 1 at bit 8 (RX) (full 6-bit unsigned).
1653 "5" 5-bit unsigned immediate * 1 at bit 0 (IMM5).
1654 "F" 4-bit signed immediate * 1 a bit 0 (IMM4) (full 15-bit signed).
1655 "H" 5-bit unsigned immediate * 2 at bit 0 (IMM5).
1656 "W" 5-bit unsigned immediate * 4 at bit 0 (IMM5).
1657 "D" 5-bit unsigned immediate * 8 at bit 0 (IMM5).
1658 "j" 5-bit signed immediate * 1 at bit 0 (IMM5).
1659 "8" 8-bit unsigned immediate * 1 at bit 0 (IMM8).
1660 "V" 8-bit unsigned immediate * 4 at bit 0 (IMM8).
1661 "C" 8-bit unsigned immediate * 8 at bit 0 (IMM8).
1662 "U" 8-bit unsigned immediate * 1 at bit 0 (IMM8) (full 16-bit unsigned).
1663 "k" 8-bit signed immediate * 1 at bit 0 (IMM8).
1664 "K" 8-bit signed immediate * 8 at bit 0 (IMM8).
1665 "p" 8-bit conditional branch address at bit 0 (IMM8).
1666 "q" 11-bit branch address at bit 0 (IMM11).
1667 "A" 8-bit PC relative address * 4 at bit 0 (IMM8).
1668 "B" 5-bit PC relative address * 8 at bit 0 (IMM5).
1669 "E" 5-bit PC relative address * 4 at bit 0 (IMM5).
1670 "m" 7-bit register list for SAVE/RESTORE instruction (18-bit extended).
1672 Characters used so far, for quick reference when adding more:
1675 "ABCDEFGHI KL NOPQRSTUVWXYZ"
1676 "abcde ijklmnopqrs uvwxyz"
1679 /* Save/restore encoding for the args field when all 4 registers are
1680 either saved as arguments or saved/restored as statics. */
1681 #define MIPS_SVRS_ALL_ARGS 0xe
1682 #define MIPS_SVRS_ALL_STATICS 0xb
1684 /* The following flags have the same value for the mips16 opcode
1689 INSN_UNCOND_BRANCH_DELAY
1690 INSN_COND_BRANCH_DELAY
1691 INSN_COND_BRANCH_LIKELY (never used)
1700 extern const struct mips_operand
*decode_mips16_operand (char, bool);
1701 extern const struct mips_opcode mips16_opcodes
[];
1702 extern const int bfd_mips16_num_opcodes
;
1704 /* These are the bit masks and shift counts used for the different fields
1705 in the microMIPS instruction formats. No masks are provided for the
1706 fixed portions of an instruction, since they are not needed. */
1708 #define MICROMIPSOP_MASK_RS 0x1f
1709 #define MICROMIPSOP_SH_RS 16
1710 #define MICROMIPSOP_MASK_RT 0x1f
1711 #define MICROMIPSOP_SH_RT 21
1712 #define MICROMIPSOP_MASK_RD 0x1f
1713 #define MICROMIPSOP_SH_RD 11
1714 #define MICROMIPSOP_MASK_BCC 0x7
1715 #define MICROMIPSOP_SH_BCC 18
1716 #define MICROMIPSOP_MASK_MD 0x7
1717 #define MICROMIPSOP_SH_MD 7
1718 #define MICROMIPSOP_MASK_MJ 0x1f
1719 #define MICROMIPSOP_SH_MJ 0
1721 /* These are the characters which may appears in the args field of a
1722 microMIPS instruction. They appear in the order in which the fields
1723 appear when the instruction is used. Commas and parentheses in the
1724 args string are ignored when assembling, and written into the output
1727 The followings are for 16-bit microMIPS instructions.
1730 "mc" 3-bit registers 2-7, 16, 17 at bit 4.
1731 The same register used as both source and target.
1732 "md" 3-bit registers 2-7, 16, 17 at bit 7.
1733 "me" 3-bit registers 2-7, 16, 17 at bit 1.
1734 The same register used as both source and target.
1735 "mf" 3-bit registers 2-7, 16, 17 at bit 3.
1736 "mg" 3-bit registers 2-7, 16, 17 at bit 0.
1737 "mh" 3-bit register pair at bit 7.
1738 "mj" 5-bit registers at bit 0.
1739 "ml" 3-bit registers 2-7, 16, 17 at bit 4.
1740 "mm" 3-bit registers 0, 2, 3, 16-20 at bit 1.
1741 "mn" 3-bit registers 0, 2, 3, 16-20 at bit 4.
1742 "mp" 5-bit registers at bit 5.
1743 "mq" 3-bit registers 0, 2-7, 17 at bit 7.
1744 "mr" Must be program counter.
1746 "mt" Must be the same as the previous register.
1747 "mx" Must be the same as the destination register.
1751 "mA" 7-bit immediate (-64 .. 63) << 2 at bit 0.
1752 "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) at bit 1.
1753 "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255,
1754 32768, 65535) at bit 0.
1755 "mD" 10-bit branch address (-512 .. 511) << 1 at bit 0.
1756 "mE" 7-bit branch address (-64 .. 63) << 1 at bit 0.
1757 "mF" 4-bit immediate (0 .. 15) at bit 0.
1758 "mG" 4-bit immediate (-1 .. 14) at bit 0.
1759 "mH" 4-bit immediate (0 .. 15) << 1 at bit 0.
1760 "mI" 7-bit immediate (-1 .. 126) at bit 0.
1761 "mJ" 4-bit immediate (0 .. 15) << 2 at bit 0.
1762 "mL" 4-bit immediate (0 .. 15) at bit 0.
1763 "mM" 3-bit immediate (1 .. 8) at bit 1.
1764 "mN" 2-bit immediate (0 .. 3) for register list at bit 4.
1765 "mO" 4-bit immediate (0 .. 15) at bit 0.
1766 "mP" 5-bit immediate (0 .. 31) << 2 at bit 0.
1767 "mU" 5-bit immediate (0 .. 31) << 2 at bit 0.
1768 "mW" 6-bit immediate (0 .. 63) << 2 at bit 1.
1769 "mX" 4-bit immediate (-8 .. 7) at bit 1.
1770 "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 at bit 1.
1773 In most cases 32-bit microMIPS instructions use the same characters
1774 as MIPS (with ADDIUPC being a notable exception, but there are some
1777 "." 10-bit signed offset/number at bit 6.
1778 "1" 5-bit SYNC type at bit 16.
1779 "<" 5-bit shift amount at bit 11.
1780 ">" Shift amount between 32 and 63, stored after subtracting 3, at bit 11.
1781 "\" 3-bit position for ASET and ACLR at bit 21.
1782 "|" 4-bit trap code at bit 12.
1783 "~" 12-bit signed offset at bit 0.
1784 "a" 26-bit target address at bit 0.
1785 "+i" Likewise, but flips bit 0.
1786 "b" 5-bit base register at bit 16 (RS).
1787 "c" 10-bit higher breakpoint code at bit 16.
1788 "d" 5-bit destination register at bit 11 (RD).
1789 "h" 5-bit PREFX hint at bit 11.
1790 "i" 16-bit unsigned immediate at bit 0.
1791 "j" 16-bit signed immediate at bit 0.
1792 "k" 5-bit CACHE opcode in target register position at bit 21.
1793 "n" 5-bit register list for 32-bit LWM/SWM instruction at bit 21 (RT).
1794 "o" 16-bit signed offset at bit 0.
1795 "p" 16-bit PC-relative branch target address at bit 0.
1796 "q" 10-bit lower breakpoint code at bit 6.
1797 "r" 5-bit same register used as both source and target at bit 16 (RS).
1798 "s" 5-bit source register at bit 16 (RS).
1799 "t" 5-bit target register at bit 21 (RT).
1800 "u" 16-bit upper 16 bits of address at bit 0.
1801 "v" 5-bit same register used as both source and destination at bit 16 (RS).
1802 "w" 5-bit same register used as both target and destination at bit 21 (RT).
1803 "x" 5-bit source 3 register for ALNV.PS at bit 6.
1804 "z" Must be zero register.
1805 "C" 23-bit coprocessor function code at bit 3.
1806 "K" 5-bit Hardware Register (RDHWR instruction) at bit 16 (RS).
1808 "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position at bit 6,
1810 Enforces: 0 <= pos < 32.
1811 "+B" 5-bit INS/DINS size at bit 11, which becomes MSB.
1812 Requires that "+A" or "+E" occur first to set position.
1813 Enforces: 0 < (pos+size) <= 32.
1814 "+C" 5-bit EXT/DEXT size at bit 11, which becomes MSBD.
1815 Requires that "+A" or "+E" occur first to set position.
1816 Enforces: 0 < (pos+size) <= 32.
1817 (Also used by DEXT w/ different limits, but limits for
1818 that are checked by the M_DEXT macro.)
1819 "+E" 5-bit DINSU/DEXTU position at bit 6, which becomes LSB-32.
1820 Enforces: 32 <= pos < 64.
1821 "+F" 5-bit DINSM/DINSU size at bit 11., which becomes MSB-32.
1822 Requires that "+A" or "+E" occur first to set position.
1823 Enforces: 32 < (pos+size) <= 64.
1824 "+G" 5-bit DEXTM size at bit 11, which becomes MSBD-32.
1825 Requires that "+A" or "+E" occur first to set position.
1826 Enforces: 32 < (pos+size) <= 64.
1827 "+H" 5-bit DEXTU size at bit 11, which becomes MSBD.
1828 Requires that "+A" or "+E" occur first to set position.
1829 Enforces: 32 < (pos+size) <= 64.
1830 "+J" 10-bit SYSCALL/WAIT/SDBBP/HYPCALL function code at bit 16.
1832 PC-relative addition (ADDIUPC) instruction:
1833 "mQ" 23-bit offset (-4194304 .. 4194303) << 2 at bit 0.
1834 "mb" 3-bit MIPS registers 2-7, 16, 17 at bit 23.
1836 Floating point instructions:
1837 "D" 5-bit destination register at bit 11 (FD).
1838 "M" 3-bit compare condition code at bit 13 (CCC).
1839 "N" 3-bit branch condition code at bit 18 (BCC).
1840 "R" 5-bit fr source 3 register at bit 6 (FR).
1841 "S" 5-bit fs source 1 register at bit 16 (FS).
1842 "T" 5-bit ft source 2 register at bit 21 (FT).
1843 "V" 5-bit same register used as floating source and destination or target
1846 Coprocessor instructions:
1847 "E" 5-bit target register at bit 21 (RT).
1848 "G" 5-bit source register at bit 16 (RS).
1849 "H" 3-bit sel field for (D)MTC* and (D)MFC* at bit 11.
1850 "g" 5-bit control source register at bit 16 (RS).
1853 "A" General 32-bit expression.
1854 "I" 32-bit immediate (value placed in imm_expr).
1855 "F" 64-bit floating point constant in .rdata.
1856 "L" 64-bit floating point constant in .lit8.
1857 "f" 32-bit floating point constant.
1858 "l" 32-bit floating point constant in .lit4.
1861 "2" 2-bit unsigned immediate for byte align at bit 14.
1862 "3" 3-bit unsigned immediate at bit 13.
1863 "4" 4-bit unsigned immediate at bit 12.
1864 "5" 8-bit unsigned immediate at bit 13.
1865 "6" 5-bit unsigned immediate at bit 16 (RS).
1866 "7" 2-bit DSP accumulator register at bit 14.
1867 "8" 6-bit unsigned immediate at bit 14.
1868 "0" 6-bit signed immediate at bit 16.
1869 "@" 10-bit signed immediate at bit 16.
1870 "^" 5-bit unsigned immediate at bit 11 (RD).
1872 microMIPS Enhanced VA Scheme:
1873 "+j" 9-bit signed offset in bit 0.
1876 "+d" 5-bit MSA register at bit 6 (FD).
1877 "+e" 5-bit MSA register at bit 11 (FS).
1878 "+h" 5-bit MSA register at bit 16 (FT).
1879 "+k" 5-bit GPR at bit 6.
1880 "+l" 5-bit MSA control register at bit 6.
1881 "+n" 5-bit MSA control register at bit 11.
1882 "+o" 4-bit vector element index at bit 16.
1883 "+u" 3-bit vector element index at bit 16.
1884 "+v" 2-bit vector element index at bit 16.
1885 "+w" 1-bit vector element index at bit 16.
1886 "+x" 5-bit shift amount at bit 16.
1887 "+T" (-512 .. 511) << 0 at bit 16.
1888 "+U" (-512 .. 511) << 1 at bit 16.
1889 "+V" (-512 .. 511) << 2 at bit 16.
1890 "+W" (-512 .. 511) << 3 at bit 16.
1891 "+~" 2-bit LSA/DLSA shift amount from 1 to 4 at bit 6.
1892 "+!" 3-bit unsigned bit position at bit 16.
1893 "+@" 4-bit unsigned bit position at bit 16.
1894 "+#" 6-bit unsigned bit position at bit 16.
1895 "+$" 5-bit unsigned immediate at bit 16.
1896 "+%" 5-bit signed immediate at bit 16.
1897 "+^" 10-bit signed immediate at bit 11.
1898 "+&" 0 vector element index.
1899 "+*" 5-bit register vector element index at bit 16.
1900 "+|" 8-bit mask at bit 16.
1903 "!" 1-bit usermode flag at bit 10.
1904 "$" 1-bit load high flag at bit 9.
1905 "*" 2-bit DSP accumulator register at bit 23.
1906 "&" 2-bit DSP accumulator register at bit 18.
1907 "J" 3-bit MFTR and MTTR sel at bit 4.
1908 "y" 5-bit control target register at bit 21 (RT).
1911 "()" Parens surrounding optional value.
1912 "," Separates operands.
1913 "m" Start of microMIPS extension sequence.
1914 "+" Start of extension sequence.
1915 "-" Start of extension sequence.
1917 Characters used so far, for quick reference when adding more:
1920 "ABCDEFGHIJKLMN RST V "
1921 "abcd fghijklmnopqrstuvwxyz"
1923 Extension character sequences used so far ("m" followed by the
1924 following), for quick reference when adding more:
1927 " BCDEFGHIJ LMNOPQ U WXYZ"
1928 " bcdefghij lmn pq st xyz"
1930 Extension character sequences used so far ("+" followed by the
1931 following), for quick reference when adding more:
1935 " de hijkl no uvwx "
1937 Extension character sequences used so far ("-" followed by the
1938 following), for quick reference when adding more:
1944 extern const struct mips_operand
*decode_micromips_operand (const char *);
1945 extern const struct mips_opcode micromips_opcodes
[];
1946 extern const int bfd_micromips_num_opcodes
;
1948 /* A NOP insn impemented as "or at,at,zero".
1949 Used to implement -mfix-loongson2f. */
1950 #define LOONGSON2F_NOP_INSN 0x00200825
1956 #endif /* _MIPS_H_ */