include/pcmcia.h

   1 /*
   2  * (C) Copyright 2000-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _PCMCIA_H
   9 #define _PCMCIA_H
  10
  11 #include <common.h>
  12 #include <config.h>
  13
  14 /*
  15  * Allow configuration to select PCMCIA slot,
  16  * or try to generate a useful default
  17  */
  18 #if defined(CONFIG_CMD_PCMCIA) || \
  19     (defined(CONFIG_CMD_IDE) && \
  20         (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) )
  21
  22 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
  23
  24 #if defined(CONFIG_TQM8xxL)
  25 # define        CONFIG_PCMCIA_SLOT_B    /* The TQM8xxL use SLOT_B       */
  26 #elif defined(CONFIG_SPD823TS)          /* The SPD8xx  use SLOT_B       */
  27 # define CONFIG_PCMCIA_SLOT_B
  28 #elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)   /* The IVM* use SLOT_A  */
  29 # define CONFIG_PCMCIA_SLOT_A
  30 #elif defined(CONFIG_LWMON)             /* The LWMON  use SLOT_B        */
  31 # define CONFIG_PCMCIA_SLOT_B
  32 #elif defined(CONFIG_R360MPI)           /* The R360MPI use SLOT_B       */
  33 # define CONFIG_PCMCIA_SLOT_B
  34 #elif defined(CONFIG_ATC)               /* The ATC use SLOT_A   */
  35 # define CONFIG_PCMCIA_SLOT_A
  36 #elif defined(CONFIG_UC100)             /* The UC100 use SLOT_B         */
  37 # define CONFIG_PCMCIA_SLOT_B
  38 #else
  39 # error "PCMCIA Slot not configured"
  40 #endif
  41
  42 #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
  43
  44 /* Make sure exactly one slot is defined - we support only one for now */
  45 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
  46 #error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured
  47 #endif
  48 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
  49 #error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured
  50 #endif
  51
  52 #ifndef PCMCIA_SOCKETS_NO
  53 #define PCMCIA_SOCKETS_NO       1
  54 #endif
  55 #ifndef PCMCIA_MEM_WIN_NO
  56 #define PCMCIA_MEM_WIN_NO       4
  57 #endif
  58 #define PCMCIA_IO_WIN_NO        2
  59
  60 /* define _slot_ to be able to optimize macros */
  61 #ifdef CONFIG_PCMCIA_SLOT_A
  62 # define _slot_                 0
  63 # define PCMCIA_SLOT_MSG        "slot A"
  64 # define PCMCIA_SLOT_x          PCMCIA_PSLOT_A
  65 #else
  66 # define _slot_                 1
  67 # define PCMCIA_SLOT_MSG        "slot B"
  68 # define PCMCIA_SLOT_x          PCMCIA_PSLOT_B
  69 #endif
  70
  71 /*
  72  * The TQM850L hardware has two pins swapped! Grrrrgh!
  73  */
  74 #ifdef  CONFIG_TQM850L
  75 #define __MY_PCMCIA_GCRX_CXRESET        PCMCIA_GCRX_CXOE
  76 #define __MY_PCMCIA_GCRX_CXOE           PCMCIA_GCRX_CXRESET
  77 #else
  78 #define __MY_PCMCIA_GCRX_CXRESET        PCMCIA_GCRX_CXRESET
  79 #define __MY_PCMCIA_GCRX_CXOE           PCMCIA_GCRX_CXOE
  80 #endif
  81
  82 /*
  83  * This structure is used to address each window in the PCMCIA controller.
  84  *
  85  * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly
  86  * after pcmcia_win_t[n]...
  87  */
  88
  89 typedef struct {
  90         ulong   br;
  91         ulong   or;
  92 } pcmcia_win_t;
  93
  94 /*
  95  * Definitions for PCMCIA control registers to operate in IDE mode
  96  *
  97  * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL)
  98  * to be done later (depending on CPU clock)
  99  */
 100
 101 /* Window 0:
 102  *      Base: 0xFE100000        CS1
 103  *      Port Size:     2 Bytes
 104  *      Port Size:    16 Bit
 105  *      Common Memory Space
 106  */
 107
 108 #define CONFIG_SYS_PCMCIA_PBR0          0xFE100000
 109 #define CONFIG_SYS_PCMCIA_POR0      (   PCMCIA_BSIZE_2  \
 110                             |   PCMCIA_PPS_16   \
 111                             |   PCMCIA_PRS_MEM  \
 112                             |   PCMCIA_SLOT_x   \
 113                             |   PCMCIA_PV       \
 114                             )
 115
 116 /* Window 1:
 117  *      Base: 0xFE100080        CS1
 118  *      Port Size:     8 Bytes
 119  *      Port Size:     8 Bit
 120  *      Common Memory Space
 121  */
 122
 123 #define CONFIG_SYS_PCMCIA_PBR1          0xFE100080
 124 #define CONFIG_SYS_PCMCIA_POR1      (   PCMCIA_BSIZE_8  \
 125                             |   PCMCIA_PPS_8    \
 126                             |   PCMCIA_PRS_MEM  \
 127                             |   PCMCIA_SLOT_x   \
 128                             |   PCMCIA_PV       \
 129                             )
 130
 131 /* Window 2:
 132  *      Base: 0xFE100100        CS2
 133  *      Port Size:     8 Bytes
 134  *      Port Size:     8 Bit
 135  *      Common Memory Space
 136  */
 137
 138 #define CONFIG_SYS_PCMCIA_PBR2          0xFE100100
 139 #define CONFIG_SYS_PCMCIA_POR2      (   PCMCIA_BSIZE_8  \
 140                             |   PCMCIA_PPS_8    \
 141                             |   PCMCIA_PRS_MEM  \
 142                             |   PCMCIA_SLOT_x   \
 143                             |   PCMCIA_PV       \
 144                             )
 145
 146 /* Window 3:
 147  *      not used
 148  */
 149 #define CONFIG_SYS_PCMCIA_PBR3          0
 150 #define CONFIG_SYS_PCMCIA_POR3          0
 151
 152 /* Window 4:
 153  *      Base: 0xFE100C00        CS1
 154  *      Port Size:     2 Bytes
 155  *      Port Size:    16 Bit
 156  *      Common Memory Space
 157  */
 158
 159 #define CONFIG_SYS_PCMCIA_PBR4          0xFE100C00
 160 #define CONFIG_SYS_PCMCIA_POR4      (   PCMCIA_BSIZE_2  \
 161                             |   PCMCIA_PPS_16   \
 162                             |   PCMCIA_PRS_MEM  \
 163                             |   PCMCIA_SLOT_x   \
 164                             |   PCMCIA_PV       \
 165                             )
 166
 167 /* Window 5:
 168  *      Base: 0xFE100C80        CS1
 169  *      Port Size:     8 Bytes
 170  *      Port Size:     8 Bit
 171  *      Common Memory Space
 172  */
 173
 174 #define CONFIG_SYS_PCMCIA_PBR5          0xFE100C80
 175 #define CONFIG_SYS_PCMCIA_POR5      (   PCMCIA_BSIZE_8  \
 176                             |   PCMCIA_PPS_8    \
 177                             |   PCMCIA_PRS_MEM  \
 178                             |   PCMCIA_SLOT_x   \
 179                             |   PCMCIA_PV       \
 180                             )
 181
 182 /* Window 6:
 183  *      Base: 0xFE100D00        CS2
 184  *      Port Size:     8 Bytes
 185  *      Port Size:     8 Bit
 186  *      Common Memory Space
 187  */
 188
 189 #define CONFIG_SYS_PCMCIA_PBR6          0xFE100D00
 190 #define CONFIG_SYS_PCMCIA_POR6      (   PCMCIA_BSIZE_8  \
 191                             |   PCMCIA_PPS_8    \
 192                             |   PCMCIA_PRS_MEM  \
 193                             |   PCMCIA_SLOT_x   \
 194                             |   PCMCIA_PV       \
 195                             )
 196
 197 /* Window 7:
 198  *      not used
 199  */
 200 #define CONFIG_SYS_PCMCIA_PBR7          0
 201 #define CONFIG_SYS_PCMCIA_POR7          0
 202
 203 /**********************************************************************/
 204
 205 /*
 206  * CIS Tupel codes
 207  */
 208 #define CISTPL_NULL             0x00
 209 #define CISTPL_DEVICE           0x01
 210 #define CISTPL_LONGLINK_CB      0x02
 211 #define CISTPL_INDIRECT         0x03
 212 #define CISTPL_CONFIG_CB        0x04
 213 #define CISTPL_CFTABLE_ENTRY_CB 0x05
 214 #define CISTPL_LONGLINK_MFC     0x06
 215 #define CISTPL_BAR              0x07
 216 #define CISTPL_PWR_MGMNT        0x08
 217 #define CISTPL_EXTDEVICE        0x09
 218 #define CISTPL_CHECKSUM         0x10
 219 #define CISTPL_LONGLINK_A       0x11
 220 #define CISTPL_LONGLINK_C       0x12
 221 #define CISTPL_LINKTARGET       0x13
 222 #define CISTPL_NO_LINK          0x14
 223 #define CISTPL_VERS_1           0x15
 224 #define CISTPL_ALTSTR           0x16
 225 #define CISTPL_DEVICE_A         0x17
 226 #define CISTPL_JEDEC_C          0x18
 227 #define CISTPL_JEDEC_A          0x19
 228 #define CISTPL_CONFIG           0x1a
 229 #define CISTPL_CFTABLE_ENTRY    0x1b
 230 #define CISTPL_DEVICE_OC        0x1c
 231 #define CISTPL_DEVICE_OA        0x1d
 232 #define CISTPL_DEVICE_GEO       0x1e
 233 #define CISTPL_DEVICE_GEO_A     0x1f
 234 #define CISTPL_MANFID           0x20
 235 #define CISTPL_FUNCID           0x21
 236 #define CISTPL_FUNCE            0x22
 237 #define CISTPL_SWIL             0x23
 238 #define CISTPL_END              0xff
 239
 240 /*
 241  * CIS Function ID codes
 242  */
 243 #define CISTPL_FUNCID_MULTI     0x00
 244 #define CISTPL_FUNCID_MEMORY    0x01
 245 #define CISTPL_FUNCID_SERIAL    0x02
 246 #define CISTPL_FUNCID_PARALLEL  0x03
 247 #define CISTPL_FUNCID_FIXED     0x04
 248 #define CISTPL_FUNCID_VIDEO     0x05
 249 #define CISTPL_FUNCID_NETWORK   0x06
 250 #define CISTPL_FUNCID_AIMS      0x07
 251 #define CISTPL_FUNCID_SCSI      0x08
 252
 253 /*
 254  * Fixed Disk FUNCE codes
 255  */
 256 #define CISTPL_IDE_INTERFACE    0x01
 257
 258 #define CISTPL_FUNCE_IDE_IFACE  0x01
 259 #define CISTPL_FUNCE_IDE_MASTER 0x02
 260 #define CISTPL_FUNCE_IDE_SLAVE  0x03
 261
 262 /* First feature byte */
 263 #define CISTPL_IDE_SILICON      0x04
 264 #define CISTPL_IDE_UNIQUE       0x08
 265 #define CISTPL_IDE_DUAL         0x10
 266
 267 /* Second feature byte */
 268 #define CISTPL_IDE_HAS_SLEEP    0x01
 269 #define CISTPL_IDE_HAS_STANDBY  0x02
 270 #define CISTPL_IDE_HAS_IDLE     0x04
 271 #define CISTPL_IDE_LOW_POWER    0x08
 272 #define CISTPL_IDE_REG_INHIBIT  0x10
 273 #define CISTPL_IDE_HAS_INDEX    0x20
 274 #define CISTPL_IDE_IOIS16       0x40
 275
 276 #endif
 277
 278 #ifdef  CONFIG_8xx
 279 extern u_int *pcmcia_pgcrx[];
 280 #define PCMCIA_PGCRX(slot)      (*pcmcia_pgcrx[slot])
 281 #endif
 282
 283 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
 284 extern int check_ide_device(int slot);
 285 #endif
 286
 287 #endif /* _PCMCIA_H */