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git.ipfire.org Git - people/ms/u-boot.git/blob - include/pcmcia.h
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
15 * Allow configuration to select PCMCIA slot,
16 * or try to generate a useful default
18 #if defined(CONFIG_CMD_PCMCIA) || \
19 (defined(CONFIG_CMD_IDE) && \
20 (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) )
22 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
24 #if defined(CONFIG_TQM8xxL)
25 # define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */
27 # error "PCMCIA Slot not configured"
30 #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
32 /* Make sure exactly one slot is defined - we support only one for now */
33 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
34 #error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured
36 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
37 #error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured
40 #ifndef PCMCIA_SOCKETS_NO
41 #define PCMCIA_SOCKETS_NO 1
43 #ifndef PCMCIA_MEM_WIN_NO
44 #define PCMCIA_MEM_WIN_NO 4
46 #define PCMCIA_IO_WIN_NO 2
48 /* define _slot_ to be able to optimize macros */
49 #ifdef CONFIG_PCMCIA_SLOT_A
51 # define PCMCIA_SLOT_MSG "slot A"
52 # define PCMCIA_SLOT_x PCMCIA_PSLOT_A
55 # define PCMCIA_SLOT_MSG "slot B"
56 # define PCMCIA_SLOT_x PCMCIA_PSLOT_B
60 * The TQM850L hardware has two pins swapped! Grrrrgh!
63 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE
64 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET
66 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET
67 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE
71 * This structure is used to address each window in the PCMCIA controller.
73 * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly
74 * after pcmcia_win_t[n]...
83 * Definitions for PCMCIA control registers to operate in IDE mode
85 * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL)
86 * to be done later (depending on CPU clock)
90 * Base: 0xFE100000 CS1
96 #define CONFIG_SYS_PCMCIA_PBR0 0xFE100000
97 #define CONFIG_SYS_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \
105 * Base: 0xFE100080 CS1
108 * Common Memory Space
111 #define CONFIG_SYS_PCMCIA_PBR1 0xFE100080
112 #define CONFIG_SYS_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \
120 * Base: 0xFE100100 CS2
123 * Common Memory Space
126 #define CONFIG_SYS_PCMCIA_PBR2 0xFE100100
127 #define CONFIG_SYS_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \
137 #define CONFIG_SYS_PCMCIA_PBR3 0
138 #define CONFIG_SYS_PCMCIA_POR3 0
141 * Base: 0xFE100C00 CS1
144 * Common Memory Space
147 #define CONFIG_SYS_PCMCIA_PBR4 0xFE100C00
148 #define CONFIG_SYS_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \
156 * Base: 0xFE100C80 CS1
159 * Common Memory Space
162 #define CONFIG_SYS_PCMCIA_PBR5 0xFE100C80
163 #define CONFIG_SYS_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \
171 * Base: 0xFE100D00 CS2
174 * Common Memory Space
177 #define CONFIG_SYS_PCMCIA_PBR6 0xFE100D00
178 #define CONFIG_SYS_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \
188 #define CONFIG_SYS_PCMCIA_PBR7 0
189 #define CONFIG_SYS_PCMCIA_POR7 0
191 /**********************************************************************/
196 #define CISTPL_NULL 0x00
197 #define CISTPL_DEVICE 0x01
198 #define CISTPL_LONGLINK_CB 0x02
199 #define CISTPL_INDIRECT 0x03
200 #define CISTPL_CONFIG_CB 0x04
201 #define CISTPL_CFTABLE_ENTRY_CB 0x05
202 #define CISTPL_LONGLINK_MFC 0x06
203 #define CISTPL_BAR 0x07
204 #define CISTPL_PWR_MGMNT 0x08
205 #define CISTPL_EXTDEVICE 0x09
206 #define CISTPL_CHECKSUM 0x10
207 #define CISTPL_LONGLINK_A 0x11
208 #define CISTPL_LONGLINK_C 0x12
209 #define CISTPL_LINKTARGET 0x13
210 #define CISTPL_NO_LINK 0x14
211 #define CISTPL_VERS_1 0x15
212 #define CISTPL_ALTSTR 0x16
213 #define CISTPL_DEVICE_A 0x17
214 #define CISTPL_JEDEC_C 0x18
215 #define CISTPL_JEDEC_A 0x19
216 #define CISTPL_CONFIG 0x1a
217 #define CISTPL_CFTABLE_ENTRY 0x1b
218 #define CISTPL_DEVICE_OC 0x1c
219 #define CISTPL_DEVICE_OA 0x1d
220 #define CISTPL_DEVICE_GEO 0x1e
221 #define CISTPL_DEVICE_GEO_A 0x1f
222 #define CISTPL_MANFID 0x20
223 #define CISTPL_FUNCID 0x21
224 #define CISTPL_FUNCE 0x22
225 #define CISTPL_SWIL 0x23
226 #define CISTPL_END 0xff
229 * CIS Function ID codes
231 #define CISTPL_FUNCID_MULTI 0x00
232 #define CISTPL_FUNCID_MEMORY 0x01
233 #define CISTPL_FUNCID_SERIAL 0x02
234 #define CISTPL_FUNCID_PARALLEL 0x03
235 #define CISTPL_FUNCID_FIXED 0x04
236 #define CISTPL_FUNCID_VIDEO 0x05
237 #define CISTPL_FUNCID_NETWORK 0x06
238 #define CISTPL_FUNCID_AIMS 0x07
239 #define CISTPL_FUNCID_SCSI 0x08
242 * Fixed Disk FUNCE codes
244 #define CISTPL_IDE_INTERFACE 0x01
246 #define CISTPL_FUNCE_IDE_IFACE 0x01
247 #define CISTPL_FUNCE_IDE_MASTER 0x02
248 #define CISTPL_FUNCE_IDE_SLAVE 0x03
250 /* First feature byte */
251 #define CISTPL_IDE_SILICON 0x04
252 #define CISTPL_IDE_UNIQUE 0x08
253 #define CISTPL_IDE_DUAL 0x10
255 /* Second feature byte */
256 #define CISTPL_IDE_HAS_SLEEP 0x01
257 #define CISTPL_IDE_HAS_STANDBY 0x02
258 #define CISTPL_IDE_HAS_IDLE 0x04
259 #define CISTPL_IDE_LOW_POWER 0x08
260 #define CISTPL_IDE_REG_INHIBIT 0x10
261 #define CISTPL_IDE_HAS_INDEX 0x20
262 #define CISTPL_IDE_IOIS16 0x40
267 extern u_int
*pcmcia_pgcrx
[];
268 #define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot])
271 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
272 extern int check_ide_device(int slot
);
275 #endif /* _PCMCIA_H */