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mpc8xx: remove netta, netta2, netphone board support
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1 /*
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #ifndef _PCMCIA_H
9 #define _PCMCIA_H
10
11 #include <common.h>
12 #include <config.h>
13
14 /*
15 * Allow configuration to select PCMCIA slot,
16 * or try to generate a useful default
17 */
18 #if defined(CONFIG_CMD_PCMCIA) || \
19 (defined(CONFIG_CMD_IDE) && \
20 (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) )
21
22 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
23
24 #if defined(CONFIG_FADS) /* The FADS series are a mess */
25 # if defined(CONFIG_MPC86x) || defined(CONFIG_MPC821)
26 # define CONFIG_PCMCIA_SLOT_A
27 # else
28 # define CONFIG_PCMCIA_SLOT_B
29 # endif
30 #elif defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx)
31 # define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */
32 #elif defined(CONFIG_SPD823TS) /* The SPD8xx use SLOT_B */
33 # define CONFIG_PCMCIA_SLOT_B
34 #elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) /* The IVM* use SLOT_A */
35 # define CONFIG_PCMCIA_SLOT_A
36 #elif defined(CONFIG_LWMON) /* The LWMON use SLOT_B */
37 # define CONFIG_PCMCIA_SLOT_B
38 #elif defined(CONFIG_ICU862) /* The ICU862 use SLOT_B */
39 # define CONFIG_PCMCIA_SLOT_B
40 #elif defined(CONFIG_R360MPI) /* The R360MPI use SLOT_B */
41 # define CONFIG_PCMCIA_SLOT_B
42 #elif defined(CONFIG_ATC) /* The ATC use SLOT_A */
43 # define CONFIG_PCMCIA_SLOT_A
44 #elif defined(CONFIG_UC100) /* The UC100 use SLOT_B */
45 # define CONFIG_PCMCIA_SLOT_B
46 #else
47 # error "PCMCIA Slot not configured"
48 #endif
49
50 #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
51
52 /* Make sure exactly one slot is defined - we support only one for now */
53 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
54 #error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured
55 #endif
56 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
57 #error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured
58 #endif
59
60 #ifndef PCMCIA_SOCKETS_NO
61 #define PCMCIA_SOCKETS_NO 1
62 #endif
63 #ifndef PCMCIA_MEM_WIN_NO
64 #define PCMCIA_MEM_WIN_NO 4
65 #endif
66 #define PCMCIA_IO_WIN_NO 2
67
68 /* define _slot_ to be able to optimize macros */
69 #ifdef CONFIG_PCMCIA_SLOT_A
70 # define _slot_ 0
71 # define PCMCIA_SLOT_MSG "slot A"
72 # define PCMCIA_SLOT_x PCMCIA_PSLOT_A
73 #else
74 # define _slot_ 1
75 # define PCMCIA_SLOT_MSG "slot B"
76 # define PCMCIA_SLOT_x PCMCIA_PSLOT_B
77 #endif
78
79 /*
80 * The TQM850L hardware has two pins swapped! Grrrrgh!
81 */
82 #ifdef CONFIG_TQM850L
83 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE
84 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET
85 #else
86 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET
87 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE
88 #endif
89
90 /*
91 * This structure is used to address each window in the PCMCIA controller.
92 *
93 * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly
94 * after pcmcia_win_t[n]...
95 */
96
97 typedef struct {
98 ulong br;
99 ulong or;
100 } pcmcia_win_t;
101
102 /*
103 * Definitions for PCMCIA control registers to operate in IDE mode
104 *
105 * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL)
106 * to be done later (depending on CPU clock)
107 */
108
109 /* Window 0:
110 * Base: 0xFE100000 CS1
111 * Port Size: 2 Bytes
112 * Port Size: 16 Bit
113 * Common Memory Space
114 */
115
116 #define CONFIG_SYS_PCMCIA_PBR0 0xFE100000
117 #define CONFIG_SYS_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \
118 | PCMCIA_PPS_16 \
119 | PCMCIA_PRS_MEM \
120 | PCMCIA_SLOT_x \
121 | PCMCIA_PV \
122 )
123
124 /* Window 1:
125 * Base: 0xFE100080 CS1
126 * Port Size: 8 Bytes
127 * Port Size: 8 Bit
128 * Common Memory Space
129 */
130
131 #define CONFIG_SYS_PCMCIA_PBR1 0xFE100080
132 #define CONFIG_SYS_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \
133 | PCMCIA_PPS_8 \
134 | PCMCIA_PRS_MEM \
135 | PCMCIA_SLOT_x \
136 | PCMCIA_PV \
137 )
138
139 /* Window 2:
140 * Base: 0xFE100100 CS2
141 * Port Size: 8 Bytes
142 * Port Size: 8 Bit
143 * Common Memory Space
144 */
145
146 #define CONFIG_SYS_PCMCIA_PBR2 0xFE100100
147 #define CONFIG_SYS_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \
148 | PCMCIA_PPS_8 \
149 | PCMCIA_PRS_MEM \
150 | PCMCIA_SLOT_x \
151 | PCMCIA_PV \
152 )
153
154 /* Window 3:
155 * not used
156 */
157 #define CONFIG_SYS_PCMCIA_PBR3 0
158 #define CONFIG_SYS_PCMCIA_POR3 0
159
160 /* Window 4:
161 * Base: 0xFE100C00 CS1
162 * Port Size: 2 Bytes
163 * Port Size: 16 Bit
164 * Common Memory Space
165 */
166
167 #define CONFIG_SYS_PCMCIA_PBR4 0xFE100C00
168 #define CONFIG_SYS_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \
169 | PCMCIA_PPS_16 \
170 | PCMCIA_PRS_MEM \
171 | PCMCIA_SLOT_x \
172 | PCMCIA_PV \
173 )
174
175 /* Window 5:
176 * Base: 0xFE100C80 CS1
177 * Port Size: 8 Bytes
178 * Port Size: 8 Bit
179 * Common Memory Space
180 */
181
182 #define CONFIG_SYS_PCMCIA_PBR5 0xFE100C80
183 #define CONFIG_SYS_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \
184 | PCMCIA_PPS_8 \
185 | PCMCIA_PRS_MEM \
186 | PCMCIA_SLOT_x \
187 | PCMCIA_PV \
188 )
189
190 /* Window 6:
191 * Base: 0xFE100D00 CS2
192 * Port Size: 8 Bytes
193 * Port Size: 8 Bit
194 * Common Memory Space
195 */
196
197 #define CONFIG_SYS_PCMCIA_PBR6 0xFE100D00
198 #define CONFIG_SYS_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \
199 | PCMCIA_PPS_8 \
200 | PCMCIA_PRS_MEM \
201 | PCMCIA_SLOT_x \
202 | PCMCIA_PV \
203 )
204
205 /* Window 7:
206 * not used
207 */
208 #define CONFIG_SYS_PCMCIA_PBR7 0
209 #define CONFIG_SYS_PCMCIA_POR7 0
210
211 /**********************************************************************/
212
213 /*
214 * CIS Tupel codes
215 */
216 #define CISTPL_NULL 0x00
217 #define CISTPL_DEVICE 0x01
218 #define CISTPL_LONGLINK_CB 0x02
219 #define CISTPL_INDIRECT 0x03
220 #define CISTPL_CONFIG_CB 0x04
221 #define CISTPL_CFTABLE_ENTRY_CB 0x05
222 #define CISTPL_LONGLINK_MFC 0x06
223 #define CISTPL_BAR 0x07
224 #define CISTPL_PWR_MGMNT 0x08
225 #define CISTPL_EXTDEVICE 0x09
226 #define CISTPL_CHECKSUM 0x10
227 #define CISTPL_LONGLINK_A 0x11
228 #define CISTPL_LONGLINK_C 0x12
229 #define CISTPL_LINKTARGET 0x13
230 #define CISTPL_NO_LINK 0x14
231 #define CISTPL_VERS_1 0x15
232 #define CISTPL_ALTSTR 0x16
233 #define CISTPL_DEVICE_A 0x17
234 #define CISTPL_JEDEC_C 0x18
235 #define CISTPL_JEDEC_A 0x19
236 #define CISTPL_CONFIG 0x1a
237 #define CISTPL_CFTABLE_ENTRY 0x1b
238 #define CISTPL_DEVICE_OC 0x1c
239 #define CISTPL_DEVICE_OA 0x1d
240 #define CISTPL_DEVICE_GEO 0x1e
241 #define CISTPL_DEVICE_GEO_A 0x1f
242 #define CISTPL_MANFID 0x20
243 #define CISTPL_FUNCID 0x21
244 #define CISTPL_FUNCE 0x22
245 #define CISTPL_SWIL 0x23
246 #define CISTPL_END 0xff
247
248 /*
249 * CIS Function ID codes
250 */
251 #define CISTPL_FUNCID_MULTI 0x00
252 #define CISTPL_FUNCID_MEMORY 0x01
253 #define CISTPL_FUNCID_SERIAL 0x02
254 #define CISTPL_FUNCID_PARALLEL 0x03
255 #define CISTPL_FUNCID_FIXED 0x04
256 #define CISTPL_FUNCID_VIDEO 0x05
257 #define CISTPL_FUNCID_NETWORK 0x06
258 #define CISTPL_FUNCID_AIMS 0x07
259 #define CISTPL_FUNCID_SCSI 0x08
260
261 /*
262 * Fixed Disk FUNCE codes
263 */
264 #define CISTPL_IDE_INTERFACE 0x01
265
266 #define CISTPL_FUNCE_IDE_IFACE 0x01
267 #define CISTPL_FUNCE_IDE_MASTER 0x02
268 #define CISTPL_FUNCE_IDE_SLAVE 0x03
269
270 /* First feature byte */
271 #define CISTPL_IDE_SILICON 0x04
272 #define CISTPL_IDE_UNIQUE 0x08
273 #define CISTPL_IDE_DUAL 0x10
274
275 /* Second feature byte */
276 #define CISTPL_IDE_HAS_SLEEP 0x01
277 #define CISTPL_IDE_HAS_STANDBY 0x02
278 #define CISTPL_IDE_HAS_IDLE 0x04
279 #define CISTPL_IDE_LOW_POWER 0x08
280 #define CISTPL_IDE_REG_INHIBIT 0x10
281 #define CISTPL_IDE_HAS_INDEX 0x20
282 #define CISTPL_IDE_IOIS16 0x40
283
284 #endif
285
286 #ifdef CONFIG_8xx
287 extern u_int *pcmcia_pgcrx[];
288 #define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot])
289 #endif
290
291 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
292 extern int check_ide_device(int slot);
293 #endif
294
295 #endif /* _PCMCIA_H */