2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Andy Fleming <afleming@gmail.com>
5 * SPDX-License-Identifier: GPL-2.0+
7 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
13 #include <linux/list.h>
14 #include <linux/mii.h>
15 #include <linux/ethtool.h>
16 #include <linux/mdio.h>
18 #define PHY_MAX_ADDR 32
20 #define PHY_BASIC_FEATURES (SUPPORTED_10baseT_Half | \
21 SUPPORTED_10baseT_Full | \
22 SUPPORTED_100baseT_Half | \
23 SUPPORTED_100baseT_Full | \
28 #define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \
29 SUPPORTED_1000baseT_Half | \
30 SUPPORTED_1000baseT_Full)
32 #define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \
33 SUPPORTED_10000baseT_Full)
35 #ifndef PHY_ANEG_TIMEOUT
36 #define PHY_ANEG_TIMEOUT 4000
41 PHY_INTERFACE_MODE_MII
,
42 PHY_INTERFACE_MODE_GMII
,
43 PHY_INTERFACE_MODE_SGMII
,
44 PHY_INTERFACE_MODE_SGMII_2500
,
45 PHY_INTERFACE_MODE_QSGMII
,
46 PHY_INTERFACE_MODE_TBI
,
47 PHY_INTERFACE_MODE_RMII
,
48 PHY_INTERFACE_MODE_RGMII
,
49 PHY_INTERFACE_MODE_RGMII_ID
,
50 PHY_INTERFACE_MODE_RGMII_RXID
,
51 PHY_INTERFACE_MODE_RGMII_TXID
,
52 PHY_INTERFACE_MODE_RTBI
,
53 PHY_INTERFACE_MODE_XGMII
,
54 PHY_INTERFACE_MODE_NONE
/* Must be last */
57 static const char *phy_interface_strings
[] = {
58 [PHY_INTERFACE_MODE_MII
] = "mii",
59 [PHY_INTERFACE_MODE_GMII
] = "gmii",
60 [PHY_INTERFACE_MODE_SGMII
] = "sgmii",
61 [PHY_INTERFACE_MODE_SGMII_2500
] = "sgmii-2500",
62 [PHY_INTERFACE_MODE_QSGMII
] = "qsgmii",
63 [PHY_INTERFACE_MODE_TBI
] = "tbi",
64 [PHY_INTERFACE_MODE_RMII
] = "rmii",
65 [PHY_INTERFACE_MODE_RGMII
] = "rgmii",
66 [PHY_INTERFACE_MODE_RGMII_ID
] = "rgmii-id",
67 [PHY_INTERFACE_MODE_RGMII_RXID
] = "rgmii-rxid",
68 [PHY_INTERFACE_MODE_RGMII_TXID
] = "rgmii-txid",
69 [PHY_INTERFACE_MODE_RTBI
] = "rtbi",
70 [PHY_INTERFACE_MODE_XGMII
] = "xgmii",
71 [PHY_INTERFACE_MODE_NONE
] = "",
74 static inline const char *phy_string_for_interface(phy_interface_t i
)
76 /* Default to unknown */
77 if (i
> PHY_INTERFACE_MODE_NONE
)
78 i
= PHY_INTERFACE_MODE_NONE
;
80 return phy_interface_strings
[i
];
86 #define MDIO_NAME_LEN 32
89 struct list_head link
;
90 char name
[MDIO_NAME_LEN
];
92 int (*read
)(struct mii_dev
*bus
, int addr
, int devad
, int reg
);
93 int (*write
)(struct mii_dev
*bus
, int addr
, int devad
, int reg
,
95 int (*reset
)(struct mii_dev
*bus
);
96 struct phy_device
*phymap
[PHY_MAX_ADDR
];
100 /* struct phy_driver: a structure which defines PHY behavior
102 * uid will contain a number which represents the PHY. During
103 * startup, the driver will poll the PHY to find out what its
104 * UID--as defined by registers 2 and 3--is. The 32-bit result
105 * gotten from the PHY will be masked to
106 * discard any bits which may change based on revision numbers
107 * unimportant to functionality
118 /* Called to do any driver startup necessities */
119 /* Will be called during phy_connect */
120 int (*probe
)(struct phy_device
*phydev
);
122 /* Called to configure the PHY, and modify the controller
123 * based on the results. Should be called after phy_connect */
124 int (*config
)(struct phy_device
*phydev
);
126 /* Called when starting up the controller */
127 int (*startup
)(struct phy_device
*phydev
);
129 /* Called when bringing down the controller */
130 int (*shutdown
)(struct phy_device
*phydev
);
132 int (*readext
)(struct phy_device
*phydev
, int addr
, int devad
, int reg
);
133 int (*writeext
)(struct phy_device
*phydev
, int addr
, int devad
, int reg
,
135 struct list_head list
;
139 /* Information about the PHY type */
140 /* And management functions */
142 struct phy_driver
*drv
;
145 struct eth_device
*dev
;
147 /* forced speed & duplex (no autoneg)
148 * partner speed & duplex & pause (autoneg)
153 /* The most recently read link state */
156 phy_interface_t interface
;
178 static inline int phy_read(struct phy_device
*phydev
, int devad
, int regnum
)
180 struct mii_dev
*bus
= phydev
->bus
;
182 return bus
->read(bus
, phydev
->addr
, devad
, regnum
);
185 static inline int phy_write(struct phy_device
*phydev
, int devad
, int regnum
,
188 struct mii_dev
*bus
= phydev
->bus
;
190 return bus
->write(bus
, phydev
->addr
, devad
, regnum
, val
);
193 #ifdef CONFIG_PHYLIB_10G
194 extern struct phy_driver gen10g_driver
;
196 /* For now, XGMII is the only 10G interface */
197 static inline int is_10g_interface(phy_interface_t interface
)
199 return interface
== PHY_INTERFACE_MODE_XGMII
;
205 int phy_reset(struct phy_device
*phydev
);
206 struct phy_device
*phy_find_by_mask(struct mii_dev
*bus
, unsigned phy_mask
,
207 phy_interface_t interface
);
208 void phy_connect_dev(struct phy_device
*phydev
, struct eth_device
*dev
);
209 struct phy_device
*phy_connect(struct mii_dev
*bus
, int addr
,
210 struct eth_device
*dev
,
211 phy_interface_t interface
);
212 int phy_startup(struct phy_device
*phydev
);
213 int phy_config(struct phy_device
*phydev
);
214 int phy_shutdown(struct phy_device
*phydev
);
215 int phy_register(struct phy_driver
*drv
);
216 int genphy_config_aneg(struct phy_device
*phydev
);
217 int genphy_restart_aneg(struct phy_device
*phydev
);
218 int genphy_update_link(struct phy_device
*phydev
);
219 int genphy_parse_link(struct phy_device
*phydev
);
220 int genphy_config(struct phy_device
*phydev
);
221 int genphy_startup(struct phy_device
*phydev
);
222 int genphy_shutdown(struct phy_device
*phydev
);
223 int gen10g_config(struct phy_device
*phydev
);
224 int gen10g_startup(struct phy_device
*phydev
);
225 int gen10g_shutdown(struct phy_device
*phydev
);
226 int gen10g_discover_mmds(struct phy_device
*phydev
);
228 int phy_aquantia_init(void);
229 int phy_atheros_init(void);
230 int phy_broadcom_init(void);
231 int phy_cortina_init(void);
232 int phy_davicom_init(void);
233 int phy_et1011c_init(void);
234 int phy_lxt_init(void);
235 int phy_marvell_init(void);
236 int phy_micrel_init(void);
237 int phy_natsemi_init(void);
238 int phy_realtek_init(void);
239 int phy_smsc_init(void);
240 int phy_teranetics_init(void);
241 int phy_vitesse_init(void);
243 int board_phy_config(struct phy_device
*phydev
);
245 /* PHY UIDs for various PHYs that are referenced in external code */
246 #define PHY_UID_CS4340 0x13e51002
247 #define PHY_UID_TN2020 0x00a19410