include/phy.h

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  *      Andy Fleming <afleming@gmail.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  *
   7  * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
   8  */
   9
  10 #ifndef _PHY_H
  11 #define _PHY_H
  12
  13 #include <linux/list.h>
  14 #include <linux/mii.h>
  15 #include <linux/ethtool.h>
  16 #include <linux/mdio.h>
  17
  18 #define PHY_MAX_ADDR 32
  19
  20 #define PHY_BASIC_FEATURES      (SUPPORTED_10baseT_Half | \
  21                                  SUPPORTED_10baseT_Full | \
  22                                  SUPPORTED_100baseT_Half | \
  23                                  SUPPORTED_100baseT_Full | \
  24                                  SUPPORTED_Autoneg | \
  25                                  SUPPORTED_TP | \
  26                                  SUPPORTED_MII)
  27
  28 #define PHY_GBIT_FEATURES       (PHY_BASIC_FEATURES | \
  29                                  SUPPORTED_1000baseT_Half | \
  30                                  SUPPORTED_1000baseT_Full)
  31
  32 #define PHY_10G_FEATURES        (PHY_GBIT_FEATURES | \
  33                                 SUPPORTED_10000baseT_Full)
  34
  35 #ifndef PHY_ANEG_TIMEOUT
  36 #define PHY_ANEG_TIMEOUT        4000
  37 #endif
  38
  39
  40 typedef enum {
  41         PHY_INTERFACE_MODE_MII,
  42         PHY_INTERFACE_MODE_GMII,
  43         PHY_INTERFACE_MODE_SGMII,
  44         PHY_INTERFACE_MODE_QSGMII,
  45         PHY_INTERFACE_MODE_TBI,
  46         PHY_INTERFACE_MODE_RMII,
  47         PHY_INTERFACE_MODE_RGMII,
  48         PHY_INTERFACE_MODE_RGMII_ID,
  49         PHY_INTERFACE_MODE_RGMII_RXID,
  50         PHY_INTERFACE_MODE_RGMII_TXID,
  51         PHY_INTERFACE_MODE_RTBI,
  52         PHY_INTERFACE_MODE_XGMII,
  53         PHY_INTERFACE_MODE_NONE /* Must be last */
  54 } phy_interface_t;
  55
  56 static const char *phy_interface_strings[] = {
  57         [PHY_INTERFACE_MODE_MII]                = "mii",
  58         [PHY_INTERFACE_MODE_GMII]               = "gmii",
  59         [PHY_INTERFACE_MODE_SGMII]              = "sgmii",
  60         [PHY_INTERFACE_MODE_QSGMII]             = "qsgmii",
  61         [PHY_INTERFACE_MODE_TBI]                = "tbi",
  62         [PHY_INTERFACE_MODE_RMII]               = "rmii",
  63         [PHY_INTERFACE_MODE_RGMII]              = "rgmii",
  64         [PHY_INTERFACE_MODE_RGMII_ID]           = "rgmii-id",
  65         [PHY_INTERFACE_MODE_RGMII_RXID]         = "rgmii-rxid",
  66         [PHY_INTERFACE_MODE_RGMII_TXID]         = "rgmii-txid",
  67         [PHY_INTERFACE_MODE_RTBI]               = "rtbi",
  68         [PHY_INTERFACE_MODE_XGMII]              = "xgmii",
  69         [PHY_INTERFACE_MODE_NONE]               = "",
  70 };
  71
  72 static inline const char *phy_string_for_interface(phy_interface_t i)
  73 {
  74         /* Default to unknown */
  75         if (i > PHY_INTERFACE_MODE_NONE)
  76                 i = PHY_INTERFACE_MODE_NONE;
  77
  78         return phy_interface_strings[i];
  79 }
  80
  81
  82 struct phy_device;
  83
  84 #define MDIO_NAME_LEN 32
  85
  86 struct mii_dev {
  87         struct list_head link;
  88         char name[MDIO_NAME_LEN];
  89         void *priv;
  90         int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
  91         int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
  92                         u16 val);
  93         int (*reset)(struct mii_dev *bus);
  94         struct phy_device *phymap[PHY_MAX_ADDR];
  95         u32 phy_mask;
  96 };
  97
  98 /* struct phy_driver: a structure which defines PHY behavior
  99  *
 100  * uid will contain a number which represents the PHY.  During
 101  * startup, the driver will poll the PHY to find out what its
 102  * UID--as defined by registers 2 and 3--is.  The 32-bit result
 103  * gotten from the PHY will be masked to
 104  * discard any bits which may change based on revision numbers
 105  * unimportant to functionality
 106  *
 107  */
 108 struct phy_driver {
 109         char *name;
 110         unsigned int uid;
 111         unsigned int mask;
 112         unsigned int mmds;
 113
 114         u32 features;
 115
 116         /* Called to do any driver startup necessities */
 117         /* Will be called during phy_connect */
 118         int (*probe)(struct phy_device *phydev);
 119
 120         /* Called to configure the PHY, and modify the controller
 121          * based on the results.  Should be called after phy_connect */
 122         int (*config)(struct phy_device *phydev);
 123
 124         /* Called when starting up the controller */
 125         int (*startup)(struct phy_device *phydev);
 126
 127         /* Called when bringing down the controller */
 128         int (*shutdown)(struct phy_device *phydev);
 129
 130         int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
 131         int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
 132                         u16 val);
 133         struct list_head list;
 134 };
 135
 136 struct phy_device {
 137         /* Information about the PHY type */
 138         /* And management functions */
 139         struct mii_dev *bus;
 140         struct phy_driver *drv;
 141         void *priv;
 142
 143         struct eth_device *dev;
 144
 145         /* forced speed & duplex (no autoneg)
 146          * partner speed & duplex & pause (autoneg)
 147          */
 148         int speed;
 149         int duplex;
 150
 151         /* The most recently read link state */
 152         int link;
 153         int port;
 154         phy_interface_t interface;
 155
 156         u32 advertising;
 157         u32 supported;
 158         u32 mmds;
 159
 160         int autoneg;
 161         int addr;
 162         int pause;
 163         int asym_pause;
 164         u32 phy_id;
 165         u32 flags;
 166 };
 167
 168 struct fixed_link {
 169         int phy_id;
 170         int duplex;
 171         int link_speed;
 172         int pause;
 173         int asym_pause;
 174 };
 175
 176 static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
 177 {
 178         struct mii_dev *bus = phydev->bus;
 179
 180         return bus->read(bus, phydev->addr, devad, regnum);
 181 }
 182
 183 static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
 184                         u16 val)
 185 {
 186         struct mii_dev *bus = phydev->bus;
 187
 188         return bus->write(bus, phydev->addr, devad, regnum, val);
 189 }
 190
 191 #ifdef CONFIG_PHYLIB_10G
 192 extern struct phy_driver gen10g_driver;
 193
 194 /* For now, XGMII is the only 10G interface */
 195 static inline int is_10g_interface(phy_interface_t interface)
 196 {
 197         return interface == PHY_INTERFACE_MODE_XGMII;
 198 }
 199
 200 #endif
 201
 202 int phy_init(void);
 203 int phy_reset(struct phy_device *phydev);
 204 struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
 205                 phy_interface_t interface);
 206 void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
 207 struct phy_device *phy_connect(struct mii_dev *bus, int addr,
 208                                 struct eth_device *dev,
 209                                 phy_interface_t interface);
 210 int phy_startup(struct phy_device *phydev);
 211 int phy_config(struct phy_device *phydev);
 212 int phy_shutdown(struct phy_device *phydev);
 213 int phy_register(struct phy_driver *drv);
 214 int genphy_config_aneg(struct phy_device *phydev);
 215 int genphy_restart_aneg(struct phy_device *phydev);
 216 int genphy_update_link(struct phy_device *phydev);
 217 int genphy_parse_link(struct phy_device *phydev);
 218 int genphy_config(struct phy_device *phydev);
 219 int genphy_startup(struct phy_device *phydev);
 220 int genphy_shutdown(struct phy_device *phydev);
 221 int gen10g_config(struct phy_device *phydev);
 222 int gen10g_startup(struct phy_device *phydev);
 223 int gen10g_shutdown(struct phy_device *phydev);
 224 int gen10g_discover_mmds(struct phy_device *phydev);
 225
 226 int phy_atheros_init(void);
 227 int phy_broadcom_init(void);
 228 int phy_davicom_init(void);
 229 int phy_et1011c_init(void);
 230 int phy_lxt_init(void);
 231 int phy_marvell_init(void);
 232 int phy_micrel_init(void);
 233 int phy_natsemi_init(void);
 234 int phy_realtek_init(void);
 235 int phy_smsc_init(void);
 236 int phy_teranetics_init(void);
 237 int phy_vitesse_init(void);
 238
 239 int board_phy_config(struct phy_device *phydev);
 240
 241 /* PHY UIDs for various PHYs that are referenced in external code */
 242 #define PHY_UID_TN2020  0x00a19410
 243
 244 #endif