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git.ipfire.org Git - people/ms/u-boot.git/blob - include/ppc405.h
1 /*----------------------------------------------------------------------------+
3 | This source code has been made available to you by IBM on an AS-IS
4 | basis. Anyone receiving this source is licensed under IBM
5 | copyrights to use it in any way he or she deems fit, including
6 | copying it, modifying it, compiling it, and redistributing it either
7 | with or without modifications. No license under IBM patents or
8 | patent applications is to be implied by the copyright license.
10 | Any user of this software should understand that IBM cannot provide
11 | technical support for this software and will not be responsible for
12 | any consequences resulting from the use of this software.
14 | Any person who transfers this source code or any derivative work
15 | must include the IBM copyright notice, this paragraph, and the
16 | preceding two paragraphs in the transferred software.
18 | COPYRIGHT I B M CORPORATION 1999
19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 +----------------------------------------------------------------------------*/
25 /*--------------------------------------------------------------------- */
26 /* Special Purpose Registers */
27 /*--------------------------------------------------------------------- */
28 #define srr2 0x3de /* save/restore register 2 */
29 #define srr3 0x3df /* save/restore register 3 */
32 * 405 does not really have CSRR0/1 but SRR2/3 are used during critical
33 * exception for the exact same purposes - let's alias them and have a
34 * common handling in crit_return() and CRIT_EXCEPTION
39 #define dbsr 0x3f0 /* debug status register */
40 #define dbcr0 0x3f2 /* debug control register 0 */
41 #define dbcr1 0x3bd /* debug control register 1 */
42 #define iac1 0x3f4 /* instruction address comparator 1 */
43 #define iac2 0x3f5 /* instruction address comparator 2 */
44 #define iac3 0x3b4 /* instruction address comparator 3 */
45 #define iac4 0x3b5 /* instruction address comparator 4 */
46 #define dac1 0x3f6 /* data address comparator 1 */
47 #define dac2 0x3f7 /* data address comparator 2 */
48 #define dccr 0x3fa /* data cache control register */
49 #define iccr 0x3fb /* instruction cache control register */
50 #define esr 0x3d4 /* execption syndrome register */
51 #define dear 0x3d5 /* data exeption address register */
52 #define evpr 0x3d6 /* exeption vector prefix register */
53 #define tsr 0x3d8 /* timer status register */
54 #define tcr 0x3da /* timer control register */
55 #define pit 0x3db /* programmable interval timer */
56 #define sgr 0x3b9 /* storage guarded reg */
57 #define dcwr 0x3ba /* data cache write-thru reg*/
58 #define sler 0x3bb /* storage little-endian reg */
59 #define cdbcr 0x3d7 /* cache debug cntrl reg */
60 #define icdbdr 0x3d3 /* instr cache dbug data reg*/
61 #define ccr0 0x3b3 /* core configuration register */
62 #define dvc1 0x3b6 /* data value compare register 1 */
63 #define dvc2 0x3b7 /* data value compare register 2 */
64 #define pid 0x3b1 /* process ID */
65 #define su0r 0x3bc /* storage user-defined register 0 */
66 #define zpr 0x3b0 /* zone protection regsiter */
68 #define tbl 0x11c /* time base lower - privileged write */
69 #define tbu 0x11d /* time base upper - privileged write */
71 #define sprg4r 0x104 /* Special purpose general 4 - read only */
72 #define sprg5r 0x105 /* Special purpose general 5 - read only */
73 #define sprg6r 0x106 /* Special purpose general 6 - read only */
74 #define sprg7r 0x107 /* Special purpose general 7 - read only */
75 #define sprg4w 0x114 /* Special purpose general 4 - write only */
76 #define sprg5w 0x115 /* Special purpose general 5 - write only */
77 #define sprg6w 0x116 /* Special purpose general 6 - write only */
78 #define sprg7w 0x117 /* Special purpose general 7 - write only */
80 /******************************************************************************
81 * Special for PPC405GP
82 ******************************************************************************/
84 /******************************************************************************
86 ******************************************************************************/
87 #define DMA_DCR_BASE 0x100
88 #define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
89 #define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
90 #define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */
91 #define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */
92 #define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */
93 #define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
94 #define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
95 #define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */
96 #define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */
97 #define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */
98 #define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
99 #define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
100 #define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */
101 #define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */
102 #define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */
103 #define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */
104 #define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */
105 #define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */
106 #define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */
107 #define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */
108 #define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
109 #define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
110 #define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */
112 /******************************************************************************
113 * Universal interrupt controller
114 ******************************************************************************/
115 #define UIC_DCR_BASE 0xc0
116 #define uicsr (UIC_DCR_BASE+0x0) /* UIC status */
117 #define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */
118 #define uicer (UIC_DCR_BASE+0x2) /* UIC enable */
119 #define uiccr (UIC_DCR_BASE+0x3) /* UIC critical */
120 #define uicpr (UIC_DCR_BASE+0x4) /* UIC polarity */
121 #define uictr (UIC_DCR_BASE+0x5) /* UIC triggering */
122 #define uicmsr (UIC_DCR_BASE+0x6) /* UIC masked status */
123 #define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */
124 #define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */
126 /*-----------------------------------------------------------------------------+
127 | Universal interrupt controller interrupts
128 +-----------------------------------------------------------------------------*/
129 #if defined(CONFIG_405EZ)
130 #define UIC_DMA0 0x80000000 /* DMA chan. 0 */
131 #define UIC_DMA1 0x40000000 /* DMA chan. 1 */
132 #define UIC_DMA2 0x20000000 /* DMA chan. 2 */
133 #define UIC_DMA3 0x10000000 /* DMA chan. 3 */
134 #define UIC_1588 0x08000000 /* IEEE 1588 network synchronization */
135 #define UIC_UART0 0x04000000 /* UART 0 */
136 #define UIC_UART1 0x02000000 /* UART 1 */
137 #define UIC_CAN0 0x01000000 /* CAN 0 */
138 #define UIC_CAN1 0x00800000 /* CAN 1 */
139 #define UIC_SPI 0x00400000 /* SPI */
140 #define UIC_IIC 0x00200000 /* IIC */
141 #define UIC_CHT0 0x00100000 /* Chameleon timer high pri interrupt */
142 #define UIC_CHT1 0x00080000 /* Chameleon timer high pri interrupt */
143 #define UIC_USBH1 0x00040000 /* USB Host 1 */
144 #define UIC_USBH2 0x00020000 /* USB Host 2 */
145 #define UIC_USBDEV 0x00010000 /* USB Device */
146 #define UIC_ENET 0x00008000 /* Ethernet interrupt status */
147 #define UIC_ENET1 0x00008000 /* dummy define */
148 #define UIC_EMAC_WAKE 0x00004000 /* EMAC wake up */
150 #define UIC_MADMAL 0x00002000 /* Logical OR of following MadMAL int */
151 #define UIC_MAL_SERR 0x00002000 /* MAL SERR */
152 #define UIC_MAL_TXDE 0x00002000 /* MAL TXDE */
153 #define UIC_MAL_RXDE 0x00002000 /* MAL RXDE */
155 #define UIC_MAL_TXEOB 0x00001000 /* MAL TXEOB */
156 #define UIC_MAL_TXEOB1 0x00000800 /* MAL TXEOB1 */
157 #define UIC_MAL_RXEOB 0x00000400 /* MAL RXEOB */
158 #define UIC_NAND 0x00000200 /* NAND Flash controller */
159 #define UIC_ADC 0x00000100 /* ADC */
160 #define UIC_DAC 0x00000080 /* DAC */
161 #define UIC_OPB2PLB 0x00000040 /* OPB to PLB bridge interrupt */
162 #define UIC_RESERVED0 0x00000020 /* Reserved */
163 #define UIC_EXT0 0x00000010 /* External interrupt 0 */
164 #define UIC_EXT1 0x00000008 /* External interrupt 1 */
165 #define UIC_EXT2 0x00000004 /* External interrupt 2 */
166 #define UIC_EXT3 0x00000002 /* External interrupt 3 */
167 #define UIC_EXT4 0x00000001 /* External interrupt 4 */
169 #else /* !defined(CONFIG_405EZ) */
171 #define UIC_UART0 0x80000000 /* UART 0 */
172 #define UIC_UART1 0x40000000 /* UART 1 */
173 #define UIC_IIC 0x20000000 /* IIC */
174 #define UIC_EXT_MAST 0x10000000 /* External Master */
175 #define UIC_PCI 0x08000000 /* PCI write to command reg */
176 #define UIC_DMA0 0x04000000 /* DMA chan. 0 */
177 #define UIC_DMA1 0x02000000 /* DMA chan. 1 */
178 #define UIC_DMA2 0x01000000 /* DMA chan. 2 */
179 #define UIC_DMA3 0x00800000 /* DMA chan. 3 */
180 #define UIC_EMAC_WAKE 0x00400000 /* EMAC wake up */
181 #define UIC_MAL_SERR 0x00200000 /* MAL SERR */
182 #define UIC_MAL_TXEOB 0x00100000 /* MAL TXEOB */
183 #define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */
184 #define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */
185 #define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */
186 #define UIC_ENET 0x00010000 /* Ethernet0 */
187 #define UIC_ENET1 0x00004000 /* Ethernet1 on 405EP */
188 #define UIC_ECC_CE 0x00004000 /* ECC Correctable Error on 405GP */
189 #define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */
190 #define UIC_PCI_PM 0x00002000 /* PCI Power Management */
191 #define UIC_EXT0 0x00000040 /* External interrupt 0 */
192 #define UIC_EXT1 0x00000020 /* External interrupt 1 */
193 #define UIC_EXT2 0x00000010 /* External interrupt 2 */
194 #define UIC_EXT3 0x00000008 /* External interrupt 3 */
195 #define UIC_EXT4 0x00000004 /* External interrupt 4 */
196 #define UIC_EXT5 0x00000002 /* External interrupt 5 */
197 #define UIC_EXT6 0x00000001 /* External interrupt 6 */
198 #endif /* defined(CONFIG_405EZ) */
200 /******************************************************************************
202 ******************************************************************************/
203 #define SDRAM_DCR_BASE 0x10
204 #define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */
205 #define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */
206 /* values for memcfga register - indirect addressing of these regs */
208 #define mem_besra 0x00 /* bus error syndrome reg a */
209 #define mem_besrsa 0x04 /* bus error syndrome reg set a */
210 #define mem_besrb 0x08 /* bus error syndrome reg b */
211 #define mem_besrsb 0x0c /* bus error syndrome reg set b */
212 #define mem_bear 0x10 /* bus error address reg */
214 #define mem_mcopt1 0x20 /* memory controller options 1 */
215 #define mem_status 0x24 /* memory status */
216 #define mem_rtr 0x30 /* refresh timer reg */
217 #define mem_pmit 0x34 /* power management idle timer */
218 #define mem_mb0cf 0x40 /* memory bank 0 configuration */
219 #define mem_mb1cf 0x44 /* memory bank 1 configuration */
221 #define mem_mb2cf 0x48 /* memory bank 2 configuration */
222 #define mem_mb3cf 0x4c /* memory bank 3 configuration */
224 #define mem_sdtr1 0x80 /* timing reg 1 */
226 #define mem_ecccf 0x94 /* ECC configuration */
227 #define mem_eccerr 0x98 /* ECC error status */
231 /******************************************************************************
232 * Decompression Controller
233 ******************************************************************************/
234 #define DECOMP_DCR_BASE 0x14
235 #define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */
236 #define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */
237 /* values for kiar register - indirect addressing of these regs */
238 #define kitor0 0x00 /* index table origin register 0 */
239 #define kitor1 0x01 /* index table origin register 1 */
240 #define kitor2 0x02 /* index table origin register 2 */
241 #define kitor3 0x03 /* index table origin register 3 */
242 #define kaddr0 0x04 /* address decode definition regsiter 0 */
243 #define kaddr1 0x05 /* address decode definition regsiter 1 */
244 #define kconf 0x40 /* decompression core config register */
245 #define kid 0x41 /* decompression core ID register */
246 #define kver 0x42 /* decompression core version # reg */
247 #define kpear 0x50 /* bus error addr reg (PLB addr) */
248 #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/
249 #define kesr0 0x52 /* bus error status reg 0 (R/clear) */
250 #define kesr0s 0x53 /* bus error status reg 0 (set) */
251 /* There are 0x400 of the following registers, from krom0 to krom3ff*/
252 /* Only the first one is given here. */
253 #define krom0 0x400 /* SRAM/ROM read/write */
256 /******************************************************************************
258 ******************************************************************************/
259 #define POWERMAN_DCR_BASE 0xb8
260 #define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */
261 #define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */
262 #define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */
264 /******************************************************************************
265 * Extrnal Bus Controller
266 ******************************************************************************/
267 #define EBC_DCR_BASE 0x12
268 #define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */
269 #define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */
270 /* values for ebccfga register - indirect addressing of these regs */
271 #define pb0cr 0x00 /* periph bank 0 config reg */
272 #define pb1cr 0x01 /* periph bank 1 config reg */
273 #define pb2cr 0x02 /* periph bank 2 config reg */
274 #define pb3cr 0x03 /* periph bank 3 config reg */
275 #define pb4cr 0x04 /* periph bank 4 config reg */
277 #define pb5cr 0x05 /* periph bank 5 config reg */
278 #define pb6cr 0x06 /* periph bank 6 config reg */
279 #define pb7cr 0x07 /* periph bank 7 config reg */
281 #define pb0ap 0x10 /* periph bank 0 access parameters */
282 #define pb1ap 0x11 /* periph bank 1 access parameters */
283 #define pb2ap 0x12 /* periph bank 2 access parameters */
284 #define pb3ap 0x13 /* periph bank 3 access parameters */
285 #define pb4ap 0x14 /* periph bank 4 access parameters */
287 #define pb5ap 0x15 /* periph bank 5 access parameters */
288 #define pb6ap 0x16 /* periph bank 6 access parameters */
289 #define pb7ap 0x17 /* periph bank 7 access parameters */
291 #define pbear 0x20 /* periph bus error addr reg */
292 #define pbesr0 0x21 /* periph bus error status reg 0 */
293 #define pbesr1 0x22 /* periph bus error status reg 1 */
294 #define epcr 0x23 /* external periph control reg */
295 #define EBC0_CFG 0x23 /* external bus configuration reg */
298 /******************************************************************************
300 ******************************************************************************/
301 #define CNTRL_DCR_BASE 0x0f0
302 #define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */
303 #define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */
304 #define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */
305 #define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */
306 #define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */
307 #define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */
309 #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
310 #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
311 #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
312 #define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/
313 #define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
314 #define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
315 #define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
316 #define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
317 #define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
318 #define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
320 /* Bit definitions */
321 #define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
322 #define PLLMR0_CPU_DIV_BYPASS 0x00000000
323 #define PLLMR0_CPU_DIV_2 0x00100000
324 #define PLLMR0_CPU_DIV_3 0x00200000
325 #define PLLMR0_CPU_DIV_4 0x00300000
327 #define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
328 #define PLLMR0_CPU_PLB_DIV_1 0x00000000
329 #define PLLMR0_CPU_PLB_DIV_2 0x00010000
330 #define PLLMR0_CPU_PLB_DIV_3 0x00020000
331 #define PLLMR0_CPU_PLB_DIV_4 0x00030000
333 #define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
334 #define PLLMR0_OPB_PLB_DIV_1 0x00000000
335 #define PLLMR0_OPB_PLB_DIV_2 0x00001000
336 #define PLLMR0_OPB_PLB_DIV_3 0x00002000
337 #define PLLMR0_OPB_PLB_DIV_4 0x00003000
339 #define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
340 #define PLLMR0_EXB_PLB_DIV_2 0x00000000
341 #define PLLMR0_EXB_PLB_DIV_3 0x00000100
342 #define PLLMR0_EXB_PLB_DIV_4 0x00000200
343 #define PLLMR0_EXB_PLB_DIV_5 0x00000300
345 #define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
346 #define PLLMR0_MAL_PLB_DIV_1 0x00000000
347 #define PLLMR0_MAL_PLB_DIV_2 0x00000010
348 #define PLLMR0_MAL_PLB_DIV_3 0x00000020
349 #define PLLMR0_MAL_PLB_DIV_4 0x00000030
351 #define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
352 #define PLLMR0_PCI_PLB_DIV_1 0x00000000
353 #define PLLMR0_PCI_PLB_DIV_2 0x00000001
354 #define PLLMR0_PCI_PLB_DIV_3 0x00000002
355 #define PLLMR0_PCI_PLB_DIV_4 0x00000003
357 #define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
358 #define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
359 #define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
360 #define PLLMR1_FBMUL_DIV_16 0x00000000
361 #define PLLMR1_FBMUL_DIV_1 0x00100000
362 #define PLLMR1_FBMUL_DIV_2 0x00200000
363 #define PLLMR1_FBMUL_DIV_3 0x00300000
364 #define PLLMR1_FBMUL_DIV_4 0x00400000
365 #define PLLMR1_FBMUL_DIV_5 0x00500000
366 #define PLLMR1_FBMUL_DIV_6 0x00600000
367 #define PLLMR1_FBMUL_DIV_7 0x00700000
368 #define PLLMR1_FBMUL_DIV_8 0x00800000
369 #define PLLMR1_FBMUL_DIV_9 0x00900000
370 #define PLLMR1_FBMUL_DIV_10 0x00A00000
371 #define PLLMR1_FBMUL_DIV_11 0x00B00000
372 #define PLLMR1_FBMUL_DIV_12 0x00C00000
373 #define PLLMR1_FBMUL_DIV_13 0x00D00000
374 #define PLLMR1_FBMUL_DIV_14 0x00E00000
375 #define PLLMR1_FBMUL_DIV_15 0x00F00000
377 #define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
378 #define PLLMR1_FWDVA_DIV_8 0x00000000
379 #define PLLMR1_FWDVA_DIV_7 0x00010000
380 #define PLLMR1_FWDVA_DIV_6 0x00020000
381 #define PLLMR1_FWDVA_DIV_5 0x00030000
382 #define PLLMR1_FWDVA_DIV_4 0x00040000
383 #define PLLMR1_FWDVA_DIV_3 0x00050000
384 #define PLLMR1_FWDVA_DIV_2 0x00060000
385 #define PLLMR1_FWDVA_DIV_1 0x00070000
386 #define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
387 #define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
389 /* Defines for CPC0_EPRCSR register */
390 #define CPC0_EPRCSR_E0NFE 0x80000000
391 #define CPC0_EPRCSR_E1NFE 0x40000000
392 #define CPC0_EPRCSR_E1RPP 0x00000080
393 #define CPC0_EPRCSR_E0RPP 0x00000040
394 #define CPC0_EPRCSR_E1ERP 0x00000020
395 #define CPC0_EPRCSR_E0ERP 0x00000010
396 #define CPC0_EPRCSR_E1PCI 0x00000002
397 #define CPC0_EPRCSR_E0PCI 0x00000001
399 /* Defines for CPC0_PCI Register */
400 #define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */
401 #define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */
402 #define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/
404 /* Defines for CPC0_BOOR Register */
405 #define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
407 /* Defines for CPC0_PLLMR1 Register fields */
408 #define PLL_ACTIVE 0x80000000
409 #define CPC0_PLLMR1_SSCS 0x80000000
410 #define PLL_RESET 0x40000000
411 #define CPC0_PLLMR1_PLLR 0x40000000
412 /* Feedback multiplier */
413 #define PLL_FBKDIV 0x00F00000
414 #define CPC0_PLLMR1_FBDV 0x00F00000
415 #define PLL_FBKDIV_16 0x00000000
416 #define PLL_FBKDIV_1 0x00100000
417 #define PLL_FBKDIV_2 0x00200000
418 #define PLL_FBKDIV_3 0x00300000
419 #define PLL_FBKDIV_4 0x00400000
420 #define PLL_FBKDIV_5 0x00500000
421 #define PLL_FBKDIV_6 0x00600000
422 #define PLL_FBKDIV_7 0x00700000
423 #define PLL_FBKDIV_8 0x00800000
424 #define PLL_FBKDIV_9 0x00900000
425 #define PLL_FBKDIV_10 0x00A00000
426 #define PLL_FBKDIV_11 0x00B00000
427 #define PLL_FBKDIV_12 0x00C00000
428 #define PLL_FBKDIV_13 0x00D00000
429 #define PLL_FBKDIV_14 0x00E00000
430 #define PLL_FBKDIV_15 0x00F00000
431 /* Forward A divisor */
432 #define PLL_FWDDIVA 0x00070000
433 #define CPC0_PLLMR1_FWDVA 0x00070000
434 #define PLL_FWDDIVA_8 0x00000000
435 #define PLL_FWDDIVA_7 0x00010000
436 #define PLL_FWDDIVA_6 0x00020000
437 #define PLL_FWDDIVA_5 0x00030000
438 #define PLL_FWDDIVA_4 0x00040000
439 #define PLL_FWDDIVA_3 0x00050000
440 #define PLL_FWDDIVA_2 0x00060000
441 #define PLL_FWDDIVA_1 0x00070000
442 /* Forward B divisor */
443 #define PLL_FWDDIVB 0x00007000
444 #define CPC0_PLLMR1_FWDVB 0x00007000
445 #define PLL_FWDDIVB_8 0x00000000
446 #define PLL_FWDDIVB_7 0x00001000
447 #define PLL_FWDDIVB_6 0x00002000
448 #define PLL_FWDDIVB_5 0x00003000
449 #define PLL_FWDDIVB_4 0x00004000
450 #define PLL_FWDDIVB_3 0x00005000
451 #define PLL_FWDDIVB_2 0x00006000
452 #define PLL_FWDDIVB_1 0x00007000
454 #define PLL_TUNE_MASK 0x000003FF
455 #define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
456 #define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
457 #define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
458 #define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
459 #define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
460 #define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
461 #define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
463 /* Defines for CPC0_PLLMR0 Register fields */
465 #define PLL_CPUDIV 0x00300000
466 #define CPC0_PLLMR0_CCDV 0x00300000
467 #define PLL_CPUDIV_1 0x00000000
468 #define PLL_CPUDIV_2 0x00100000
469 #define PLL_CPUDIV_3 0x00200000
470 #define PLL_CPUDIV_4 0x00300000
472 #define PLL_PLBDIV 0x00030000
473 #define CPC0_PLLMR0_CBDV 0x00030000
474 #define PLL_PLBDIV_1 0x00000000
475 #define PLL_PLBDIV_2 0x00010000
476 #define PLL_PLBDIV_3 0x00020000
477 #define PLL_PLBDIV_4 0x00030000
479 #define PLL_OPBDIV 0x00003000
480 #define CPC0_PLLMR0_OPDV 0x00003000
481 #define PLL_OPBDIV_1 0x00000000
482 #define PLL_OPBDIV_2 0x00001000
483 #define PLL_OPBDIV_3 0x00002000
484 #define PLL_OPBDIV_4 0x00003000
486 #define PLL_EXTBUSDIV 0x00000300
487 #define CPC0_PLLMR0_EPDV 0x00000300
488 #define PLL_EXTBUSDIV_2 0x00000000
489 #define PLL_EXTBUSDIV_3 0x00000100
490 #define PLL_EXTBUSDIV_4 0x00000200
491 #define PLL_EXTBUSDIV_5 0x00000300
493 #define PLL_MALDIV 0x00000030
494 #define CPC0_PLLMR0_MPDV 0x00000030
495 #define PLL_MALDIV_1 0x00000000
496 #define PLL_MALDIV_2 0x00000010
497 #define PLL_MALDIV_3 0x00000020
498 #define PLL_MALDIV_4 0x00000030
500 #define PLL_PCIDIV 0x00000003
501 #define CPC0_PLLMR0_PPFD 0x00000003
502 #define PLL_PCIDIV_1 0x00000000
503 #define PLL_PCIDIV_2 0x00000001
504 #define PLL_PCIDIV_3 0x00000002
505 #define PLL_PCIDIV_4 0x00000003
508 *-------------------------------------------------------------------------------
509 * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
510 * assuming a 33.3MHz input clock to the 405EP.
511 *-------------------------------------------------------------------------------
513 #define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
514 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
515 PLL_MALDIV_1 | PLL_PCIDIV_4)
516 #define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \
517 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
518 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
520 #define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
521 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
522 PLL_MALDIV_1 | PLL_PCIDIV_4)
523 #define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
524 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
525 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
526 #define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
527 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
528 PLL_MALDIV_1 | PLL_PCIDIV_4)
529 #define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
530 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
531 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
532 #define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
533 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
534 PLL_MALDIV_1 | PLL_PCIDIV_4)
535 #define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
536 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
537 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
538 #define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \
539 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
540 PLL_MALDIV_1 | PLL_PCIDIV_2)
541 #define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
542 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
543 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
546 * PLL Voltage Controlled Oscillator (VCO) definitions
547 * Maximum and minimum values (in MHz) for correct PLL operation.
551 #elif defined(CONFIG_405EZ)
552 /******************************************************************************
554 ******************************************************************************/
555 #define SDR_DCR_BASE 0x0E
556 #define sdrcfga (SDR_DCR_BASE+0x0) /* ADDR */
557 #define sdrcfgd (SDR_DCR_BASE+0x1) /* Data */
559 #define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0)
560 #define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0)
562 #define sdrnand0 0x4000
563 #define sdrultra0 0x4040
564 #define sdrultra1 0x4050
565 #define sdricintstat 0x4510
567 #define SDR_NAND0_NDEN 0x80000000
568 #define SDR_NAND0_NDBTEN 0x40000000
569 #define SDR_NAND0_NDBADR_MASK 0x30000000
570 #define SDR_NAND0_NDBPG_MASK 0x0f000000
571 #define SDR_NAND0_NDAREN 0x00800000
572 #define SDR_NAND0_NDRBEN 0x00400000
574 #define SDR_ULTRA0_NDGPIOBP 0x80000000
575 #define SDR_ULTRA0_CSN_MASK 0x78000000
576 #define SDR_ULTRA0_CSNSEL0 0x40000000
577 #define SDR_ULTRA0_CSNSEL1 0x20000000
578 #define SDR_ULTRA0_CSNSEL2 0x10000000
579 #define SDR_ULTRA0_CSNSEL3 0x08000000
580 #define SDR_ULTRA0_EBCRDYEN 0x04000000
581 #define SDR_ULTRA0_SPISSINEN 0x02000000
582 #define SDR_ULTRA0_NFSRSTEN 0x01000000
584 #define SDR_ULTRA1_LEDNENABLE 0x40000000
586 #define SDR_ICRX_STAT 0x80000000
587 #define SDR_ICTX0_STAT 0x40000000
588 #define SDR_ICTX1_STAT 0x20000000
590 #define SDR_PINSTP 0x40
592 /******************************************************************************
594 ******************************************************************************/
595 #define CNTRL_DCR_BASE 0x0C
596 #define cprcfga (CNTRL_DCR_BASE+0x0) /* CPR addr reg */
597 #define cprcfgd (CNTRL_DCR_BASE+0x1) /* CPR data reg */
600 #define cprclkupd 0x020 /* CPR_CLKUPD */
601 #define cprpllc 0x040 /* CPR_PLLC */
602 #define cprplld 0x060 /* CPR_PLLD */
603 #define cprprimad 0x080 /* CPR_PRIMAD */
604 #define cprperd0 0x0e0 /* CPR_PERD0 */
605 #define cprperd1 0x0e1 /* CPR_PERD1 */
606 #define cprperc0 0x180 /* CPR_PERC0 */
607 #define cprmisc0 0x181 /* CPR_MISC0 */
608 #define cprmisc1 0x182 /* CPR_MISC1 */
611 * Macro for accessing the indirect CPR register
613 #define mtcpr(reg, data) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,data); } while (0)
614 #define mfcpr(reg, data) do { mtdcr(cprcfga,reg);data = mfdcr(cprcfgd); } while (0)
616 #define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */
617 #define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
618 #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
620 #define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
621 #define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
622 #define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
624 #define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
625 #define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
626 #define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
627 #define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
629 #define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
630 #define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
631 #define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
632 #define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
634 #if 0 /* Deprecated */
635 #define CNTRL_DCR_BASE 0x0f0
636 #define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */
637 #define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */
638 #define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */
639 #define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */
640 #define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */
641 #define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */
643 #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
644 #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
645 #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
646 #define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/
647 #define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
648 #define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
649 #define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
650 #define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
651 #define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
652 #define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
654 /* Bit definitions */
655 #define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
656 #define PLLMR0_CPU_DIV_BYPASS 0x00000000
657 #define PLLMR0_CPU_DIV_2 0x00100000
658 #define PLLMR0_CPU_DIV_3 0x00200000
659 #define PLLMR0_CPU_DIV_4 0x00300000
661 #define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
662 #define PLLMR0_CPU_PLB_DIV_1 0x00000000
663 #define PLLMR0_CPU_PLB_DIV_2 0x00010000
664 #define PLLMR0_CPU_PLB_DIV_3 0x00020000
665 #define PLLMR0_CPU_PLB_DIV_4 0x00030000
667 #define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
668 #define PLLMR0_OPB_PLB_DIV_1 0x00000000
669 #define PLLMR0_OPB_PLB_DIV_2 0x00001000
670 #define PLLMR0_OPB_PLB_DIV_3 0x00002000
671 #define PLLMR0_OPB_PLB_DIV_4 0x00003000
673 #define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
674 #define PLLMR0_EXB_PLB_DIV_2 0x00000000
675 #define PLLMR0_EXB_PLB_DIV_3 0x00000100
676 #define PLLMR0_EXB_PLB_DIV_4 0x00000200
677 #define PLLMR0_EXB_PLB_DIV_5 0x00000300
679 #define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
680 #define PLLMR0_MAL_PLB_DIV_1 0x00000000
681 #define PLLMR0_MAL_PLB_DIV_2 0x00000010
682 #define PLLMR0_MAL_PLB_DIV_3 0x00000020
683 #define PLLMR0_MAL_PLB_DIV_4 0x00000030
685 #define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
686 #define PLLMR0_PCI_PLB_DIV_1 0x00000000
687 #define PLLMR0_PCI_PLB_DIV_2 0x00000001
688 #define PLLMR0_PCI_PLB_DIV_3 0x00000002
689 #define PLLMR0_PCI_PLB_DIV_4 0x00000003
691 #define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
692 #define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
693 #define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
694 #define PLLMR1_FBMUL_DIV_16 0x00000000
695 #define PLLMR1_FBMUL_DIV_1 0x00100000
696 #define PLLMR1_FBMUL_DIV_2 0x00200000
697 #define PLLMR1_FBMUL_DIV_3 0x00300000
698 #define PLLMR1_FBMUL_DIV_4 0x00400000
699 #define PLLMR1_FBMUL_DIV_5 0x00500000
700 #define PLLMR1_FBMUL_DIV_6 0x00600000
701 #define PLLMR1_FBMUL_DIV_7 0x00700000
702 #define PLLMR1_FBMUL_DIV_8 0x00800000
703 #define PLLMR1_FBMUL_DIV_9 0x00900000
704 #define PLLMR1_FBMUL_DIV_10 0x00A00000
705 #define PLLMR1_FBMUL_DIV_11 0x00B00000
706 #define PLLMR1_FBMUL_DIV_12 0x00C00000
707 #define PLLMR1_FBMUL_DIV_13 0x00D00000
708 #define PLLMR1_FBMUL_DIV_14 0x00E00000
709 #define PLLMR1_FBMUL_DIV_15 0x00F00000
711 #define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
712 #define PLLMR1_FWDVA_DIV_8 0x00000000
713 #define PLLMR1_FWDVA_DIV_7 0x00010000
714 #define PLLMR1_FWDVA_DIV_6 0x00020000
715 #define PLLMR1_FWDVA_DIV_5 0x00030000
716 #define PLLMR1_FWDVA_DIV_4 0x00040000
717 #define PLLMR1_FWDVA_DIV_3 0x00050000
718 #define PLLMR1_FWDVA_DIV_2 0x00060000
719 #define PLLMR1_FWDVA_DIV_1 0x00070000
720 #define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
721 #define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
723 /* Defines for CPC0_EPRCSR register */
724 #define CPC0_EPRCSR_E0NFE 0x80000000
725 #define CPC0_EPRCSR_E1NFE 0x40000000
726 #define CPC0_EPRCSR_E1RPP 0x00000080
727 #define CPC0_EPRCSR_E0RPP 0x00000040
728 #define CPC0_EPRCSR_E1ERP 0x00000020
729 #define CPC0_EPRCSR_E0ERP 0x00000010
730 #define CPC0_EPRCSR_E1PCI 0x00000002
731 #define CPC0_EPRCSR_E0PCI 0x00000001
733 /* Defines for CPC0_BOOR Register */
734 #define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
736 /* Defines for CPC0_PLLMR1 Register fields */
737 #define PLL_ACTIVE 0x80000000
738 #define CPC0_PLLMR1_SSCS 0x80000000
739 #define PLL_RESET 0x40000000
740 #define CPC0_PLLMR1_PLLR 0x40000000
741 /* Feedback multiplier */
742 #define PLL_FBKDIV 0x00F00000
743 #define CPC0_PLLMR1_FBDV 0x00F00000
744 #define PLL_FBKDIV_16 0x00000000
745 #define PLL_FBKDIV_1 0x00100000
746 #define PLL_FBKDIV_2 0x00200000
747 #define PLL_FBKDIV_3 0x00300000
748 #define PLL_FBKDIV_4 0x00400000
749 #define PLL_FBKDIV_5 0x00500000
750 #define PLL_FBKDIV_6 0x00600000
751 #define PLL_FBKDIV_7 0x00700000
752 #define PLL_FBKDIV_8 0x00800000
753 #define PLL_FBKDIV_9 0x00900000
754 #define PLL_FBKDIV_10 0x00A00000
755 #define PLL_FBKDIV_11 0x00B00000
756 #define PLL_FBKDIV_12 0x00C00000
757 #define PLL_FBKDIV_13 0x00D00000
758 #define PLL_FBKDIV_14 0x00E00000
759 #define PLL_FBKDIV_15 0x00F00000
760 /* Forward A divisor */
761 #define PLL_FWDDIVA 0x00070000
762 #define CPC0_PLLMR1_FWDVA 0x00070000
763 #define PLL_FWDDIVA_8 0x00000000
764 #define PLL_FWDDIVA_7 0x00010000
765 #define PLL_FWDDIVA_6 0x00020000
766 #define PLL_FWDDIVA_5 0x00030000
767 #define PLL_FWDDIVA_4 0x00040000
768 #define PLL_FWDDIVA_3 0x00050000
769 #define PLL_FWDDIVA_2 0x00060000
770 #define PLL_FWDDIVA_1 0x00070000
771 /* Forward B divisor */
772 #define PLL_FWDDIVB 0x00007000
773 #define CPC0_PLLMR1_FWDVB 0x00007000
774 #define PLL_FWDDIVB_8 0x00000000
775 #define PLL_FWDDIVB_7 0x00001000
776 #define PLL_FWDDIVB_6 0x00002000
777 #define PLL_FWDDIVB_5 0x00003000
778 #define PLL_FWDDIVB_4 0x00004000
779 #define PLL_FWDDIVB_3 0x00005000
780 #define PLL_FWDDIVB_2 0x00006000
781 #define PLL_FWDDIVB_1 0x00007000
783 #define PLL_TUNE_MASK 0x000003FF
784 #define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
785 #define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
786 #define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
787 #define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
788 #define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
789 #define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
790 #define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
792 /* Defines for CPC0_PLLMR0 Register fields */
794 #define PLL_CPUDIV 0x00300000
795 #define CPC0_PLLMR0_CCDV 0x00300000
796 #define PLL_CPUDIV_1 0x00000000
797 #define PLL_CPUDIV_2 0x00100000
798 #define PLL_CPUDIV_3 0x00200000
799 #define PLL_CPUDIV_4 0x00300000
801 #define PLL_PLBDIV 0x00030000
802 #define CPC0_PLLMR0_CBDV 0x00030000
803 #define PLL_PLBDIV_1 0x00000000
804 #define PLL_PLBDIV_2 0x00010000
805 #define PLL_PLBDIV_3 0x00020000
806 #define PLL_PLBDIV_4 0x00030000
808 #define PLL_OPBDIV 0x00003000
809 #define CPC0_PLLMR0_OPDV 0x00003000
810 #define PLL_OPBDIV_1 0x00000000
811 #define PLL_OPBDIV_2 0x00001000
812 #define PLL_OPBDIV_3 0x00002000
813 #define PLL_OPBDIV_4 0x00003000
815 #define PLL_EXTBUSDIV 0x00000300
816 #define CPC0_PLLMR0_EPDV 0x00000300
817 #define PLL_EXTBUSDIV_2 0x00000000
818 #define PLL_EXTBUSDIV_3 0x00000100
819 #define PLL_EXTBUSDIV_4 0x00000200
820 #define PLL_EXTBUSDIV_5 0x00000300
822 #define PLL_MALDIV 0x00000030
823 #define CPC0_PLLMR0_MPDV 0x00000030
824 #define PLL_MALDIV_1 0x00000000
825 #define PLL_MALDIV_2 0x00000010
826 #define PLL_MALDIV_3 0x00000020
827 #define PLL_MALDIV_4 0x00000030
829 #define PLL_PCIDIV 0x00000003
830 #define CPC0_PLLMR0_PPFD 0x00000003
831 #define PLL_PCIDIV_1 0x00000000
832 #define PLL_PCIDIV_2 0x00000001
833 #define PLL_PCIDIV_3 0x00000002
834 #define PLL_PCIDIV_4 0x00000003
837 *-------------------------------------------------------------------------------
838 * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
839 * assuming a 33.3MHz input clock to the 405EP.
840 *-------------------------------------------------------------------------------
842 #define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
843 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
844 PLL_MALDIV_1 | PLL_PCIDIV_4)
845 #define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \
846 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
847 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
848 #define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
849 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
850 PLL_MALDIV_1 | PLL_PCIDIV_4)
851 #define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
852 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
853 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
854 #define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
855 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
856 PLL_MALDIV_1 | PLL_PCIDIV_4)
857 #define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
858 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
859 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
860 #define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
861 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
862 PLL_MALDIV_1 | PLL_PCIDIV_4)
863 #define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
864 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
865 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
866 #define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \
867 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
868 PLL_MALDIV_1 | PLL_PCIDIV_2)
869 #define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
870 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
871 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
874 * PLL Voltage Controlled Oscillator (VCO) definitions
875 * Maximum and minimum values (in MHz) for correct PLL operation.
880 #else /* #ifdef CONFIG_405EP */
881 /******************************************************************************
883 ******************************************************************************/
884 #define CNTRL_DCR_BASE 0x0b0
885 #define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */
886 #define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */
887 #define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */
888 #define reset (CNTRL_DCR_BASE+0x3) /* reset register */
889 #define strap (CNTRL_DCR_BASE+0x4) /* strap register */
891 #define ecr (0xaa) /* edge conditioner register (405gpr) */
893 /* Bit definitions */
894 #define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
895 #define PLLMR_FWD_DIV_BYPASS 0xE0000000
896 #define PLLMR_FWD_DIV_3 0xA0000000
897 #define PLLMR_FWD_DIV_4 0x80000000
898 #define PLLMR_FWD_DIV_6 0x40000000
900 #define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
901 #define PLLMR_FB_DIV_1 0x02000000
902 #define PLLMR_FB_DIV_2 0x04000000
903 #define PLLMR_FB_DIV_3 0x06000000
904 #define PLLMR_FB_DIV_4 0x08000000
906 #define PLLMR_TUNING_MASK 0x01F80000
908 #define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
909 #define PLLMR_CPU_PLB_DIV_1 0x00000000
910 #define PLLMR_CPU_PLB_DIV_2 0x00020000
911 #define PLLMR_CPU_PLB_DIV_3 0x00040000
912 #define PLLMR_CPU_PLB_DIV_4 0x00060000
914 #define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
915 #define PLLMR_OPB_PLB_DIV_1 0x00000000
916 #define PLLMR_OPB_PLB_DIV_2 0x00008000
917 #define PLLMR_OPB_PLB_DIV_3 0x00010000
918 #define PLLMR_OPB_PLB_DIV_4 0x00018000
920 #define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
921 #define PLLMR_PCI_PLB_DIV_1 0x00000000
922 #define PLLMR_PCI_PLB_DIV_2 0x00002000
923 #define PLLMR_PCI_PLB_DIV_3 0x00004000
924 #define PLLMR_PCI_PLB_DIV_4 0x00006000
926 #define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
927 #define PLLMR_EXB_PLB_DIV_2 0x00000000
928 #define PLLMR_EXB_PLB_DIV_3 0x00000800
929 #define PLLMR_EXB_PLB_DIV_4 0x00001000
930 #define PLLMR_EXB_PLB_DIV_5 0x00001800
932 /* definitions for PPC405GPr (new mode strapping) */
933 #define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
935 #define PSR_PLL_FWD_MASK 0xC0000000
936 #define PSR_PLL_FDBACK_MASK 0x30000000
937 #define PSR_PLL_TUNING_MASK 0x0E000000
938 #define PSR_PLB_CPU_MASK 0x01800000
939 #define PSR_OPB_PLB_MASK 0x00600000
940 #define PSR_PCI_PLB_MASK 0x00180000
941 #define PSR_EB_PLB_MASK 0x00060000
942 #define PSR_ROM_WIDTH_MASK 0x00018000
943 #define PSR_ROM_LOC 0x00004000
944 #define PSR_PCI_ASYNC_EN 0x00001000
945 #define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
946 #define PSR_PCI_ARBIT_EN 0x00000400
947 #define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
949 #ifndef CONFIG_IOP480
951 * PLL Voltage Controlled Oscillator (VCO) definitions
952 * Maximum and minimum values (in MHz) for correct PLL operation.
956 #endif /* #ifndef CONFIG_IOP480 */
957 #endif /* #ifdef CONFIG_405EP */
959 /******************************************************************************
960 * Memory Access Layer
961 ******************************************************************************/
962 #if defined(CONFIG_405EZ)
963 #define MAL_DCR_BASE 0x380
964 #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
965 #define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/
966 #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
967 #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
968 #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/
969 #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
970 #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
971 #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
972 /* 0x08-0x0F Reserved */
973 #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/
974 #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
975 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
976 #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
977 /* 0x14-0x1F Reserved */
978 #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */
979 #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */
980 #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */
981 #define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */
982 #define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */
983 #define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */
984 #define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */
985 #define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */
986 #define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */
987 #define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */
988 #define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */
989 #define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */
990 #define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */
991 #define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */
992 #define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */
993 #define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */
994 #define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */
995 #define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */
996 #define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */
997 #define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */
998 #define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */
999 #define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */
1000 #define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */
1001 #define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */
1002 #define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */
1003 #define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */
1004 #define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */
1005 #define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */
1006 #define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */
1007 #define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */
1008 #define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */
1009 #define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */
1010 #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */
1011 #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */
1012 #define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */
1013 #define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */
1014 #define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */
1015 #define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */
1016 #define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */
1017 #define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */
1018 #define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */
1019 #define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */
1020 #define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */
1021 #define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */
1022 #define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */
1023 #define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */
1024 #define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */
1025 #define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */
1026 #define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */
1027 #define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */
1028 #define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */
1029 #define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */
1030 #define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */
1031 #define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */
1032 #define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */
1033 #define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */
1034 #define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */
1035 #define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */
1036 #define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */
1037 #define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */
1038 #define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */
1039 #define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */
1040 #define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */
1041 #define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */
1042 #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
1043 #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
1044 #define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
1045 #define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
1046 #define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */
1047 #define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */
1048 #define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */
1049 #define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */
1050 #define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */
1051 #define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */
1052 #define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */
1053 #define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */
1054 #define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */
1055 #define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */
1056 #define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */
1057 #define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */
1058 #define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */
1059 #define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */
1060 #define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */
1061 #define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */
1062 #define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */
1063 #define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */
1064 #define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */
1065 #define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */
1066 #define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */
1067 #define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */
1068 #define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */
1069 #define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */
1070 #define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */
1071 #define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */
1072 #define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */
1073 #define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */
1075 #else /* !defined(CONFIG_405EZ) */
1077 #define MAL_DCR_BASE 0x180
1078 #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
1079 #define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
1080 #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
1081 #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
1082 #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
1083 #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
1084 #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
1085 #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
1086 #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
1087 #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
1088 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
1089 #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
1090 #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
1091 #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
1092 #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */
1093 #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
1094 #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
1095 #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
1096 #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
1097 #endif /* defined(CONFIG_405EZ) */
1099 /*-----------------------------------------------------------------------------
1100 | IIC Register Offsets
1101 '----------------------------------------------------------------------------*/
1102 #define IICMDBUF 0x00
1103 #define IICSDBUF 0x02
1104 #define IICLMADR 0x04
1105 #define IICHMADR 0x05
1106 #define IICCNTL 0x06
1107 #define IICMDCNTL 0x07
1109 #define IICEXTSTS 0x09
1110 #define IICLSADR 0x0A
1111 #define IICHSADR 0x0B
1112 #define IICCLKDIV 0x0C
1113 #define IICINTRMSK 0x0D
1114 #define IICXFRCNT 0x0E
1115 #define IICXTCNTLSS 0x0F
1116 #define IICDIRECTCNTL 0x10
1118 /*-----------------------------------------------------------------------------
1119 | UART Register Offsets
1120 '----------------------------------------------------------------------------*/
1121 #define DATA_REG 0x00
1124 #define INT_ENABLE 0x01
1125 #define FIFO_CONTROL 0x02
1126 #define LINE_CONTROL 0x03
1127 #define MODEM_CONTROL 0x04
1128 #define LINE_STATUS 0x05
1129 #define MODEM_STATUS 0x06
1130 #define SCRATCH 0x07
1132 /******************************************************************************
1134 ******************************************************************************/
1135 #if defined(CONFIG_405EZ)
1136 #define OCM_DCR_BASE 0x020
1137 #define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */
1138 #define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */
1139 #define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */
1140 #define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */
1141 #define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */
1142 #define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */
1143 #define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */
1144 #define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */
1145 #define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */
1146 #define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */
1147 #define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */
1148 #define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */
1149 #define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/
1150 #define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/
1151 #define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/
1153 #define OCM_DCR_BASE 0x018
1154 #define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */
1155 #define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
1156 #define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */
1157 #define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */
1158 #endif /* CONFIG_405EZ */
1160 /******************************************************************************
1161 * GPIO macro register defines
1162 ******************************************************************************/
1163 #if defined(CONFIG_405EZ)
1164 /* Only the 405EZ has 2 GPIOs */
1165 #define GPIO_BASE 0xEF600700
1166 #define GPIO0_OR (GPIO_BASE+0x0)
1167 #define GPIO0_TCR (GPIO_BASE+0x4)
1168 #define GPIO0_OSRL (GPIO_BASE+0x8)
1169 #define GPIO0_OSRH (GPIO_BASE+0xC)
1170 #define GPIO0_TSRL (GPIO_BASE+0x10)
1171 #define GPIO0_TSRH (GPIO_BASE+0x14)
1172 #define GPIO0_ODR (GPIO_BASE+0x18)
1173 #define GPIO0_IR (GPIO_BASE+0x1C)
1174 #define GPIO0_RR1 (GPIO_BASE+0x20)
1175 #define GPIO0_RR2 (GPIO_BASE+0x24)
1176 #define GPIO0_RR3 (GPIO_BASE+0x28)
1177 #define GPIO0_ISR1L (GPIO_BASE+0x30)
1178 #define GPIO0_ISR1H (GPIO_BASE+0x34)
1179 #define GPIO0_ISR2L (GPIO_BASE+0x38)
1180 #define GPIO0_ISR2H (GPIO_BASE+0x3C)
1181 #define GPIO0_ISR3L (GPIO_BASE+0x40)
1182 #define GPIO0_ISR3H (GPIO_BASE+0x44)
1184 #define GPIO1_BASE 0xEF600800
1185 #define GPIO1_OR (GPIO1_BASE+0x0)
1186 #define GPIO1_TCR (GPIO1_BASE+0x4)
1187 #define GPIO1_OSRL (GPIO1_BASE+0x8)
1188 #define GPIO1_OSRH (GPIO1_BASE+0xC)
1189 #define GPIO1_TSRL (GPIO1_BASE+0x10)
1190 #define GPIO1_TSRH (GPIO1_BASE+0x14)
1191 #define GPIO1_ODR (GPIO1_BASE+0x18)
1192 #define GPIO1_IR (GPIO1_BASE+0x1C)
1193 #define GPIO1_RR1 (GPIO1_BASE+0x20)
1194 #define GPIO1_RR2 (GPIO1_BASE+0x24)
1195 #define GPIO1_RR3 (GPIO1_BASE+0x28)
1196 #define GPIO1_ISR1L (GPIO1_BASE+0x30)
1197 #define GPIO1_ISR1H (GPIO1_BASE+0x34)
1198 #define GPIO1_ISR2L (GPIO1_BASE+0x38)
1199 #define GPIO1_ISR2H (GPIO1_BASE+0x3C)
1200 #define GPIO1_ISR3L (GPIO1_BASE+0x40)
1201 #define GPIO1_ISR3H (GPIO1_BASE+0x44)
1205 #define GPIO_BASE 0xEF600700
1206 #define GPIO0_OR (GPIO_BASE+0x0)
1207 #define GPIO0_TCR (GPIO_BASE+0x4)
1208 #define GPIO0_OSRH (GPIO_BASE+0x8)
1209 #define GPIO0_OSRL (GPIO_BASE+0xC)
1210 #define GPIO0_TSRH (GPIO_BASE+0x10)
1211 #define GPIO0_TSRL (GPIO_BASE+0x14)
1212 #define GPIO0_ODR (GPIO_BASE+0x18)
1213 #define GPIO0_IR (GPIO_BASE+0x1C)
1214 #define GPIO0_RR1 (GPIO_BASE+0x20)
1215 #define GPIO0_RR2 (GPIO_BASE+0x24)
1216 #define GPIO0_ISR1H (GPIO_BASE+0x30)
1217 #define GPIO0_ISR1L (GPIO_BASE+0x34)
1218 #define GPIO0_ISR2H (GPIO_BASE+0x38)
1219 #define GPIO0_ISR2L (GPIO_BASE+0x3C)
1221 #endif /* CONFIG_405EZ */
1224 * Macro for accessing the indirect EBC register
1226 #define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
1227 #define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
1230 #ifndef __ASSEMBLY__
1234 unsigned long pllFwdDiv
;
1235 unsigned long pllFwdDivB
;
1236 unsigned long pllFbkDiv
;
1237 unsigned long pllPlbDiv
;
1238 unsigned long pllPciDiv
;
1239 unsigned long pllExtBusDiv
;
1240 unsigned long pllOpbDiv
;
1241 unsigned long freqVCOMhz
; /* in MHz */
1242 unsigned long freqProcessor
;
1243 unsigned long freqPLB
;
1244 unsigned long freqPCI
;
1245 unsigned long pciIntArbEn
; /* Internal PCI arbiter is enabled */
1246 unsigned long pciClkSync
; /* PCI clock is synchronous */
1247 unsigned long freqVCOHz
;
1250 #endif /* _ASMLANGUAGE */
1252 #define RESET_VECTOR 0xfffffffc
1253 #define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
1254 line aligned data. */
1256 #endif /* __PPC405_H__ */
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