include/ppc4xx.h

   1 /*----------------------------------------------------------------------------+
   2 |
   3 |       This source code has been made available to you by IBM on an AS-IS
   4 |       basis.  Anyone receiving this source is licensed under IBM
   5 |       copyrights to use it in any way he or she deems fit, including
   6 |       copying it, modifying it, compiling it, and redistributing it either
   7 |       with or without modifications.  No license under IBM patents or
   8 |       patent applications is to be implied by the copyright license.
   9 |
  10 |       Any user of this software should understand that IBM cannot provide
  11 |       technical support for this software and will not be responsible for
  12 |       any consequences resulting from the use of this software.
  13 |
  14 |       Any person who transfers this source code or any derivative work
  15 |       must include the IBM copyright notice, this paragraph, and the
  16 |       preceding two paragraphs in the transferred software.
  17 |
  18 |       COPYRIGHT   I B M   CORPORATION 1999
  19 |       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  20 +----------------------------------------------------------------------------*/
  21
  22 #ifndef __PPC4XX_H__
  23 #define __PPC4XX_H__
  24
  25 /*
  26  * Configure which SDRAM/DDR/DDR2 controller is equipped
  27  */
  28 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
  29         defined(CONFIG_AP1000) || defined(CONFIG_ML2)
  30 #define CONFIG_SDRAM_PPC4xx_IBM_SDRAM   /* IBM SDRAM controller */
  31 #endif
  32
  33 #if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
  34     defined(CONFIG_440EP) || defined(CONFIG_440GR)
  35 #define CONFIG_SDRAM_PPC4xx_IBM_DDR     /* IBM DDR controller */
  36 #endif
  37
  38 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  39 #define CONFIG_SDRAM_PPC4xx_DENALI_DDR2 /* Denali DDR(2) controller */
  40 #endif
  41
  42 #if defined(CONFIG_405EX) || \
  43     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  44     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  45     defined(CONFIG_460SX)
  46 #define CONFIG_SDRAM_PPC4xx_IBM_DDR2    /* IBM DDR(2) controller */
  47 #endif
  48
  49 #if defined(CONFIG_440)
  50 #include <ppc440.h>
  51 #else
  52 #include <ppc405.h>
  53 #endif
  54
  55 #include <asm/ppc4xx-sdram.h>
  56 #include <asm/ppc4xx-ebc.h>
  57 #if !defined(CONFIG_XILINX_440)
  58 #include <asm/ppc4xx-uic.h>
  59 #endif
  60
  61 /*
  62  * Macro for generating register field mnemonics
  63  */
  64 #define PPC_REG_BITS            32
  65 #define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
  66
  67 /*
  68  * Elide casts when assembling register mnemonics
  69  */
  70 #ifndef __ASSEMBLY__
  71 #define static_cast(type, val)  (type)(val)
  72 #else
  73 #define static_cast(type, val)  (val)
  74 #endif
  75
  76 /*
  77  * Common stuff for 4xx (405 and 440)
  78  */
  79
  80 #define EXC_OFF_SYS_RESET       0x0100  /* System reset                         */
  81 #define _START_OFFSET           (EXC_OFF_SYS_RESET + 0x2000)
  82
  83 #define RESET_VECTOR    0xfffffffc
  84 #define CACHELINE_MASK  (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
  85                                                      line aligned data. */
  86
  87 #define CPR0_DCR_BASE   0x0C
  88 #define cprcfga         (CPR0_DCR_BASE+0x0)
  89 #define cprcfgd         (CPR0_DCR_BASE+0x1)
  90
  91 #define SDR_DCR_BASE    0x0E
  92 #define sdrcfga         (SDR_DCR_BASE+0x0)
  93 #define sdrcfgd         (SDR_DCR_BASE+0x1)
  94
  95 #define SDRAM_DCR_BASE  0x10
  96 #define memcfga         (SDRAM_DCR_BASE+0x0)
  97 #define memcfgd         (SDRAM_DCR_BASE+0x1)
  98
  99 #define EBC_DCR_BASE    0x12
 100 #define ebccfga         (EBC_DCR_BASE+0x0)
 101 #define ebccfgd         (EBC_DCR_BASE+0x1)
 102
 103 /*
 104  * Macros for indirect DCR access
 105  */
 106 #define mtcpr(reg, d)   do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0)
 107 #define mfcpr(reg, d)   do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0)
 108
 109 #define mtebc(reg, d)   do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0)
 110 #define mfebc(reg, d)   do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0)
 111
 112 #define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0)
 113 #define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0)
 114
 115 #define mtsdr(reg, d)   do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0)
 116 #define mfsdr(reg, d)   do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0)
 117
 118 #ifndef __ASSEMBLY__
 119
 120 typedef struct
 121 {
 122         unsigned long freqDDR;
 123         unsigned long freqEBC;
 124         unsigned long freqOPB;
 125         unsigned long freqPCI;
 126         unsigned long freqPLB;
 127         unsigned long freqTmrClk;
 128         unsigned long freqUART;
 129         unsigned long freqProcessor;
 130         unsigned long freqVCOHz;
 131         unsigned long freqVCOMhz;       /* in MHz                          */
 132         unsigned long pciClkSync;       /* PCI clock is synchronous        */
 133         unsigned long pciIntArbEn;      /* Internal PCI arbiter is enabled */
 134         unsigned long pllExtBusDiv;
 135         unsigned long pllFbkDiv;
 136         unsigned long pllFwdDiv;
 137         unsigned long pllFwdDivA;
 138         unsigned long pllFwdDivB;
 139         unsigned long pllOpbDiv;
 140         unsigned long pllPciDiv;
 141         unsigned long pllPlbDiv;
 142 } PPC4xx_SYS_INFO;
 143
 144 #endif  /* __ASSEMBLY__ */
 145
 146 #endif  /* __PPC4XX_H__ */