include/ppc4xx.h

   1 /*----------------------------------------------------------------------------+
   2 |       This source code is dual-licensed.  You may use it under the terms of
   3 |       the GNU General Public License version 2, or under the license below.
   4 |
   5 |       This source code has been made available to you by IBM on an AS-IS
   6 |       basis.  Anyone receiving this source is licensed under IBM
   7 |       copyrights to use it in any way he or she deems fit, including
   8 |       copying it, modifying it, compiling it, and redistributing it either
   9 |       with or without modifications.  No license under IBM patents or
  10 |       patent applications is to be implied by the copyright license.
  11 |
  12 |       Any user of this software should understand that IBM cannot provide
  13 |       technical support for this software and will not be responsible for
  14 |       any consequences resulting from the use of this software.
  15 |
  16 |       Any person who transfers this source code or any derivative work
  17 |       must include the IBM copyright notice, this paragraph, and the
  18 |       preceding two paragraphs in the transferred software.
  19 |
  20 |       COPYRIGHT   I B M   CORPORATION 1999
  21 |       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  22 +----------------------------------------------------------------------------*/
  23
  24 #ifndef __PPC4XX_H__
  25 #define __PPC4XX_H__
  26
  27 /*
  28  * Configure which SDRAM/DDR/DDR2 controller is equipped
  29  */
  30 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
  31         defined(CONFIG_AP1000) || defined(CONFIG_ML2)
  32 #define CONFIG_SDRAM_PPC4xx_IBM_SDRAM   /* IBM SDRAM controller */
  33 #endif
  34
  35 #if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
  36     defined(CONFIG_440EP) || defined(CONFIG_440GR)
  37 #define CONFIG_SDRAM_PPC4xx_IBM_DDR     /* IBM DDR controller */
  38 #endif
  39
  40 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  41 #define CONFIG_SDRAM_PPC4xx_DENALI_DDR2 /* Denali DDR(2) controller */
  42 #endif
  43
  44 #if defined(CONFIG_405EX) || \
  45     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  46     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  47     defined(CONFIG_460SX)
  48 #define CONFIG_SDRAM_PPC4xx_IBM_DDR2    /* IBM DDR(2) controller */
  49 #endif
  50
  51 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) ||   \
  52     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  53     defined(CONFIG_405EZ) || defined(CONFIG_405EX) ||   \
  54     defined(CONFIG_460EX) || defined(CONFIG_460GT)
  55 #define CONFIG_NAND_NDFC
  56 #endif
  57
  58 /* PLB4 CrossBar Arbiter Core supported across PPC4xx families */
  59 #if defined(CONFIG_405EX) || \
  60     defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
  61     defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
  62     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  63     defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
  64     defined(CONFIG_460SX)
  65
  66 #define PLB_ARBITER_BASE                0x80
  67
  68 #define PLB0_ACR                        (PLB_ARBITER_BASE + 0x01)
  69 #define PLB0_ACR_PPM_MASK               0xF0000000
  70 #define PLB0_ACR_PPM_FIXED              0x00000000
  71 #define PLB0_ACR_PPM_FAIR               0xD0000000
  72 #define PLB0_ACR_HBU_MASK               0x08000000
  73 #define PLB0_ACR_HBU_DISABLED           0x00000000
  74 #define PLB0_ACR_HBU_ENABLED            0x08000000
  75 #define PLB0_ACR_RDP_MASK               0x06000000
  76 #define PLB0_ACR_RDP_DISABLED           0x00000000
  77 #define PLB0_ACR_RDP_2DEEP              0x02000000
  78 #define PLB0_ACR_RDP_3DEEP              0x04000000
  79 #define PLB0_ACR_RDP_4DEEP              0x06000000
  80 #define PLB0_ACR_WRP_MASK               0x01000000
  81 #define PLB0_ACR_WRP_DISABLED           0x00000000
  82 #define PLB0_ACR_WRP_2DEEP              0x01000000
  83
  84 #define PLB1_ACR                        (PLB_ARBITER_BASE + 0x09)
  85 #define PLB1_ACR_PPM_MASK               0xF0000000
  86 #define PLB1_ACR_PPM_FIXED              0x00000000
  87 #define PLB1_ACR_PPM_FAIR               0xD0000000
  88 #define PLB1_ACR_HBU_MASK               0x08000000
  89 #define PLB1_ACR_HBU_DISABLED           0x00000000
  90 #define PLB1_ACR_HBU_ENABLED            0x08000000
  91 #define PLB1_ACR_RDP_MASK               0x06000000
  92 #define PLB1_ACR_RDP_DISABLED           0x00000000
  93 #define PLB1_ACR_RDP_2DEEP              0x02000000
  94 #define PLB1_ACR_RDP_3DEEP              0x04000000
  95 #define PLB1_ACR_RDP_4DEEP              0x06000000
  96 #define PLB1_ACR_WRP_MASK               0x01000000
  97 #define PLB1_ACR_WRP_DISABLED           0x00000000
  98 #define PLB1_ACR_WRP_2DEEP              0x01000000
  99
 100 #endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/
 101
 102 #if defined(CONFIG_440)
 103 #include <ppc440.h>
 104 #else
 105 #include <ppc405.h>
 106 #endif
 107
 108 #include <asm/ppc4xx-sdram.h>
 109 #include <asm/ppc4xx-ebc.h>
 110 #if !defined(CONFIG_XILINX_440)
 111 #include <asm/ppc4xx-uic.h>
 112 #endif
 113
 114 /*
 115  * Macro for generating register field mnemonics
 116  */
 117 #define PPC_REG_BITS            32
 118 #define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
 119
 120 /*
 121  * Elide casts when assembling register mnemonics
 122  */
 123 #ifndef __ASSEMBLY__
 124 #define static_cast(type, val)  (type)(val)
 125 #else
 126 #define static_cast(type, val)  (val)
 127 #endif
 128
 129 /*
 130  * Common stuff for 4xx (405 and 440)
 131  */
 132
 133 #define EXC_OFF_SYS_RESET       0x0100  /* System reset                 */
 134 #define _START_OFFSET           (EXC_OFF_SYS_RESET + 0x2000)
 135
 136 #define RESET_VECTOR    0xfffffffc
 137 #define CACHELINE_MASK  (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for
 138                                                 cache line aligned data. */
 139
 140 #define CPR0_DCR_BASE   0x0C
 141 #define CPR0_CFGADDR    (CPR0_DCR_BASE + 0x0)
 142 #define CPR0_CFGDATA    (CPR0_DCR_BASE + 0x1)
 143
 144 #define SDR_DCR_BASE    0x0E
 145 #define SDR0_CFGADDR    (SDR_DCR_BASE + 0x0)
 146 #define SDR0_CFGDATA    (SDR_DCR_BASE + 0x1)
 147
 148 #define SDRAM_DCR_BASE  0x10
 149 #define SDRAM0_CFGADDR  (SDRAM_DCR_BASE + 0x0)
 150 #define SDRAM0_CFGDATA  (SDRAM_DCR_BASE + 0x1)
 151
 152 #define EBC_DCR_BASE    0x12
 153 #define EBC0_CFGADDR    (EBC_DCR_BASE + 0x0)
 154 #define EBC0_CFGDATA    (EBC_DCR_BASE + 0x1)
 155
 156 /*
 157  * Macros for indirect DCR access
 158  */
 159 #define mtcpr(reg, d)   \
 160   do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0)
 161 #define mfcpr(reg, d)   \
 162   do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0)
 163
 164 #define mtebc(reg, d)   \
 165   do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0)
 166 #define mfebc(reg, d)   \
 167   do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0)
 168
 169 #define mtsdram(reg, d) \
 170   do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
 171 #define mfsdram(reg, d) \
 172   do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
 173
 174 #define mtsdr(reg, d)   \
 175   do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0)
 176 #define mfsdr(reg, d)   \
 177   do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0)
 178
 179 #ifndef __ASSEMBLY__
 180
 181 typedef struct
 182 {
 183         unsigned long freqDDR;
 184         unsigned long freqEBC;
 185         unsigned long freqOPB;
 186         unsigned long freqPCI;
 187         unsigned long freqPLB;
 188         unsigned long freqTmrClk;
 189         unsigned long freqUART;
 190         unsigned long freqProcessor;
 191         unsigned long freqVCOHz;
 192         unsigned long freqVCOMhz;       /* in MHz                          */
 193         unsigned long pciClkSync;       /* PCI clock is synchronous        */
 194         unsigned long pciIntArbEn;      /* Internal PCI arbiter is enabled */
 195         unsigned long pllExtBusDiv;
 196         unsigned long pllFbkDiv;
 197         unsigned long pllFwdDiv;
 198         unsigned long pllFwdDivA;
 199         unsigned long pllFwdDivB;
 200         unsigned long pllOpbDiv;
 201         unsigned long pllPciDiv;
 202         unsigned long pllPlbDiv;
 203 } PPC4xx_SYS_INFO;
 204
 205 static inline u32 get_mcsr(void)
 206 {
 207         u32 val;
 208
 209         asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
 210         return val;
 211 }
 212
 213 static inline void set_mcsr(u32 val)
 214 {
 215         asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
 216 }
 217
 218 int ppc4xx_pci_sync_clock_config(u32 async);
 219
 220 #endif  /* __ASSEMBLY__ */
 221
 222 /* for multi-cpu support */
 223 #define NA_OR_UNKNOWN_CPU       -1
 224
 225 #endif  /* __PPC4XX_H__ */