include/ppc4xx_enet.h

   1 /*----------------------------------------------------------------------------+
   2 |   This source code is dual-licensed.  You may use it under the terms of the
   3 |   GNU General Public License version 2, or under the license below.
   4 |
   5 |       This source code has been made available to you by IBM on an AS-IS
   6 |       basis.  Anyone receiving this source is licensed under IBM
   7 |       copyrights to use it in any way he or she deems fit, including
   8 |       copying it, modifying it, compiling it, and redistributing it either
   9 |       with or without modifications.  No license under IBM patents or
  10 |       patent applications is to be implied by the copyright license.
  11 |
  12 |       Any user of this software should understand that IBM cannot provide
  13 |       technical support for this software and will not be responsible for
  14 |       any consequences resulting from the use of this software.
  15 |
  16 |       Any person who transfers this source code or any derivative work
  17 |       must include the IBM copyright notice, this paragraph, and the
  18 |       preceding two paragraphs in the transferred software.
  19 |
  20 |       COPYRIGHT   I B M   CORPORATION 1999
  21 |       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  22 +----------------------------------------------------------------------------*/
  23 /*----------------------------------------------------------------------------+
  24 |
  25 |  File Name:   enetemac.h
  26 |
  27 |  Function:    Header file for the EMAC3 macro on the 405GP.
  28 |
  29 |  Author:      Mark Wisner
  30 |
  31 |  Change Activity-
  32 |
  33 |  Date        Description of Change                                       BY
  34 |  ---------   ---------------------                                       ---
  35 |  29-Apr-99   Created                                                     MKW
  36 |
  37 +----------------------------------------------------------------------------*/
  38 /*----------------------------------------------------------------------------+
  39 |  19-Nov-03   Travis Sawyer, Sandburst Corporation, tsawyer@sandburst.com
  40 |              ported to handle 440GP and 440GX multiple EMACs
  41 +----------------------------------------------------------------------------*/
  42
  43 #ifndef _PPC4XX_ENET_H_
  44 #define _PPC4XX_ENET_H_
  45
  46 #include <net.h>
  47 #include "405_mal.h"
  48
  49
  50 /*-----------------------------------------------------------------------------+
  51 | General enternet defines.  802 frames are not supported.
  52 +-----------------------------------------------------------------------------*/
  53 #define ENET_ADDR_LENGTH                6
  54 #define ENET_ARPTYPE                    0x806
  55 #define ARP_REQUEST                     1
  56 #define ARP_REPLY                       2
  57 #define ENET_IPTYPE                     0x800
  58 #define ARP_CACHE_SIZE                  5
  59
  60 #define NUM_TX_BUFF 1
  61 #define NUM_RX_BUFF PKTBUFSRX
  62
  63 struct enet_frame {
  64    unsigned char        dest_addr[ENET_ADDR_LENGTH];
  65    unsigned char        source_addr[ENET_ADDR_LENGTH];
  66    unsigned short       type;
  67    unsigned char        enet_data[1];
  68 };
  69
  70 struct arp_entry {
  71    unsigned long        inet_address;
  72    unsigned char        mac_address[ENET_ADDR_LENGTH];
  73    unsigned long        valid;
  74    unsigned long        sec;
  75    unsigned long        nsec;
  76 };
  77
  78
  79 /* Statistic Areas */
  80 #define MAX_ERR_LOG 10
  81
  82 typedef struct emac_stats_st{   /* Statistic Block */
  83         int data_len_err;
  84         int rx_frames;
  85         int rx;
  86         int rx_prot_err;
  87         int int_err;
  88         int pkts_tx;
  89         int pkts_rx;
  90         int pkts_handled;
  91         short tx_err_log[MAX_ERR_LOG];
  92         short rx_err_log[MAX_ERR_LOG];
  93 } EMAC_STATS_ST, *EMAC_STATS_PST;
  94
  95 /* Structure containing variables used by the shared code (4xx_enet.c) */
  96 typedef struct emac_4xx_hw_st {
  97     uint32_t            hw_addr;                /* EMAC offset */
  98     uint32_t            tah_addr;               /* TAH offset */
  99     uint32_t            phy_id;
 100     uint32_t            phy_addr;
 101     uint32_t            original_fc;
 102     uint32_t            txcw;
 103     uint32_t            autoneg_failed;
 104     uint32_t            emac_ier;
 105     volatile mal_desc_t *tx;
 106     volatile mal_desc_t *rx;
 107     u32                 tx_phys;
 108     u32                 rx_phys;
 109     bd_t                *bis;   /* for eth_init upon mal error */
 110     mal_desc_t          *alloc_tx_buf;
 111     mal_desc_t          *alloc_rx_buf;
 112     char                *txbuf_ptr;
 113     uint16_t            devnum;
 114     int                 get_link_status;
 115     int                 tbi_compatibility_en;
 116     int                 tbi_compatibility_on;
 117     int                 fc_send_xon;
 118     int                 report_tx_early;
 119     int                 first_init;
 120     int                 tx_err_index;
 121     int                 rx_err_index;
 122     int                 rx_slot;        /* MAL Receive Slot */
 123     int                 rx_i_index;     /* Receive Interrupt Queue Index */
 124     int                 rx_u_index;     /* Receive User Queue Index */
 125     int                 tx_slot;        /* MAL Transmit Slot */
 126     int                 tx_i_index;     /* Transmit Interrupt Queue Index */
 127     int                 tx_u_index;             /* Transmit User Queue Index */
 128     int                 rx_ready[NUM_RX_BUFF];  /* Receive Ready Queue */
 129     int                 tx_run[NUM_TX_BUFF];    /* Transmit Running Queue */
 130     int                 is_receiving;   /* sync with eth interrupt */
 131     int                 print_speed;    /* print speed message upon start */
 132     EMAC_STATS_ST       stats;
 133 } EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST;
 134
 135
 136 #if defined(CONFIG_440GX) || defined(CONFIG_460GT)
 137 #define EMAC_NUM_DEV            4
 138 #elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
 139         defined(CONFIG_NET_MULTI) &&                    \
 140         !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
 141 #define EMAC_NUM_DEV            2
 142 #else
 143 #define EMAC_NUM_DEV            1
 144 #endif
 145
 146 #ifdef CONFIG_IBM_EMAC4_V4      /* EMAC4 V4 changed bit setting */
 147 #define EMAC_STACR_OC_MASK      (0x00008000)
 148 #else
 149 #define EMAC_STACR_OC_MASK      (0x00000000)
 150 #endif
 151
 152 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
 153     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
 154     defined(CONFIG_405EX)
 155 #define SDR0_PFC1_EM_1000       (0x00200000)
 156 #endif
 157
 158 /*
 159  * XMII bridge configurations for those systems (e.g. 405EX(r)) that do
 160  * not have a pin function control (PFC) register to otherwise determine
 161  * the bridge configuration.
 162  */
 163 #define EMAC_PHY_MODE_NONE              0
 164 #define EMAC_PHY_MODE_NONE_RGMII        1
 165 #define EMAC_PHY_MODE_RGMII_NONE        2
 166 #define EMAC_PHY_MODE_RGMII_RGMII       3
 167 #define EMAC_PHY_MODE_NONE_GMII         4
 168 #define EMAC_PHY_MODE_GMII_NONE         5
 169 #define EMAC_PHY_MODE_NONE_MII          6
 170 #define EMAC_PHY_MODE_MII_NONE          7
 171
 172 /* ZMII Bridge Register addresses */
 173 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
 174     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
 175     defined(CONFIG_460EX) || defined(CONFIG_460GT)
 176 #define ZMII0_BASE              (CONFIG_SYS_PERIPHERAL_BASE + 0x0D00)
 177 #else
 178 #define ZMII0_BASE              (CONFIG_SYS_PERIPHERAL_BASE + 0x0780)
 179 #endif
 180 #define ZMII0_FER               (ZMII0_BASE)
 181 #define ZMII0_SSR               (ZMII0_BASE + 4)
 182 #define ZMII0_SMIISR            (ZMII0_BASE + 8)
 183
 184 /* ZMII FER Register Bit Definitions */
 185 #define ZMII_FER_DIS            (0x0)
 186 #define ZMII_FER_MDI            (0x8)
 187 #define ZMII_FER_SMII           (0x4)
 188 #define ZMII_FER_RMII           (0x2)
 189 #define ZMII_FER_MII            (0x1)
 190
 191 #define ZMII_FER_RSVD11         (0x00200000)
 192 #define ZMII_FER_RSVD10         (0x00100000)
 193 #define ZMII_FER_RSVD14_31      (0x0003FFFF)
 194
 195 #define ZMII_FER_V(__x)         (((3 - __x) * 4) + 16)
 196
 197
 198 /* ZMII Speed Selection Register Bit Definitions */
 199 #define ZMII0_SSR_SCI           (0x4)
 200 #define ZMII0_SSR_FSS           (0x2)
 201 #define ZMII0_SSR_SP            (0x1)
 202 #define ZMII0_SSR_RSVD16_31     (0x0000FFFF)
 203
 204 #define ZMII0_SSR_V(__x)                (((3 - __x) * 4) + 16)
 205
 206
 207 /* ZMII SMII Status Register Bit Definitions */
 208 #define ZMII0_SMIISR_E1         (0x80)
 209 #define ZMII0_SMIISR_EC         (0x40)
 210 #define ZMII0_SMIISR_EN         (0x20)
 211 #define ZMII0_SMIISR_EJ         (0x10)
 212 #define ZMII0_SMIISR_EL         (0x08)
 213 #define ZMII0_SMIISR_ED         (0x04)
 214 #define ZMII0_SMIISR_ES         (0x02)
 215 #define ZMII0_SMIISR_EF         (0x01)
 216
 217 #define ZMII0_SMIISR_V(__x)     ((3 - __x) * 8)
 218
 219 /* RGMII Register Addresses */
 220 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 221 #define RGMII_BASE              (CONFIG_SYS_PERIPHERAL_BASE + 0x1000)
 222 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
 223 #define RGMII_BASE              (CONFIG_SYS_PERIPHERAL_BASE + 0x1500)
 224 #elif defined(CONFIG_405EX)
 225 #define RGMII_BASE              (CONFIG_SYS_PERIPHERAL_BASE + 0xB00)
 226 #else
 227 #define RGMII_BASE              (CONFIG_SYS_PERIPHERAL_BASE + 0x0790)
 228 #endif
 229 #define RGMII_FER               (RGMII_BASE + 0x00)
 230 #define RGMII_SSR               (RGMII_BASE + 0x04)
 231
 232 #if defined(CONFIG_460GT)
 233 #define RGMII1_BASE_OFFSET      0x100
 234 #endif
 235
 236 /* RGMII Function Enable (FER) Register Bit Definitions */
 237 #define RGMII_FER_DIS           (0x00)
 238 #define RGMII_FER_RTBI          (0x04)
 239 #define RGMII_FER_RGMII         (0x05)
 240 #define RGMII_FER_TBI           (0x06)
 241 #define RGMII_FER_GMII          (0x07)
 242 #define RGMII_FER_MII           (RGMII_FER_GMII)
 243
 244 #define RGMII_FER_V(__x)        ((__x - 2) * 4)
 245
 246 #define RGMII_FER_MDIO(__x)     (1 << (19 - (__x)))
 247
 248 /* RGMII Speed Selection Register Bit Definitions */
 249 #define RGMII_SSR_SP_10MBPS     (0x00)
 250 #define RGMII_SSR_SP_100MBPS    (0x02)
 251 #define RGMII_SSR_SP_1000MBPS   (0x04)
 252
 253 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
 254     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
 255     defined(CONFIG_405EX)
 256 #define RGMII_SSR_V(__x)        ((__x) * 8)
 257 #else
 258 #define RGMII_SSR_V(__x)        ((__x -2) * 8)
 259 #endif
 260
 261 /*---------------------------------------------------------------------------+
 262 |  TCP/IP Acceleration Hardware (TAH) 440GX Only
 263 +---------------------------------------------------------------------------*/
 264 #if defined(CONFIG_440GX)
 265 #define TAH_BASE        (CONFIG_SYS_PERIPHERAL_BASE + 0x0B50)
 266 #define TAH_REVID       (TAH_BASE + 0x0)    /* Revision ID (RO)*/
 267 #define TAH_MR          (TAH_BASE + 0x10)   /* Mode Register (R/W) */
 268 #define TAH_SSR0        (TAH_BASE + 0x14)   /* Segment Size Reg 0 (R/W) */
 269 #define TAH_SSR1        (TAH_BASE + 0x18)   /* Segment Size Reg 1 (R/W) */
 270 #define TAH_SSR2        (TAH_BASE + 0x1C)   /* Segment Size Reg 2 (R/W) */
 271 #define TAH_SSR3        (TAH_BASE + 0x20)   /* Segment Size Reg 3 (R/W) */
 272 #define TAH_SSR4        (TAH_BASE + 0x24)   /* Segment Size Reg 4 (R/W) */
 273 #define TAH_SSR5        (TAH_BASE + 0x28)   /* Segment Size Reg 5 (R/W) */
 274 #define TAH_TSR         (TAH_BASE + 0x2C)   /* Transmit Status Register (RO) */
 275
 276 /* TAH Revision */
 277 #define TAH_REV_RN_M            (0x000FFF00)        /* Revision Number */
 278 #define TAH_REV_BN_M            (0x000000FF)        /* Branch Revision Number */
 279
 280 #define TAH_REV_RN_V            (8)
 281 #define TAH_REV_BN_V            (0)
 282
 283 /* TAH Mode Register */
 284 #define TAH_MR_CVR      (0x80000000)        /* Checksum verification on RX */
 285 #define TAH_MR_SR       (0x40000000)        /* Software reset */
 286 #define TAH_MR_ST       (0x3F000000)        /* Send Threshold */
 287 #define TAH_MR_TFS      (0x00E00000)        /* Transmit FIFO size */
 288 #define TAH_MR_DTFP     (0x00100000)        /* Disable TX FIFO parity */
 289 #define TAH_MR_DIG      (0x00080000)        /* Disable interrupt generation */
 290 #define TAH_MR_RSVD     (0x0007FFFF)        /* Reserved */
 291
 292 #define TAH_MR_ST_V     (20)
 293 #define TAH_MR_TFS_V    (17)
 294
 295 #define TAH_MR_TFS_2K   (0x1)       /* Transmit FIFO size 2Kbyte */
 296 #define TAH_MR_TFS_4K   (0x2)       /* Transmit FIFO size 4Kbyte */
 297 #define TAH_MR_TFS_6K   (0x3)       /* Transmit FIFO size 6Kbyte */
 298 #define TAH_MR_TFS_8K   (0x4)       /* Transmit FIFO size 8Kbyte */
 299 #define TAH_MR_TFS_10K  (0x5)       /* Transmit FIFO size 10Kbyte (max)*/
 300
 301
 302 /* TAH Segment Size Registers 0:5 */
 303 #define TAH_SSR_RSVD0   (0xC0000000)        /* Reserved */
 304 #define TAH_SSR_SS      (0x3FFE0000)        /* Segment size in multiples of 2 */
 305 #define TAH_SSR_RSVD1   (0x0001FFFF)        /* Reserved */
 306
 307 /* TAH Transmit Status Register */
 308 #define TAH_TSR_TFTS    (0x80000000)        /* Transmit FIFO too small */
 309 #define TAH_TSR_UH      (0x40000000)        /* Unrecognized header */
 310 #define TAH_TSR_NIPF    (0x20000000)        /* Not IPv4 */
 311 #define TAH_TSR_IPOP    (0x10000000)        /* IP option present */
 312 #define TAH_TSR_NISF    (0x08000000)        /* No IEEE SNAP format */
 313 #define TAH_TSR_ILTS    (0x04000000)        /* IP length too short */
 314 #define TAH_TSR_IPFP    (0x02000000)        /* IP fragment present */
 315 #define TAH_TSR_UP      (0x01000000)        /* Unsupported protocol */
 316 #define TAH_TSR_TFP     (0x00800000)        /* TCP flags present */
 317 #define TAH_TSR_SUDP    (0x00400000)        /* Segmentation for UDP */
 318 #define TAH_TSR_DLM     (0x00200000)        /* Data length mismatch */
 319 #define TAH_TSR_SIEEE   (0x00100000)        /* Segmentation for IEEE */
 320 #define TAH_TSR_TFPE    (0x00080000)        /* Transmit FIFO parity error */
 321 #define TAH_TSR_SSTS    (0x00040000)        /* Segment size too small */
 322 #define TAH_TSR_RSVD    (0x0003FFFF)        /* Reserved */
 323 #endif /* CONFIG_440GX */
 324
 325
 326 /* Ethernet MAC Regsiter Addresses */
 327 #if defined(CONFIG_440)
 328 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
 329     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
 330     defined(CONFIG_460EX) || defined(CONFIG_460GT)
 331 #define EMAC0_BASE              (CONFIG_SYS_PERIPHERAL_BASE + 0x0E00)
 332 #else
 333 #define EMAC0_BASE              (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
 334 #endif
 335 #else
 336 #if defined(CONFIG_405EZ) || defined(CONFIG_405EX)
 337 #define EMAC0_BASE              0xEF600900
 338 #else
 339 #define EMAC0_BASE              0xEF600800
 340 #endif
 341 #endif
 342
 343 #if defined(CONFIG_440EPX)
 344 #define EMAC1_BASE              0xEF600F00
 345 #define EMAC1_MR1               (EMAC1_BASE + 0x04)
 346 #endif
 347
 348 #define EMAC0_MR0               (EMAC0_BASE)
 349 #define EMAC0_MR1               (EMAC0_BASE + 0x04)
 350 #define EMAC0_TMR0              (EMAC0_BASE + 0x08)
 351 #define EMAC0_TMR1              (EMAC0_BASE + 0x0c)
 352 #define EMAC0_RXM               (EMAC0_BASE + 0x10)
 353 #define EMAC0_ISR               (EMAC0_BASE + 0x14)
 354 #define EMAC0_IER               (EMAC0_BASE + 0x18)
 355 #define EMAC0_IAH               (EMAC0_BASE + 0x1c)
 356 #define EMAC0_IAL               (EMAC0_BASE + 0x20)
 357 #define EMAC0_PTR               (EMAC0_BASE + 0x2c)
 358 #define EMAC0_PAUSE_TIME_REG    EMAC0_PTR
 359 #define EMAC0_IPGVR             (EMAC0_BASE + 0x58)
 360 #define EMAC0_I_FRAME_GAP_REG   EMAC0_IPGVR
 361 #define EMAC0_STACR             (EMAC0_BASE + 0x5c)
 362 #define EMAC0_TRTR              (EMAC0_BASE + 0x60)
 363 #define EMAC0_RWMR              (EMAC0_BASE + 0x64)
 364 #define EMAC0_RX_HI_LO_WMARK    EMAC0_RWMR
 365
 366 /* bit definitions */
 367 /* MODE REG 0 */
 368 #define EMAC_MR0_RXI            (0x80000000)
 369 #define EMAC_MR0_TXI            (0x40000000)
 370 #define EMAC_MR0_SRST           (0x20000000)
 371 #define EMAC_MR0_TXE            (0x10000000)
 372 #define EMAC_MR0_RXE            (0x08000000)
 373 #define EMAC_MR0_WKE            (0x04000000)
 374
 375 /* on 440GX EMAC_MR1 has a different layout! */
 376 #if defined(CONFIG_440GX) || \
 377     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
 378     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
 379     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
 380     defined(CONFIG_405EX)
 381 /* MODE Reg 1 */
 382 #define EMAC_MR1_FDE            (0x80000000)
 383 #define EMAC_MR1_ILE            (0x40000000)
 384 #define EMAC_MR1_VLE            (0x20000000)
 385 #define EMAC_MR1_EIFC           (0x10000000)
 386 #define EMAC_MR1_APP            (0x08000000)
 387 #define EMAC_MR1_RSVD           (0x06000000)
 388 #define EMAC_MR1_IST            (0x01000000)
 389 #define EMAC_MR1_MF_1000GPCS    (0x00C00000)
 390 #define EMAC_MR1_MF_1000MBPS    (0x00800000)    /* 0's for 10MBPS */
 391 #define EMAC_MR1_MF_100MBPS     (0x00400000)
 392 #define EMAC_MR1_RFS_MASK       (0x00380000)
 393 #define EMAC_MR1_RFS_16K                (0x00280000)
 394 #define EMAC_MR1_RFS_8K         (0x00200000)
 395 #define EMAC_MR1_RFS_4K         (0x00180000)
 396 #define EMAC_MR1_RFS_2K         (0x00100000)
 397 #define EMAC_MR1_RFS_1K         (0x00080000)
 398 #define EMAC_MR1_TX_FIFO_MASK   (0x00070000)
 399 #define EMAC_MR1_TX_FIFO_16K    (0x00050000)
 400 #define EMAC_MR1_TX_FIFO_8K     (0x00040000)
 401 #define EMAC_MR1_TX_FIFO_4K     (0x00030000)
 402 #define EMAC_MR1_TX_FIFO_2K     (0x00020000)
 403 #define EMAC_MR1_TX_FIFO_1K     (0x00010000)
 404 #define EMAC_MR1_TR_MULTI       (0x00008000)    /* 0'x for single packet */
 405 #define EMAC_MR1_MWSW           (0x00007000)
 406 #define EMAC_MR1_JUMBO_ENABLE   (0x00000800)
 407 #define EMAC_MR1_IPPA           (0x000007c0)
 408 #define EMAC_MR1_IPPA_SET(id)   (((id) & 0x1f) << 6)
 409 #define EMAC_MR1_IPPA_GET(id)   (((id) >> 6) & 0x1f)
 410 #define EMAC_MR1_OBCI_GT100     (0x00000020)
 411 #define EMAC_MR1_OBCI_100       (0x00000018)
 412 #define EMAC_MR1_OBCI_83                (0x00000010)
 413 #define EMAC_MR1_OBCI_66                (0x00000008)
 414 #define EMAC_MR1_RSVD1          (0x00000007)
 415 #else /* defined(CONFIG_440GX) */
 416 /* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
 417 #define EMAC_MR1_FDE            0x80000000
 418 #define EMAC_MR1_ILE            0x40000000
 419 #define EMAC_MR1_VLE            0x20000000
 420 #define EMAC_MR1_EIFC           0x10000000
 421 #define EMAC_MR1_APP            0x08000000
 422 #define EMAC_MR1_AEMI           0x02000000
 423 #define EMAC_MR1_IST            0x01000000
 424 #define EMAC_MR1_MF_1000MBPS    0x00800000      /* 0's for 10MBPS */
 425 #define EMAC_MR1_MF_100MBPS     0x00400000
 426 #define EMAC_MR1_RFS_MASK       0x00300000
 427 #define EMAC_MR1_RFS_4K         0x00300000
 428 #define EMAC_MR1_RFS_2K         0x00200000
 429 #define EMAC_MR1_RFS_1K         0x00100000
 430 #define EMAC_MR1_RFS_512                0x00000000
 431 #define EMAC_MR1_TX_FIFO_MASK   0x000c0000
 432 #define EMAC_MR1_TX_FIFO_2K     0x00080000
 433 #define EMAC_MR1_TX_FIFO_1K     0x00040000
 434 #define EMAC_MR1_TX_FIFO_512    0x00000000
 435 #define EMAC_MR1_TR0_DEPEND     0x00010000      /* 0'x for single packet */
 436 #define EMAC_MR1_TR0_MULTI      0x00008000
 437 #define EMAC_MR1_TR1_DEPEND     0x00004000
 438 #define EMAC_MR1_TR1_MULTI      0x00002000
 439 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 440 #define EMAC_MR1_JUMBO_ENABLE   0x00001000
 441 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
 442 #endif /* defined(CONFIG_440GX) */
 443
 444 #define EMAC_MR1_FIFO_MASK      (EMAC_MR1_RFS_MASK | EMAC_MR1_TX_FIFO_MASK)
 445 #if defined(CONFIG_405EZ)
 446 /* 405EZ only supports 512 bytes fifos */
 447 #define EMAC_MR1_FIFO_SIZE      (EMAC_MR1_RFS_512 | EMAC_MR1_TX_FIFO_512)
 448 #else
 449 /* Set receive fifo to 4k and tx fifo to 2k */
 450 #define EMAC_MR1_FIFO_SIZE      (EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K)
 451 #endif
 452
 453 /* Transmit Mode Register 0 */
 454 #define EMAC_TMR0_GNP0          (0x80000000)
 455 #define EMAC_TMR0_GNP1          (0x40000000)
 456 #define EMAC_TMR0_GNPD          (0x20000000)
 457 #define EMAC_TMR0_FC            (0x10000000)
 458
 459 /* Receive Mode Register */
 460 #define EMAC_RMR_SP             (0x80000000)
 461 #define EMAC_RMR_SFCS           (0x40000000)
 462 #define EMAC_RMR_ARRP           (0x20000000)
 463 #define EMAC_RMR_ARP            (0x10000000)
 464 #define EMAC_RMR_AROP           (0x08000000)
 465 #define EMAC_RMR_ARPI           (0x04000000)
 466 #define EMAC_RMR_PPP            (0x02000000)
 467 #define EMAC_RMR_PME            (0x01000000)
 468 #define EMAC_RMR_PMME           (0x00800000)
 469 #define EMAC_RMR_IAE            (0x00400000)
 470 #define EMAC_RMR_MIAE           (0x00200000)
 471 #define EMAC_RMR_BAE            (0x00100000)
 472 #define EMAC_RMR_MAE            (0x00080000)
 473
 474 /* Interrupt Status & enable Regs */
 475 #define EMAC_ISR_OVR            (0x02000000)
 476 #define EMAC_ISR_PP             (0x01000000)
 477 #define EMAC_ISR_BP             (0x00800000)
 478 #define EMAC_ISR_RP             (0x00400000)
 479 #define EMAC_ISR_SE             (0x00200000)
 480 #define EMAC_ISR_SYE            (0x00100000)
 481 #define EMAC_ISR_BFCS           (0x00080000)
 482 #define EMAC_ISR_PTLE           (0x00040000)
 483 #define EMAC_ISR_ORE            (0x00020000)
 484 #define EMAC_ISR_IRE            (0x00010000)
 485 #define EMAC_ISR_DBDM           (0x00000200)
 486 #define EMAC_ISR_DB0            (0x00000100)
 487 #define EMAC_ISR_SE0            (0x00000080)
 488 #define EMAC_ISR_TE0            (0x00000040)
 489 #define EMAC_ISR_DB1            (0x00000020)
 490 #define EMAC_ISR_SE1            (0x00000010)
 491 #define EMAC_ISR_TE1            (0x00000008)
 492 #define EMAC_ISR_MOS            (0x00000002)
 493 #define EMAC_ISR_MOF            (0x00000001)
 494
 495 /* STA CONTROL REG */
 496 #define EMAC_STACR_OC           (0x00008000)
 497 #define EMAC_STACR_PHYE         (0x00004000)
 498
 499 #ifdef CONFIG_IBM_EMAC4_V4      /* EMAC4 V4 changed bit setting */
 500 #define EMAC_STACR_INDIRECT_MODE (0x00002000)
 501 #define EMAC_STACR_WRITE        (0x00000800) /* $BUC */
 502 #define EMAC_STACR_READ         (0x00001000) /* $BUC */
 503 #define EMAC_STACR_OP_MASK      (0x00001800)
 504 #define EMAC_STACR_MDIO_ADDR    (0x00000000)
 505 #define EMAC_STACR_MDIO_WRITE   (0x00000800)
 506 #define EMAC_STACR_MDIO_READ    (0x00001800)
 507 #define EMAC_STACR_MDIO_READ_INC (0x00001000)
 508 #else
 509 #define EMAC_STACR_WRITE        (0x00002000)
 510 #define EMAC_STACR_READ         (0x00001000)
 511 #endif
 512
 513 #define EMAC_STACR_CLK_83MHZ    (0x00000800)  /* 0's for 50Mhz */
 514 #define EMAC_STACR_CLK_66MHZ    (0x00000400)
 515 #define EMAC_STACR_CLK_100MHZ   (0x00000C00)
 516
 517 /* Transmit Request Threshold Register */
 518 #define EMAC_TRTR_256           (0x18000000)   /* 0's for 64 Bytes */
 519 #define EMAC_TRTR_192           (0x10000000)
 520 #define EMAC_TRTR_128           (0x01000000)
 521
 522 /* the follwing defines are for the MadMAL status and control registers. */
 523 /* For bits 0..5 look at the mal.h file                                  */
 524 #define EMAC_TX_CTRL_GFCS       (0x0200)
 525 #define EMAC_TX_CTRL_GP         (0x0100)
 526 #define EMAC_TX_CTRL_ISA        (0x0080)
 527 #define EMAC_TX_CTRL_RSA        (0x0040)
 528 #define EMAC_TX_CTRL_IVT        (0x0020)
 529 #define EMAC_TX_CTRL_RVT        (0x0010)
 530
 531 #define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP)
 532
 533 #define EMAC_TX_ST_BFCS         (0x0200)
 534 #define EMAC_TX_ST_BPP          (0x0100)
 535 #define EMAC_TX_ST_LCS          (0x0080)
 536 #define EMAC_TX_ST_ED           (0x0040)
 537 #define EMAC_TX_ST_EC           (0x0020)
 538 #define EMAC_TX_ST_LC           (0x0010)
 539 #define EMAC_TX_ST_MC           (0x0008)
 540 #define EMAC_TX_ST_SC           (0x0004)
 541 #define EMAC_TX_ST_UR           (0x0002)
 542 #define EMAC_TX_ST_SQE          (0x0001)
 543
 544 #define EMAC_TX_ST_DEFAULT      (0x03F3)
 545
 546
 547 /* madmal receive status / Control bits */
 548
 549 #define EMAC_RX_ST_OE           (0x0200)
 550 #define EMAC_RX_ST_PP           (0x0100)
 551 #define EMAC_RX_ST_BP           (0x0080)
 552 #define EMAC_RX_ST_RP           (0x0040)
 553 #define EMAC_RX_ST_SE           (0x0020)
 554 #define EMAC_RX_ST_AE           (0x0010)
 555 #define EMAC_RX_ST_BFCS         (0x0008)
 556 #define EMAC_RX_ST_PTL          (0x0004)
 557 #define EMAC_RX_ST_ORE          (0x0002)
 558 #define EMAC_RX_ST_IRE          (0x0001)
 559 /* all the errors we care about */
 560 #define EMAC_RX_ERRORS          (0x03FF)
 561
 562 #endif /* _PPC4XX_ENET_H_ */