include/ppc4xx_enet.h

   1 /*----------------------------------------------------------------------------+
   2 |
   3 |       This source code has been made available to you by IBM on an AS-IS
   4 |       basis.  Anyone receiving this source is licensed under IBM
   5 |       copyrights to use it in any way he or she deems fit, including
   6 |       copying it, modifying it, compiling it, and redistributing it either
   7 |       with or without modifications.  No license under IBM patents or
   8 |       patent applications is to be implied by the copyright license.
   9 |
  10 |       Any user of this software should understand that IBM cannot provide
  11 |       technical support for this software and will not be responsible for
  12 |       any consequences resulting from the use of this software.
  13 |
  14 |       Any person who transfers this source code or any derivative work
  15 |       must include the IBM copyright notice, this paragraph, and the
  16 |       preceding two paragraphs in the transferred software.
  17 |
  18 |       COPYRIGHT   I B M   CORPORATION 1999
  19 |       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  20 +----------------------------------------------------------------------------*/
  21 /*----------------------------------------------------------------------------+
  22 |
  23 |  File Name:   enetemac.h
  24 |
  25 |  Function:    Header file for the EMAC3 macro on the 405GP.
  26 |
  27 |  Author:      Mark Wisner
  28 |
  29 |  Change Activity-
  30 |
  31 |  Date        Description of Change                                       BY
  32 |  ---------   ---------------------                                       ---
  33 |  29-Apr-99   Created                                                     MKW
  34 |
  35 +----------------------------------------------------------------------------*/
  36 /*----------------------------------------------------------------------------+
  37 |  19-Nov-03   Travis Sawyer, Sandburst Corporation, tsawyer@sandburst.com
  38 |              ported to handle 440GP and 440GX multiple EMACs
  39 +----------------------------------------------------------------------------*/
  40
  41 #ifndef _PPC4XX_ENET_H_
  42 #define _PPC4XX_ENET_H_
  43
  44 #include <net.h>
  45 #include "405_mal.h"
  46
  47
  48 /*-----------------------------------------------------------------------------+
  49 | General enternet defines.  802 frames are not supported.
  50 +-----------------------------------------------------------------------------*/
  51 #define ENET_ADDR_LENGTH                6
  52 #define ENET_ARPTYPE                    0x806
  53 #define ARP_REQUEST                     1
  54 #define ARP_REPLY                       2
  55 #define ENET_IPTYPE                     0x800
  56 #define ARP_CACHE_SIZE                  5
  57
  58 #define NUM_TX_BUFF 1
  59 #define NUM_RX_BUFF PKTBUFSRX
  60
  61 struct enet_frame {
  62    unsigned char        dest_addr[ENET_ADDR_LENGTH];
  63    unsigned char        source_addr[ENET_ADDR_LENGTH];
  64    unsigned short       type;
  65    unsigned char        enet_data[1];
  66 };
  67
  68 struct arp_entry {
  69    unsigned long        inet_address;
  70    unsigned char        mac_address[ENET_ADDR_LENGTH];
  71    unsigned long        valid;
  72    unsigned long        sec;
  73    unsigned long        nsec;
  74 };
  75
  76
  77 /* Statistic Areas */
  78 #define MAX_ERR_LOG 10
  79
  80 typedef struct emac_stats_st{   /* Statistic Block */
  81         int data_len_err;
  82         int rx_frames;
  83         int rx;
  84         int rx_prot_err;
  85         int int_err;
  86         int pkts_tx;
  87         int pkts_rx;
  88         int pkts_handled;
  89         short tx_err_log[MAX_ERR_LOG];
  90         short rx_err_log[MAX_ERR_LOG];
  91 } EMAC_STATS_ST, *EMAC_STATS_PST;
  92
  93 /* Structure containing variables used by the shared code (4xx_enet.c) */
  94 typedef struct emac_4xx_hw_st {
  95     uint32_t            hw_addr;                /* EMAC offset */
  96     uint32_t            tah_addr;               /* TAH offset */
  97     uint32_t            phy_id;
  98     uint32_t            phy_addr;
  99     uint32_t            original_fc;
 100     uint32_t            txcw;
 101     uint32_t            autoneg_failed;
 102     uint32_t            emac_ier;
 103     volatile mal_desc_t *tx;
 104     volatile mal_desc_t *rx;
 105     u32                 tx_phys;
 106     u32                 rx_phys;
 107     bd_t                *bis;   /* for eth_init upon mal error */
 108     mal_desc_t          *alloc_tx_buf;
 109     mal_desc_t          *alloc_rx_buf;
 110     char                *txbuf_ptr;
 111     uint16_t            devnum;
 112     int                 get_link_status;
 113     int                 tbi_compatibility_en;
 114     int                 tbi_compatibility_on;
 115     int                 fc_send_xon;
 116     int                 report_tx_early;
 117     int                 first_init;
 118     int                 tx_err_index;
 119     int                 rx_err_index;
 120     int                 rx_slot;                        /* MAL Receive Slot */
 121     int                 rx_i_index;             /* Receive Interrupt Queue Index */
 122     int                 rx_u_index;             /* Receive User Queue Index */
 123     int                 tx_slot;                        /* MAL Transmit Slot */
 124     int                 tx_i_index;             /* Transmit Interrupt Queue Index */
 125     int                 tx_u_index;             /* Transmit User Queue Index */
 126     int                 rx_ready[NUM_RX_BUFF];  /* Receive Ready Queue */
 127     int                 tx_run[NUM_TX_BUFF];    /* Transmit Running Queue */
 128     int                 is_receiving;   /* sync with eth interrupt */
 129     int                 print_speed;    /* print speed message upon start */
 130     EMAC_STATS_ST       stats;
 131 } EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST;
 132
 133
 134 #if defined(CONFIG_440GX) || defined(CONFIG_460GT)
 135 #define EMAC_NUM_DEV            4
 136 #elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
 137         defined(CONFIG_NET_MULTI) &&                    \
 138         !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
 139 #define EMAC_NUM_DEV            2
 140 #else
 141 #define EMAC_NUM_DEV            1
 142 #endif
 143
 144 #ifdef CONFIG_IBM_EMAC4_V4      /* EMAC4 V4 changed bit setting */
 145 #define EMAC_STACR_OC_MASK      (0x00008000)
 146 #else
 147 #define EMAC_STACR_OC_MASK      (0x00000000)
 148 #endif
 149
 150 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
 151     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
 152     defined(CONFIG_405EX)
 153 #define SDR0_PFC1_EM_1000       (0x00200000)
 154 #endif
 155
 156 /*
 157  * XMII bridge configurations for those systems (e.g. 405EX(r)) that do
 158  * not have a pin function control (PFC) register to otherwise determine
 159  * the bridge configuration.
 160  */
 161 #define EMAC_PHY_MODE_NONE              0
 162 #define EMAC_PHY_MODE_NONE_RGMII        1
 163 #define EMAC_PHY_MODE_RGMII_NONE        2
 164 #define EMAC_PHY_MODE_RGMII_RGMII       3
 165 #define EMAC_PHY_MODE_NONE_GMII         4
 166 #define EMAC_PHY_MODE_GMII_NONE         5
 167 #define EMAC_PHY_MODE_NONE_MII          6
 168 #define EMAC_PHY_MODE_MII_NONE          7
 169
 170 /* ZMII Bridge Register addresses */
 171 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
 172     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
 173     defined(CONFIG_460EX) || defined(CONFIG_460GT)
 174 #define ZMII_BASE               (CONFIG_SYS_PERIPHERAL_BASE + 0x0D00)
 175 #else
 176 #define ZMII_BASE               (CONFIG_SYS_PERIPHERAL_BASE + 0x0780)
 177 #endif
 178 #define ZMII_FER                (ZMII_BASE)
 179 #define ZMII_SSR                (ZMII_BASE + 4)
 180 #define ZMII_SMIISR             (ZMII_BASE + 8)
 181
 182 /* ZMII FER Register Bit Definitions */
 183 #define ZMII_FER_DIS            (0x0)
 184 #define ZMII_FER_MDI            (0x8)
 185 #define ZMII_FER_SMII           (0x4)
 186 #define ZMII_FER_RMII           (0x2)
 187 #define ZMII_FER_MII            (0x1)
 188
 189 #define ZMII_FER_RSVD11         (0x00200000)
 190 #define ZMII_FER_RSVD10         (0x00100000)
 191 #define ZMII_FER_RSVD14_31      (0x0003FFFF)
 192
 193 #define ZMII_FER_V(__x)         (((3 - __x) * 4) + 16)
 194
 195
 196 /* ZMII Speed Selection Register Bit Definitions */
 197 #define ZMII_SSR_SCI            (0x4)
 198 #define ZMII_SSR_FSS            (0x2)
 199 #define ZMII_SSR_SP             (0x1)
 200 #define ZMII_SSR_RSVD16_31      (0x0000FFFF)
 201
 202 #define ZMII_SSR_V(__x)         (((3 - __x) * 4) + 16)
 203
 204
 205 /* ZMII SMII Status Register Bit Definitions */
 206 #define ZMII_SMIISR_E1          (0x80)
 207 #define ZMII_SMIISR_EC          (0x40)
 208 #define ZMII_SMIISR_EN          (0x20)
 209 #define ZMII_SMIISR_EJ          (0x10)
 210 #define ZMII_SMIISR_EL          (0x08)
 211 #define ZMII_SMIISR_ED          (0x04)
 212 #define ZMII_SMIISR_ES          (0x02)
 213 #define ZMII_SMIISR_EF          (0x01)
 214
 215 #define ZMII_SMIISR_V(__x)      ((3 - __x) * 8)
 216
 217 /* RGMII Register Addresses */
 218 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 219 #define RGMII_BASE              (CONFIG_SYS_PERIPHERAL_BASE + 0x1000)
 220 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
 221 #define RGMII_BASE              (CONFIG_SYS_PERIPHERAL_BASE + 0x1500)
 222 #elif defined(CONFIG_405EX)
 223 #define RGMII_BASE              (CONFIG_SYS_PERIPHERAL_BASE + 0xB00)
 224 #else
 225 #define RGMII_BASE              (CONFIG_SYS_PERIPHERAL_BASE + 0x0790)
 226 #endif
 227 #define RGMII_FER               (RGMII_BASE + 0x00)
 228 #define RGMII_SSR               (RGMII_BASE + 0x04)
 229
 230 #if defined(CONFIG_460GT)
 231 #define RGMII1_BASE_OFFSET      0x100
 232 #endif
 233
 234 /* RGMII Function Enable (FER) Register Bit Definitions */
 235 #define RGMII_FER_DIS           (0x00)
 236 #define RGMII_FER_RTBI          (0x04)
 237 #define RGMII_FER_RGMII         (0x05)
 238 #define RGMII_FER_TBI           (0x06)
 239 #define RGMII_FER_GMII          (0x07)
 240 #define RGMII_FER_MII           (RGMII_FER_GMII)
 241
 242 #define RGMII_FER_V(__x)        ((__x - 2) * 4)
 243
 244 #define RGMII_FER_MDIO(__x)     (1 << (19 - (__x)))
 245
 246 /* RGMII Speed Selection Register Bit Definitions */
 247 #define RGMII_SSR_SP_10MBPS     (0x00)
 248 #define RGMII_SSR_SP_100MBPS    (0x02)
 249 #define RGMII_SSR_SP_1000MBPS   (0x04)
 250
 251 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
 252     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
 253     defined(CONFIG_405EX)
 254 #define RGMII_SSR_V(__x)        ((__x) * 8)
 255 #else
 256 #define RGMII_SSR_V(__x)        ((__x -2) * 8)
 257 #endif
 258
 259 /*---------------------------------------------------------------------------+
 260 |  TCP/IP Acceleration Hardware (TAH) 440GX Only
 261 +---------------------------------------------------------------------------*/
 262 #if defined(CONFIG_440GX)
 263 #define TAH_BASE                (CONFIG_SYS_PERIPHERAL_BASE + 0x0B50)
 264 #define TAH_REVID               (TAH_BASE + 0x0)    /* Revision ID (RO)*/
 265 #define TAH_MR                  (TAH_BASE + 0x10)   /* Mode Register (R/W) */
 266 #define TAH_SSR0                (TAH_BASE + 0x14)   /* Segment Size Reg 0 (R/W) */
 267 #define TAH_SSR1                (TAH_BASE + 0x18)   /* Segment Size Reg 1 (R/W) */
 268 #define TAH_SSR2                (TAH_BASE + 0x1C)   /* Segment Size Reg 2 (R/W) */
 269 #define TAH_SSR3                (TAH_BASE + 0x20)   /* Segment Size Reg 3 (R/W) */
 270 #define TAH_SSR4                (TAH_BASE + 0x24)   /* Segment Size Reg 4 (R/W) */
 271 #define TAH_SSR5                (TAH_BASE + 0x28)   /* Segment Size Reg 5 (R/W) */
 272 #define TAH_TSR                 (TAH_BASE + 0x2C)   /* Transmit Status Register (RO) */
 273
 274 /* TAH Revision */
 275 #define TAH_REV_RN_M            (0x000FFF00)        /* Revision Number */
 276 #define TAH_REV_BN_M            (0x000000FF)        /* Branch Revision Number */
 277
 278 #define TAH_REV_RN_V            (8)
 279 #define TAH_REV_BN_V            (0)
 280
 281 /* TAH Mode Register */
 282 #define TAH_MR_CVR              (0x80000000)        /* Checksum verification on RX */
 283 #define TAH_MR_SR               (0x40000000)        /* Software reset */
 284 #define TAH_MR_ST               (0x3F000000)        /* Send Threshold */
 285 #define TAH_MR_TFS              (0x00E00000)        /* Transmit FIFO size */
 286 #define TAH_MR_DTFP             (0x00100000)        /* Disable TX FIFO parity */
 287 #define TAH_MR_DIG              (0x00080000)        /* Disable interrupt generation */
 288 #define TAH_MR_RSVD             (0x0007FFFF)        /* Reserved */
 289
 290 #define TAH_MR_ST_V             (20)
 291 #define TAH_MR_TFS_V            (17)
 292
 293 #define TAH_MR_TFS_2K           (0x1)               /* Transmit FIFO size 2Kbyte */
 294 #define TAH_MR_TFS_4K           (0x2)               /* Transmit FIFO size 4Kbyte */
 295 #define TAH_MR_TFS_6K           (0x3)               /* Transmit FIFO size 6Kbyte */
 296 #define TAH_MR_TFS_8K           (0x4)               /* Transmit FIFO size 8Kbyte */
 297 #define TAH_MR_TFS_10K          (0x5)               /* Transmit FIFO size 10Kbyte (max)*/
 298
 299
 300 /* TAH Segment Size Registers 0:5 */
 301 #define TAH_SSR_RSVD0           (0xC0000000)        /* Reserved */
 302 #define TAH_SSR_SS              (0x3FFE0000)        /* Segment size in multiples of 2 */
 303 #define TAH_SSR_RSVD1           (0x0001FFFF)        /* Reserved */
 304
 305 /* TAH Transmit Status Register */
 306 #define TAH_TSR_TFTS            (0x80000000)        /* Transmit FIFO too small */
 307 #define TAH_TSR_UH              (0x40000000)        /* Unrecognized header */
 308 #define TAH_TSR_NIPF            (0x20000000)        /* Not IPv4 */
 309 #define TAH_TSR_IPOP            (0x10000000)        /* IP option present */
 310 #define TAH_TSR_NISF            (0x08000000)        /* No IEEE SNAP format */
 311 #define TAH_TSR_ILTS            (0x04000000)        /* IP length too short */
 312 #define TAH_TSR_IPFP            (0x02000000)        /* IP fragment present */
 313 #define TAH_TSR_UP              (0x01000000)        /* Unsupported protocol */
 314 #define TAH_TSR_TFP             (0x00800000)        /* TCP flags present */
 315 #define TAH_TSR_SUDP            (0x00400000)        /* Segmentation for UDP */
 316 #define TAH_TSR_DLM             (0x00200000)        /* Data length mismatch */
 317 #define TAH_TSR_SIEEE           (0x00100000)        /* Segmentation for IEEE */
 318 #define TAH_TSR_TFPE            (0x00080000)        /* Transmit FIFO parity error */
 319 #define TAH_TSR_SSTS            (0x00040000)        /* Segment size too small */
 320 #define TAH_TSR_RSVD            (0x0003FFFF)        /* Reserved */
 321 #endif /* CONFIG_440GX */
 322
 323
 324 /* Ethernet MAC Regsiter Addresses */
 325 #if defined(CONFIG_440)
 326 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
 327     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
 328     defined(CONFIG_460EX) || defined(CONFIG_460GT)
 329 #define EMAC_BASE               (CONFIG_SYS_PERIPHERAL_BASE + 0x0E00)
 330 #else
 331 #define EMAC_BASE               (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
 332 #endif
 333 #else
 334 #if defined(CONFIG_405EZ) || defined(CONFIG_405EX)
 335 #define EMAC_BASE               0xEF600900
 336 #else
 337 #define EMAC_BASE               0xEF600800
 338 #endif
 339 #endif
 340
 341 #define EMAC_M0                 (EMAC_BASE)
 342 #define EMAC_M1                 (EMAC_BASE + 4)
 343 #define EMAC_TXM0               (EMAC_BASE + 8)
 344 #define EMAC_TXM1               (EMAC_BASE + 12)
 345 #define EMAC_RXM                (EMAC_BASE + 16)
 346 #define EMAC_ISR                (EMAC_BASE + 20)
 347 #define EMAC_IER                (EMAC_BASE + 24)
 348 #define EMAC_IAH                (EMAC_BASE + 28)
 349 #define EMAC_IAL                (EMAC_BASE + 32)
 350 #define EMAC_PAUSE_TIME_REG     (EMAC_BASE + 44)
 351 #define EMAC_I_FRAME_GAP_REG    (EMAC_BASE + 88)
 352 #define EMAC_STACR              (EMAC_BASE + 92)
 353 #define EMAC_TRTR               (EMAC_BASE + 96)
 354 #define EMAC_RX_HI_LO_WMARK     (EMAC_BASE + 100)
 355
 356 /* bit definitions */
 357 /* MODE REG 0 */
 358 #define EMAC_M0_RXI             (0x80000000)
 359 #define EMAC_M0_TXI             (0x40000000)
 360 #define EMAC_M0_SRST            (0x20000000)
 361 #define EMAC_M0_TXE             (0x10000000)
 362 #define EMAC_M0_RXE             (0x08000000)
 363 #define EMAC_M0_WKE             (0x04000000)
 364
 365 /* on 440GX EMAC_MR1 has a different layout! */
 366 #if defined(CONFIG_440GX) || \
 367     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
 368     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
 369     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
 370     defined(CONFIG_405EX)
 371 /* MODE Reg 1 */
 372 #define EMAC_M1_FDE             (0x80000000)
 373 #define EMAC_M1_ILE             (0x40000000)
 374 #define EMAC_M1_VLE             (0x20000000)
 375 #define EMAC_M1_EIFC            (0x10000000)
 376 #define EMAC_M1_APP             (0x08000000)
 377 #define EMAC_M1_RSVD            (0x06000000)
 378 #define EMAC_M1_IST             (0x01000000)
 379 #define EMAC_M1_MF_1000GPCS     (0x00C00000)
 380 #define EMAC_M1_MF_1000MBPS     (0x00800000)    /* 0's for 10MBPS */
 381 #define EMAC_M1_MF_100MBPS      (0x00400000)
 382 #define EMAC_M1_RFS_MASK        (0x00380000)
 383 #define EMAC_M1_RFS_16K         (0x00280000)
 384 #define EMAC_M1_RFS_8K          (0x00200000)
 385 #define EMAC_M1_RFS_4K          (0x00180000)
 386 #define EMAC_M1_RFS_2K          (0x00100000)
 387 #define EMAC_M1_RFS_1K          (0x00080000)
 388 #define EMAC_M1_TX_FIFO_MASK    (0x00070000)
 389 #define EMAC_M1_TX_FIFO_16K     (0x00050000)
 390 #define EMAC_M1_TX_FIFO_8K      (0x00040000)
 391 #define EMAC_M1_TX_FIFO_4K      (0x00030000)
 392 #define EMAC_M1_TX_FIFO_2K      (0x00020000)
 393 #define EMAC_M1_TX_FIFO_1K      (0x00010000)
 394 #define EMAC_M1_TR_MULTI        (0x00008000)    /* 0'x for single packet */
 395 #define EMAC_M1_MWSW            (0x00007000)
 396 #define EMAC_M1_JUMBO_ENABLE    (0x00000800)
 397 #define EMAC_M1_IPPA            (0x000007c0)
 398 #define EMAC_M1_IPPA_SET(id)    (((id) & 0x1f) << 6)
 399 #define EMAC_M1_IPPA_GET(id)    (((id) >> 6) & 0x1f)
 400 #define EMAC_M1_OBCI_GT100      (0x00000020)
 401 #define EMAC_M1_OBCI_100        (0x00000018)
 402 #define EMAC_M1_OBCI_83         (0x00000010)
 403 #define EMAC_M1_OBCI_66         (0x00000008)
 404 #define EMAC_M1_RSVD1           (0x00000007)
 405 #else /* defined(CONFIG_440GX) */
 406 /* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
 407 #define EMAC_M1_FDE             0x80000000
 408 #define EMAC_M1_ILE             0x40000000
 409 #define EMAC_M1_VLE             0x20000000
 410 #define EMAC_M1_EIFC            0x10000000
 411 #define EMAC_M1_APP             0x08000000
 412 #define EMAC_M1_AEMI            0x02000000
 413 #define EMAC_M1_IST             0x01000000
 414 #define EMAC_M1_MF_1000MBPS     0x00800000      /* 0's for 10MBPS */
 415 #define EMAC_M1_MF_100MBPS      0x00400000
 416 #define EMAC_M1_RFS_MASK        0x00300000
 417 #define EMAC_M1_RFS_4K          0x00300000
 418 #define EMAC_M1_RFS_2K          0x00200000
 419 #define EMAC_M1_RFS_1K          0x00100000
 420 #define EMAC_M1_RFS_512         0x00000000
 421 #define EMAC_M1_TX_FIFO_MASK    0x000c0000
 422 #define EMAC_M1_TX_FIFO_2K      0x00080000
 423 #define EMAC_M1_TX_FIFO_1K      0x00040000
 424 #define EMAC_M1_TX_FIFO_512     0x00000000
 425 #define EMAC_M1_TR0_DEPEND      0x00010000      /* 0'x for single packet */
 426 #define EMAC_M1_TR0_MULTI       0x00008000
 427 #define EMAC_M1_TR1_DEPEND      0x00004000
 428 #define EMAC_M1_TR1_MULTI       0x00002000
 429 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 430 #define EMAC_M1_JUMBO_ENABLE    0x00001000
 431 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
 432 #endif /* defined(CONFIG_440GX) */
 433
 434 #define EMAC_MR1_FIFO_MASK      (EMAC_M1_RFS_MASK | EMAC_M1_TX_FIFO_MASK)
 435 #if defined(CONFIG_405EZ)
 436 /* 405EZ only supports 512 bytes fifos */
 437 #define EMAC_MR1_FIFO_SIZE      (EMAC_M1_RFS_512 | EMAC_M1_TX_FIFO_512)
 438 #else
 439 /* Set receive fifo to 4k and tx fifo to 2k */
 440 #define EMAC_MR1_FIFO_SIZE      (EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K)
 441 #endif
 442
 443 /* Transmit Mode Register 0 */
 444 #define EMAC_TXM0_GNP0          (0x80000000)
 445 #define EMAC_TXM0_GNP1          (0x40000000)
 446 #define EMAC_TXM0_GNPD          (0x20000000)
 447 #define EMAC_TXM0_FC            (0x10000000)
 448
 449 /* Receive Mode Register */
 450 #define EMAC_RMR_SP             (0x80000000)
 451 #define EMAC_RMR_SFCS           (0x40000000)
 452 #define EMAC_RMR_ARRP           (0x20000000)
 453 #define EMAC_RMR_ARP            (0x10000000)
 454 #define EMAC_RMR_AROP           (0x08000000)
 455 #define EMAC_RMR_ARPI           (0x04000000)
 456 #define EMAC_RMR_PPP            (0x02000000)
 457 #define EMAC_RMR_PME            (0x01000000)
 458 #define EMAC_RMR_PMME           (0x00800000)
 459 #define EMAC_RMR_IAE            (0x00400000)
 460 #define EMAC_RMR_MIAE           (0x00200000)
 461 #define EMAC_RMR_BAE            (0x00100000)
 462 #define EMAC_RMR_MAE            (0x00080000)
 463
 464 /* Interrupt Status & enable Regs */
 465 #define EMAC_ISR_OVR            (0x02000000)
 466 #define EMAC_ISR_PP             (0x01000000)
 467 #define EMAC_ISR_BP             (0x00800000)
 468 #define EMAC_ISR_RP             (0x00400000)
 469 #define EMAC_ISR_SE             (0x00200000)
 470 #define EMAC_ISR_SYE            (0x00100000)
 471 #define EMAC_ISR_BFCS           (0x00080000)
 472 #define EMAC_ISR_PTLE           (0x00040000)
 473 #define EMAC_ISR_ORE            (0x00020000)
 474 #define EMAC_ISR_IRE            (0x00010000)
 475 #define EMAC_ISR_DBDM           (0x00000200)
 476 #define EMAC_ISR_DB0            (0x00000100)
 477 #define EMAC_ISR_SE0            (0x00000080)
 478 #define EMAC_ISR_TE0            (0x00000040)
 479 #define EMAC_ISR_DB1            (0x00000020)
 480 #define EMAC_ISR_SE1            (0x00000010)
 481 #define EMAC_ISR_TE1            (0x00000008)
 482 #define EMAC_ISR_MOS            (0x00000002)
 483 #define EMAC_ISR_MOF            (0x00000001)
 484
 485 /* STA CONTROL REG */
 486 #define EMAC_STACR_OC           (0x00008000)
 487 #define EMAC_STACR_PHYE         (0x00004000)
 488
 489 #ifdef CONFIG_IBM_EMAC4_V4      /* EMAC4 V4 changed bit setting */
 490 #define EMAC_STACR_INDIRECT_MODE (0x00002000)
 491 #define EMAC_STACR_WRITE        (0x00000800) /* $BUC */
 492 #define EMAC_STACR_READ         (0x00001000) /* $BUC */
 493 #define EMAC_STACR_OP_MASK      (0x00001800)
 494 #define EMAC_STACR_MDIO_ADDR    (0x00000000)
 495 #define EMAC_STACR_MDIO_WRITE   (0x00000800)
 496 #define EMAC_STACR_MDIO_READ    (0x00001800)
 497 #define EMAC_STACR_MDIO_READ_INC (0x00001000)
 498 #else
 499 #define EMAC_STACR_WRITE        (0x00002000)
 500 #define EMAC_STACR_READ         (0x00001000)
 501 #endif
 502
 503 #define EMAC_STACR_CLK_83MHZ    (0x00000800)  /* 0's for 50Mhz */
 504 #define EMAC_STACR_CLK_66MHZ    (0x00000400)
 505 #define EMAC_STACR_CLK_100MHZ   (0x00000C00)
 506
 507 /* Transmit Request Threshold Register */
 508 #define EMAC_TRTR_256           (0x18000000)   /* 0's for 64 Bytes */
 509 #define EMAC_TRTR_192           (0x10000000)
 510 #define EMAC_TRTR_128           (0x01000000)
 511
 512 /* the follwing defines are for the MadMAL status and control registers. */
 513 /* For bits 0..5 look at the mal.h file                                  */
 514 #define EMAC_TX_CTRL_GFCS       (0x0200)
 515 #define EMAC_TX_CTRL_GP         (0x0100)
 516 #define EMAC_TX_CTRL_ISA        (0x0080)
 517 #define EMAC_TX_CTRL_RSA        (0x0040)
 518 #define EMAC_TX_CTRL_IVT        (0x0020)
 519 #define EMAC_TX_CTRL_RVT        (0x0010)
 520
 521 #define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP)
 522
 523 #define EMAC_TX_ST_BFCS         (0x0200)
 524 #define EMAC_TX_ST_BPP          (0x0100)
 525 #define EMAC_TX_ST_LCS          (0x0080)
 526 #define EMAC_TX_ST_ED           (0x0040)
 527 #define EMAC_TX_ST_EC           (0x0020)
 528 #define EMAC_TX_ST_LC           (0x0010)
 529 #define EMAC_TX_ST_MC           (0x0008)
 530 #define EMAC_TX_ST_SC           (0x0004)
 531 #define EMAC_TX_ST_UR           (0x0002)
 532 #define EMAC_TX_ST_SQE          (0x0001)
 533
 534 #define EMAC_TX_ST_DEFAULT      (0x03F3)
 535
 536
 537 /* madmal receive status / Control bits */
 538
 539 #define EMAC_RX_ST_OE           (0x0200)
 540 #define EMAC_RX_ST_PP           (0x0100)
 541 #define EMAC_RX_ST_BP           (0x0080)
 542 #define EMAC_RX_ST_RP           (0x0040)
 543 #define EMAC_RX_ST_SE           (0x0020)
 544 #define EMAC_RX_ST_AE           (0x0010)
 545 #define EMAC_RX_ST_BFCS         (0x0008)
 546 #define EMAC_RX_ST_PTL          (0x0004)
 547 #define EMAC_RX_ST_ORE          (0x0002)
 548 #define EMAC_RX_ST_IRE          (0x0001)
 549 /* all the errors we care about */
 550 #define EMAC_RX_ERRORS          (0x03FF)
 551
 552 #endif /* _PPC4XX_ENET_H_ */