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[thirdparty/u-boot.git] / include / sdhci.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright 2011, Marvell Semiconductor Inc.
4 * Lei Wen <leiwen@marvell.com>
5 *
6 * Back ported to the 8xx platform (from the 8260 platform) by
7 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
8 */
9 #ifndef __SDHCI_HW_H
10 #define __SDHCI_HW_H
11
12 #include <linux/types.h>
13 #include <asm/io.h>
14 #include <mmc.h>
15 #include <asm/gpio.h>
16
17 /*
18 * Controller registers
19 */
20
21 #define SDHCI_DMA_ADDRESS 0x00
22
23 #define SDHCI_BLOCK_SIZE 0x04
24 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
25
26 #define SDHCI_BLOCK_COUNT 0x06
27
28 #define SDHCI_ARGUMENT 0x08
29
30 #define SDHCI_TRANSFER_MODE 0x0C
31 #define SDHCI_TRNS_DMA BIT(0)
32 #define SDHCI_TRNS_BLK_CNT_EN BIT(1)
33 #define SDHCI_TRNS_ACMD12 BIT(2)
34 #define SDHCI_TRNS_READ BIT(4)
35 #define SDHCI_TRNS_MULTI BIT(5)
36
37 #define SDHCI_COMMAND 0x0E
38 #define SDHCI_CMD_RESP_MASK 0x03
39 #define SDHCI_CMD_CRC 0x08
40 #define SDHCI_CMD_INDEX 0x10
41 #define SDHCI_CMD_DATA 0x20
42 #define SDHCI_CMD_ABORTCMD 0xC0
43
44 #define SDHCI_CMD_RESP_NONE 0x00
45 #define SDHCI_CMD_RESP_LONG 0x01
46 #define SDHCI_CMD_RESP_SHORT 0x02
47 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03
48
49 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
50 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
51
52 #define SDHCI_RESPONSE 0x10
53
54 #define SDHCI_BUFFER 0x20
55
56 #define SDHCI_PRESENT_STATE 0x24
57 #define SDHCI_CMD_INHIBIT BIT(0)
58 #define SDHCI_DATA_INHIBIT BIT(1)
59 #define SDHCI_DOING_WRITE BIT(8)
60 #define SDHCI_DOING_READ BIT(9)
61 #define SDHCI_SPACE_AVAILABLE BIT(10)
62 #define SDHCI_DATA_AVAILABLE BIT(11)
63 #define SDHCI_CARD_PRESENT BIT(16)
64 #define SDHCI_CARD_STATE_STABLE BIT(17)
65 #define SDHCI_CARD_DETECT_PIN_LEVEL BIT(18)
66 #define SDHCI_WRITE_PROTECT BIT(19)
67
68 #define SDHCI_HOST_CONTROL 0x28
69 #define SDHCI_CTRL_LED BIT(0)
70 #define SDHCI_CTRL_4BITBUS BIT(1)
71 #define SDHCI_CTRL_HISPD BIT(2)
72 #define SDHCI_CTRL_DMA_MASK 0x18
73 #define SDHCI_CTRL_SDMA 0x00
74 #define SDHCI_CTRL_ADMA1 0x08
75 #define SDHCI_CTRL_ADMA32 0x10
76 #define SDHCI_CTRL_ADMA64 0x18
77 #define SDHCI_CTRL_8BITBUS BIT(5)
78 #define SDHCI_CTRL_CD_TEST_INS BIT(6)
79 #define SDHCI_CTRL_CD_TEST BIT(7)
80
81 #define SDHCI_POWER_CONTROL 0x29
82 #define SDHCI_POWER_ON 0x01
83 #define SDHCI_POWER_180 0x0A
84 #define SDHCI_POWER_300 0x0C
85 #define SDHCI_POWER_330 0x0E
86
87 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
88
89 #define SDHCI_WAKE_UP_CONTROL 0x2B
90 #define SDHCI_WAKE_ON_INT BIT(0)
91 #define SDHCI_WAKE_ON_INSERT BIT(1)
92 #define SDHCI_WAKE_ON_REMOVE BIT(2)
93
94 #define SDHCI_CLOCK_CONTROL 0x2C
95 #define SDHCI_DIVIDER_SHIFT 8
96 #define SDHCI_DIVIDER_HI_SHIFT 6
97 #define SDHCI_DIV_MASK 0xFF
98 #define SDHCI_DIV_MASK_LEN 8
99 #define SDHCI_DIV_HI_MASK 0x300
100 #define SDHCI_PROG_CLOCK_MODE BIT(5)
101 #define SDHCI_CLOCK_CARD_EN BIT(2)
102 #define SDHCI_CLOCK_INT_STABLE BIT(1)
103 #define SDHCI_CLOCK_INT_EN BIT(0)
104
105 #define SDHCI_TIMEOUT_CONTROL 0x2E
106
107 #define SDHCI_SOFTWARE_RESET 0x2F
108 #define SDHCI_RESET_ALL 0x01
109 #define SDHCI_RESET_CMD 0x02
110 #define SDHCI_RESET_DATA 0x04
111
112 #define SDHCI_INT_STATUS 0x30
113 #define SDHCI_INT_ENABLE 0x34
114 #define SDHCI_SIGNAL_ENABLE 0x38
115 #define SDHCI_INT_RESPONSE BIT(0)
116 #define SDHCI_INT_DATA_END BIT(1)
117 #define SDHCI_INT_DMA_END BIT(3)
118 #define SDHCI_INT_SPACE_AVAIL BIT(4)
119 #define SDHCI_INT_DATA_AVAIL BIT(5)
120 #define SDHCI_INT_CARD_INSERT BIT(6)
121 #define SDHCI_INT_CARD_REMOVE BIT(7)
122 #define SDHCI_INT_CARD_INT BIT(8)
123 #define SDHCI_INT_ERROR BIT(15)
124 #define SDHCI_INT_TIMEOUT BIT(16)
125 #define SDHCI_INT_CRC BIT(17)
126 #define SDHCI_INT_END_BIT BIT(18)
127 #define SDHCI_INT_INDEX BIT(19)
128 #define SDHCI_INT_DATA_TIMEOUT BIT(20)
129 #define SDHCI_INT_DATA_CRC BIT(21)
130 #define SDHCI_INT_DATA_END_BIT BIT(22)
131 #define SDHCI_INT_BUS_POWER BIT(23)
132 #define SDHCI_INT_ACMD12ERR BIT(24)
133 #define SDHCI_INT_ADMA_ERROR BIT(25)
134
135 #define SDHCI_INT_NORMAL_MASK 0x00007FFF
136 #define SDHCI_INT_ERROR_MASK 0xFFFF8000
137
138 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
139 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
140 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
141 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
142 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
143 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
144 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
145
146 #define SDHCI_ACMD12_ERR 0x3C
147
148 #define SDHCI_HOST_CONTROL2 0x3E
149 #define SDHCI_CTRL_UHS_MASK 0x0007
150 #define SDHCI_CTRL_UHS_SDR12 0x0000
151 #define SDHCI_CTRL_UHS_SDR25 0x0001
152 #define SDHCI_CTRL_UHS_SDR50 0x0002
153 #define SDHCI_CTRL_UHS_SDR104 0x0003
154 #define SDHCI_CTRL_UHS_DDR50 0x0004
155 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
156 #define SDHCI_CTRL_VDD_180 0x0008
157 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
158 #define SDHCI_CTRL_DRV_TYPE_B 0x0000
159 #define SDHCI_CTRL_DRV_TYPE_A 0x0010
160 #define SDHCI_CTRL_DRV_TYPE_C 0x0020
161 #define SDHCI_CTRL_DRV_TYPE_D 0x0030
162 #define SDHCI_CTRL_EXEC_TUNING 0x0040
163 #define SDHCI_CTRL_TUNED_CLK 0x0080
164 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
165
166 #define SDHCI_CAPABILITIES 0x40
167 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
168 #define SDHCI_TIMEOUT_CLK_SHIFT 0
169 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
170 #define SDHCI_CLOCK_BASE_MASK 0x00003F00
171 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
172 #define SDHCI_CLOCK_BASE_SHIFT 8
173 #define SDHCI_MAX_BLOCK_MASK 0x00030000
174 #define SDHCI_MAX_BLOCK_SHIFT 16
175 #define SDHCI_CAN_DO_8BIT BIT(18)
176 #define SDHCI_CAN_DO_ADMA2 BIT(19)
177 #define SDHCI_CAN_DO_ADMA1 BIT(20)
178 #define SDHCI_CAN_DO_HISPD BIT(21)
179 #define SDHCI_CAN_DO_SDMA BIT(22)
180 #define SDHCI_CAN_VDD_330 BIT(24)
181 #define SDHCI_CAN_VDD_300 BIT(25)
182 #define SDHCI_CAN_VDD_180 BIT(26)
183 #define SDHCI_CAN_64BIT BIT(28)
184
185 #define SDHCI_CAPABILITIES_1 0x44
186 #define SDHCI_SUPPORT_SDR50 0x00000001
187 #define SDHCI_SUPPORT_SDR104 0x00000002
188 #define SDHCI_SUPPORT_DDR50 0x00000004
189 #define SDHCI_USE_SDR50_TUNING 0x00002000
190
191 #define SDHCI_CLOCK_MUL_MASK 0x00FF0000
192 #define SDHCI_CLOCK_MUL_SHIFT 16
193
194 #define SDHCI_MAX_CURRENT 0x48
195
196 /* 4C-4F reserved for more max current */
197
198 #define SDHCI_SET_ACMD12_ERROR 0x50
199 #define SDHCI_SET_INT_ERROR 0x52
200
201 #define SDHCI_ADMA_ERROR 0x54
202
203 /* 55-57 reserved */
204
205 #define SDHCI_ADMA_ADDRESS 0x58
206 #define SDHCI_ADMA_ADDRESS_HI 0x5c
207
208 /* 60-FB reserved */
209
210 #define SDHCI_SLOT_INT_STATUS 0xFC
211
212 #define SDHCI_HOST_VERSION 0xFE
213 #define SDHCI_VENDOR_VER_MASK 0xFF00
214 #define SDHCI_VENDOR_VER_SHIFT 8
215 #define SDHCI_SPEC_VER_MASK 0x00FF
216 #define SDHCI_SPEC_VER_SHIFT 0
217 #define SDHCI_SPEC_100 0
218 #define SDHCI_SPEC_200 1
219 #define SDHCI_SPEC_300 2
220
221 #define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)
222
223 /*
224 * End of controller registers.
225 */
226
227 #define SDHCI_MAX_DIV_SPEC_200 256
228 #define SDHCI_MAX_DIV_SPEC_300 2046
229
230 /*
231 * quirks
232 */
233 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0)
234 #define SDHCI_QUIRK_REG32_RW (1 << 1)
235 #define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
236 #define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
237 #define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
238 /*
239 * SDHCI_QUIRK_BROKEN_HISPD_MODE
240 * the hardware cannot operate correctly in high-speed mode,
241 * this quirk forces the sdhci host-controller to non high-speed mode
242 */
243 #define SDHCI_QUIRK_BROKEN_HISPD_MODE BIT(5)
244 #define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
245 #define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
246
247 /* to make gcc happy */
248 struct sdhci_host;
249
250 /*
251 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
252 */
253 #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
254 #define SDHCI_DEFAULT_BOUNDARY_ARG (7)
255 struct sdhci_ops {
256 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
257 u32 (*read_l)(struct sdhci_host *host, int reg);
258 u16 (*read_w)(struct sdhci_host *host, int reg);
259 u8 (*read_b)(struct sdhci_host *host, int reg);
260 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
261 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
262 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
263 #endif
264 int (*get_cd)(struct sdhci_host *host);
265 void (*set_control_reg)(struct sdhci_host *host);
266 int (*set_ios_post)(struct sdhci_host *host);
267 void (*set_clock)(struct sdhci_host *host, u32 div);
268 int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
269 void (*set_delay)(struct sdhci_host *host);
270 int (*deferred_probe)(struct sdhci_host *host);
271 };
272
273 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
274 #define ADMA_MAX_LEN 65532
275 #ifdef CONFIG_DMA_ADDR_T_64BIT
276 #define ADMA_DESC_LEN 16
277 #else
278 #define ADMA_DESC_LEN 8
279 #endif
280 #define ADMA_TABLE_NO_ENTRIES (CONFIG_SYS_MMC_MAX_BLK_COUNT * \
281 MMC_MAX_BLOCK_LEN) / ADMA_MAX_LEN
282
283 #define ADMA_TABLE_SZ (ADMA_TABLE_NO_ENTRIES * ADMA_DESC_LEN)
284
285 /* Decriptor table defines */
286 #define ADMA_DESC_ATTR_VALID BIT(0)
287 #define ADMA_DESC_ATTR_END BIT(1)
288 #define ADMA_DESC_ATTR_INT BIT(2)
289 #define ADMA_DESC_ATTR_ACT1 BIT(4)
290 #define ADMA_DESC_ATTR_ACT2 BIT(5)
291
292 #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
293 #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
294
295 struct sdhci_adma_desc {
296 u8 attr;
297 u8 reserved;
298 u16 len;
299 u32 addr_lo;
300 #ifdef CONFIG_DMA_ADDR_T_64BIT
301 u32 addr_hi;
302 #endif
303 } __packed;
304 #endif
305 struct sdhci_host {
306 const char *name;
307 void *ioaddr;
308 unsigned int quirks;
309 unsigned int host_caps;
310 unsigned int version;
311 unsigned int max_clk; /* Maximum Base Clock frequency */
312 unsigned int clk_mul; /* Clock Multiplier value */
313 unsigned int clock;
314 struct mmc *mmc;
315 const struct sdhci_ops *ops;
316 int index;
317
318 int bus_width;
319 struct gpio_desc pwr_gpio; /* Power GPIO */
320 struct gpio_desc cd_gpio; /* Card Detect GPIO */
321
322 uint voltages;
323
324 struct mmc_config cfg;
325 void *align_buffer;
326 bool force_align_buffer;
327 dma_addr_t start_addr;
328 int flags;
329 #define USE_SDMA (0x1 << 0)
330 #define USE_ADMA (0x1 << 1)
331 #define USE_ADMA64 (0x1 << 2)
332 #define USE_DMA (USE_SDMA | USE_ADMA | USE_ADMA64)
333 dma_addr_t adma_addr;
334 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
335 struct sdhci_adma_desc *adma_desc_table;
336 uint desc_slot;
337 #endif
338 };
339
340 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
341
342 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
343 {
344 if (unlikely(host->ops->write_l))
345 host->ops->write_l(host, val, reg);
346 else
347 writel(val, host->ioaddr + reg);
348 }
349
350 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
351 {
352 if (unlikely(host->ops->write_w))
353 host->ops->write_w(host, val, reg);
354 else
355 writew(val, host->ioaddr + reg);
356 }
357
358 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
359 {
360 if (unlikely(host->ops->write_b))
361 host->ops->write_b(host, val, reg);
362 else
363 writeb(val, host->ioaddr + reg);
364 }
365
366 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
367 {
368 if (unlikely(host->ops->read_l))
369 return host->ops->read_l(host, reg);
370 else
371 return readl(host->ioaddr + reg);
372 }
373
374 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
375 {
376 if (unlikely(host->ops->read_w))
377 return host->ops->read_w(host, reg);
378 else
379 return readw(host->ioaddr + reg);
380 }
381
382 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
383 {
384 if (unlikely(host->ops->read_b))
385 return host->ops->read_b(host, reg);
386 else
387 return readb(host->ioaddr + reg);
388 }
389
390 #else
391
392 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
393 {
394 writel(val, host->ioaddr + reg);
395 }
396
397 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
398 {
399 writew(val, host->ioaddr + reg);
400 }
401
402 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
403 {
404 writeb(val, host->ioaddr + reg);
405 }
406 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
407 {
408 return readl(host->ioaddr + reg);
409 }
410
411 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
412 {
413 return readw(host->ioaddr + reg);
414 }
415
416 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
417 {
418 return readb(host->ioaddr + reg);
419 }
420 #endif
421
422 #ifdef CONFIG_BLK
423 /**
424 * sdhci_setup_cfg() - Set up the configuration for DWMMC
425 *
426 * This is used to set up an SDHCI device when you are using CONFIG_BLK.
427 *
428 * This should be called from your MMC driver's probe() method once you have
429 * the information required.
430 *
431 * Generally your driver will have a platform data structure which holds both
432 * the configuration (struct mmc_config) and the MMC device info (struct mmc).
433 * For example:
434 *
435 * struct msm_sdhc_plat {
436 * struct mmc_config cfg;
437 * struct mmc mmc;
438 * };
439 *
440 * ...
441 *
442 * Inside U_BOOT_DRIVER():
443 * .platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat),
444 *
445 * To access platform data:
446 * struct msm_sdhc_plat *plat = dev_get_platdata(dev);
447 *
448 * See msm_sdhci.c for an example.
449 *
450 * @cfg: Configuration structure to fill in (generally &plat->mmc)
451 * @host: SDHCI host structure
452 * @f_max: Maximum supported clock frequency in HZ (0 for default)
453 * @f_min: Minimum supported clock frequency in HZ (0 for default)
454 */
455 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
456 u32 f_max, u32 f_min);
457
458 /**
459 * sdhci_bind() - Set up a new MMC block device
460 *
461 * This is used to set up an SDHCI block device when you are using CONFIG_BLK.
462 * It should be called from your driver's bind() method.
463 *
464 * See msm_sdhci.c for an example.
465 *
466 * @dev: Device to set up
467 * @mmc: Pointer to mmc structure (normally &plat->mmc)
468 * @cfg: Empty configuration structure (generally &plat->cfg). This is
469 * normally all zeroes at this point. The only purpose of passing
470 * this in is to set mmc->cfg to it.
471 * @return 0 if OK, -ve if the block device could not be created
472 */
473 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
474 #else
475
476 /**
477 * add_sdhci() - Add a new SDHCI interface
478 *
479 * This is used when you are not using CONFIG_BLK. Convert your driver over!
480 *
481 * @host: SDHCI host structure
482 * @f_max: Maximum supported clock frequency in HZ (0 for default)
483 * @f_min: Minimum supported clock frequency in HZ (0 for default)
484 * @return 0 if OK, -ve on error
485 */
486 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
487 #endif /* !CONFIG_BLK */
488
489 void sdhci_set_uhs_timing(struct sdhci_host *host);
490 #ifdef CONFIG_DM_MMC
491 /* Export the operations to drivers */
492 int sdhci_probe(struct udevice *dev);
493 int sdhci_set_clock(struct mmc *mmc, unsigned int clock);
494 extern const struct dm_mmc_ops sdhci_ops;
495 #else
496 #endif
497
498 #endif /* __SDHCI_HW_H */
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