include/sdhci.h

   1 /*
   2  * Copyright 2011, Marvell Semiconductor Inc.
   3  * Lei Wen <leiwen@marvell.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  * Back ported to the 8xx platform (from the 8260 platform) by
  24  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
  25  */
  26 #ifndef __SDHCI_HW_H
  27 #define __SDHCI_HW_H
  28
  29 #include <asm/io.h>
  30 #include <mmc.h>
  31
  32 /*
  33  * Controller registers
  34  */
  35
  36 #define SDHCI_DMA_ADDRESS       0x00
  37
  38 #define SDHCI_BLOCK_SIZE        0x04
  39 #define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
  40
  41 #define SDHCI_BLOCK_COUNT       0x06
  42
  43 #define SDHCI_ARGUMENT          0x08
  44
  45 #define SDHCI_TRANSFER_MODE     0x0C
  46 #define  SDHCI_TRNS_DMA         0x01
  47 #define  SDHCI_TRNS_BLK_CNT_EN  0x02
  48 #define  SDHCI_TRNS_ACMD12      0x04
  49 #define  SDHCI_TRNS_READ        0x10
  50 #define  SDHCI_TRNS_MULTI       0x20
  51
  52 #define SDHCI_COMMAND           0x0E
  53 #define  SDHCI_CMD_RESP_MASK    0x03
  54 #define  SDHCI_CMD_CRC          0x08
  55 #define  SDHCI_CMD_INDEX        0x10
  56 #define  SDHCI_CMD_DATA         0x20
  57 #define  SDHCI_CMD_ABORTCMD     0xC0
  58
  59 #define  SDHCI_CMD_RESP_NONE    0x00
  60 #define  SDHCI_CMD_RESP_LONG    0x01
  61 #define  SDHCI_CMD_RESP_SHORT   0x02
  62 #define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
  63
  64 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
  65 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
  66
  67 #define SDHCI_RESPONSE          0x10
  68
  69 #define SDHCI_BUFFER            0x20
  70
  71 #define SDHCI_PRESENT_STATE     0x24
  72 #define  SDHCI_CMD_INHIBIT      0x00000001
  73 #define  SDHCI_DATA_INHIBIT     0x00000002
  74 #define  SDHCI_DOING_WRITE      0x00000100
  75 #define  SDHCI_DOING_READ       0x00000200
  76 #define  SDHCI_SPACE_AVAILABLE  0x00000400
  77 #define  SDHCI_DATA_AVAILABLE   0x00000800
  78 #define  SDHCI_CARD_PRESENT     0x00010000
  79 #define  SDHCI_WRITE_PROTECT    0x00080000
  80
  81 #define SDHCI_HOST_CONTROL      0x28
  82 #define  SDHCI_CTRL_LED         0x01
  83 #define  SDHCI_CTRL_4BITBUS     0x02
  84 #define  SDHCI_CTRL_HISPD       0x04
  85 #define  SDHCI_CTRL_DMA_MASK    0x18
  86 #define   SDHCI_CTRL_SDMA       0x00
  87 #define   SDHCI_CTRL_ADMA1      0x08
  88 #define   SDHCI_CTRL_ADMA32     0x10
  89 #define   SDHCI_CTRL_ADMA64     0x18
  90 #define   SDHCI_CTRL_8BITBUS    0x20
  91
  92 #define SDHCI_POWER_CONTROL     0x29
  93 #define  SDHCI_POWER_ON         0x01
  94 #define  SDHCI_POWER_180        0x0A
  95 #define  SDHCI_POWER_300        0x0C
  96 #define  SDHCI_POWER_330        0x0E
  97
  98 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
  99
 100 #define SDHCI_WAKE_UP_CONTROL   0x2B
 101 #define  SDHCI_WAKE_ON_INT      0x01
 102 #define  SDHCI_WAKE_ON_INSERT   0x02
 103 #define  SDHCI_WAKE_ON_REMOVE   0x04
 104
 105 #define SDHCI_CLOCK_CONTROL     0x2C
 106 #define  SDHCI_DIVIDER_SHIFT    8
 107 #define  SDHCI_DIVIDER_HI_SHIFT 6
 108 #define  SDHCI_DIV_MASK 0xFF
 109 #define  SDHCI_DIV_MASK_LEN     8
 110 #define  SDHCI_DIV_HI_MASK      0x300
 111 #define  SDHCI_CLOCK_CARD_EN    0x0004
 112 #define  SDHCI_CLOCK_INT_STABLE 0x0002
 113 #define  SDHCI_CLOCK_INT_EN     0x0001
 114
 115 #define SDHCI_TIMEOUT_CONTROL   0x2E
 116
 117 #define SDHCI_SOFTWARE_RESET    0x2F
 118 #define  SDHCI_RESET_ALL        0x01
 119 #define  SDHCI_RESET_CMD        0x02
 120 #define  SDHCI_RESET_DATA       0x04
 121
 122 #define SDHCI_INT_STATUS        0x30
 123 #define SDHCI_INT_ENABLE        0x34
 124 #define SDHCI_SIGNAL_ENABLE     0x38
 125 #define  SDHCI_INT_RESPONSE     0x00000001
 126 #define  SDHCI_INT_DATA_END     0x00000002
 127 #define  SDHCI_INT_DMA_END      0x00000008
 128 #define  SDHCI_INT_SPACE_AVAIL  0x00000010
 129 #define  SDHCI_INT_DATA_AVAIL   0x00000020
 130 #define  SDHCI_INT_CARD_INSERT  0x00000040
 131 #define  SDHCI_INT_CARD_REMOVE  0x00000080
 132 #define  SDHCI_INT_CARD_INT     0x00000100
 133 #define  SDHCI_INT_ERROR        0x00008000
 134 #define  SDHCI_INT_TIMEOUT      0x00010000
 135 #define  SDHCI_INT_CRC          0x00020000
 136 #define  SDHCI_INT_END_BIT      0x00040000
 137 #define  SDHCI_INT_INDEX        0x00080000
 138 #define  SDHCI_INT_DATA_TIMEOUT 0x00100000
 139 #define  SDHCI_INT_DATA_CRC     0x00200000
 140 #define  SDHCI_INT_DATA_END_BIT 0x00400000
 141 #define  SDHCI_INT_BUS_POWER    0x00800000
 142 #define  SDHCI_INT_ACMD12ERR    0x01000000
 143 #define  SDHCI_INT_ADMA_ERROR   0x02000000
 144
 145 #define  SDHCI_INT_NORMAL_MASK  0x00007FFF
 146 #define  SDHCI_INT_ERROR_MASK   0xFFFF8000
 147
 148 #define  SDHCI_INT_CMD_MASK     (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
 149                 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
 150 #define  SDHCI_INT_DATA_MASK    (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
 151                 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
 152                 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
 153                 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
 154 #define SDHCI_INT_ALL_MASK      ((unsigned int)-1)
 155
 156 #define SDHCI_ACMD12_ERR        0x3C
 157
 158 /* 3E-3F reserved */
 159
 160 #define SDHCI_CAPABILITIES      0x40
 161 #define  SDHCI_TIMEOUT_CLK_MASK 0x0000003F
 162 #define  SDHCI_TIMEOUT_CLK_SHIFT 0
 163 #define  SDHCI_TIMEOUT_CLK_UNIT 0x00000080
 164 #define  SDHCI_CLOCK_BASE_MASK  0x00003F00
 165 #define  SDHCI_CLOCK_V3_BASE_MASK       0x0000FF00
 166 #define  SDHCI_CLOCK_BASE_SHIFT 8
 167 #define  SDHCI_MAX_BLOCK_MASK   0x00030000
 168 #define  SDHCI_MAX_BLOCK_SHIFT  16
 169 #define  SDHCI_CAN_DO_8BIT      0x00040000
 170 #define  SDHCI_CAN_DO_ADMA2     0x00080000
 171 #define  SDHCI_CAN_DO_ADMA1     0x00100000
 172 #define  SDHCI_CAN_DO_HISPD     0x00200000
 173 #define  SDHCI_CAN_DO_SDMA      0x00400000
 174 #define  SDHCI_CAN_VDD_330      0x01000000
 175 #define  SDHCI_CAN_VDD_300      0x02000000
 176 #define  SDHCI_CAN_VDD_180      0x04000000
 177 #define  SDHCI_CAN_64BIT        0x10000000
 178
 179 #define SDHCI_CAPABILITIES_1    0x44
 180
 181 #define SDHCI_MAX_CURRENT       0x48
 182
 183 /* 4C-4F reserved for more max current */
 184
 185 #define SDHCI_SET_ACMD12_ERROR  0x50
 186 #define SDHCI_SET_INT_ERROR     0x52
 187
 188 #define SDHCI_ADMA_ERROR        0x54
 189
 190 /* 55-57 reserved */
 191
 192 #define SDHCI_ADMA_ADDRESS      0x58
 193
 194 /* 60-FB reserved */
 195
 196 #define SDHCI_SLOT_INT_STATUS   0xFC
 197
 198 #define SDHCI_HOST_VERSION      0xFE
 199 #define  SDHCI_VENDOR_VER_MASK  0xFF00
 200 #define  SDHCI_VENDOR_VER_SHIFT 8
 201 #define  SDHCI_SPEC_VER_MASK    0x00FF
 202 #define  SDHCI_SPEC_VER_SHIFT   0
 203 #define   SDHCI_SPEC_100        0
 204 #define   SDHCI_SPEC_200        1
 205 #define   SDHCI_SPEC_300        2
 206
 207 /*
 208  * End of controller registers.
 209  */
 210
 211 #define SDHCI_MAX_DIV_SPEC_200  256
 212 #define SDHCI_MAX_DIV_SPEC_300  2046
 213
 214 /*
 215  * quirks
 216  */
 217 #define SDHCI_QUIRK_32BIT_DMA_ADDR      (1 << 0)
 218 #define SDHCI_QUIRK_REG32_RW            (1 << 1)
 219
 220 /* to make gcc happy */
 221 struct sdhci_host;
 222
 223 /*
 224  * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
 225  */
 226 #define SDHCI_DEFAULT_BOUNDARY_SIZE     (512 * 1024)
 227 #define SDHCI_DEFAULT_BOUNDARY_ARG      (7)
 228 struct sdhci_ops {
 229 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 230         u32             (*read_l)(struct sdhci_host *host, int reg);
 231         u16             (*read_w)(struct sdhci_host *host, int reg);
 232         u8              (*read_b)(struct sdhci_host *host, int reg);
 233         void            (*write_l)(struct sdhci_host *host, u32 val, int reg);
 234         void            (*write_w)(struct sdhci_host *host, u16 val, int reg);
 235         void            (*write_b)(struct sdhci_host *host, u8 val, int reg);
 236 #endif
 237 };
 238
 239 struct sdhci_host {
 240         char *name;
 241         void *ioaddr;
 242         unsigned int quirks;
 243         unsigned int version;
 244         unsigned int clock;
 245         struct mmc *mmc;
 246         const struct sdhci_ops *ops;
 247 };
 248
 249 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 250
 251 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 252 {
 253         if (unlikely(host->ops->write_l))
 254                 host->ops->write_l(host, val, reg);
 255         else
 256                 writel(val, host->ioaddr + reg);
 257 }
 258
 259 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 260 {
 261         if (unlikely(host->ops->write_w))
 262                 host->ops->write_w(host, val, reg);
 263         else
 264                 writew(val, host->ioaddr + reg);
 265 }
 266
 267 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 268 {
 269         if (unlikely(host->ops->write_b))
 270                 host->ops->write_b(host, val, reg);
 271         else
 272                 writeb(val, host->ioaddr + reg);
 273 }
 274
 275 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
 276 {
 277         if (unlikely(host->ops->read_l))
 278                 return host->ops->read_l(host, reg);
 279         else
 280                 return readl(host->ioaddr + reg);
 281 }
 282
 283 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
 284 {
 285         if (unlikely(host->ops->read_w))
 286                 return host->ops->read_w(host, reg);
 287         else
 288                 return readw(host->ioaddr + reg);
 289 }
 290
 291 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
 292 {
 293         if (unlikely(host->ops->read_b))
 294                 return host->ops->read_b(host, reg);
 295         else
 296                 return readb(host->ioaddr + reg);
 297 }
 298
 299 #else
 300
 301 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 302 {
 303         writel(val, host->ioaddr + reg);
 304 }
 305
 306 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 307 {
 308         writew(val, host->ioaddr + reg);
 309 }
 310
 311 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 312 {
 313         writeb(val, host->ioaddr + reg);
 314 }
 315 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
 316 {
 317         return readl(host->ioaddr + reg);
 318 }
 319
 320 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
 321 {
 322         return readw(host->ioaddr + reg);
 323 }
 324
 325 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
 326 {
 327         return readb(host->ioaddr + reg);
 328 }
 329 #endif
 330
 331 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk);
 332 #endif /* __SDHCI_HW_H */