include/sdhci.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011, Marvell Semiconductor Inc.
   4  * Lei Wen <leiwen@marvell.com>
   5  *
   6  * Back ported to the 8xx platform (from the 8260 platform) by
   7  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
   8  */
   9 #ifndef __SDHCI_HW_H
  10 #define __SDHCI_HW_H
  11
  12 #include <asm/io.h>
  13 #include <mmc.h>
  14 #include <asm/gpio.h>
  15
  16 /*
  17  * Controller registers
  18  */
  19
  20 #define SDHCI_DMA_ADDRESS       0x00
  21
  22 #define SDHCI_BLOCK_SIZE        0x04
  23 #define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
  24
  25 #define SDHCI_BLOCK_COUNT       0x06
  26
  27 #define SDHCI_ARGUMENT          0x08
  28
  29 #define SDHCI_TRANSFER_MODE     0x0C
  30 #define  SDHCI_TRNS_DMA         BIT(0)
  31 #define  SDHCI_TRNS_BLK_CNT_EN  BIT(1)
  32 #define  SDHCI_TRNS_ACMD12      BIT(2)
  33 #define  SDHCI_TRNS_READ        BIT(4)
  34 #define  SDHCI_TRNS_MULTI       BIT(5)
  35
  36 #define SDHCI_COMMAND           0x0E
  37 #define  SDHCI_CMD_RESP_MASK    0x03
  38 #define  SDHCI_CMD_CRC          0x08
  39 #define  SDHCI_CMD_INDEX        0x10
  40 #define  SDHCI_CMD_DATA         0x20
  41 #define  SDHCI_CMD_ABORTCMD     0xC0
  42
  43 #define  SDHCI_CMD_RESP_NONE    0x00
  44 #define  SDHCI_CMD_RESP_LONG    0x01
  45 #define  SDHCI_CMD_RESP_SHORT   0x02
  46 #define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
  47
  48 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
  49 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
  50
  51 #define SDHCI_RESPONSE          0x10
  52
  53 #define SDHCI_BUFFER            0x20
  54
  55 #define SDHCI_PRESENT_STATE     0x24
  56 #define  SDHCI_CMD_INHIBIT      BIT(0)
  57 #define  SDHCI_DATA_INHIBIT     BIT(1)
  58 #define  SDHCI_DOING_WRITE      BIT(8)
  59 #define  SDHCI_DOING_READ       BIT(9)
  60 #define  SDHCI_SPACE_AVAILABLE  BIT(10)
  61 #define  SDHCI_DATA_AVAILABLE   BIT(11)
  62 #define  SDHCI_CARD_PRESENT     BIT(16)
  63 #define  SDHCI_CARD_STATE_STABLE        BIT(17)
  64 #define  SDHCI_CARD_DETECT_PIN_LEVEL    BIT(18)
  65 #define  SDHCI_WRITE_PROTECT    BIT(19)
  66
  67 #define SDHCI_HOST_CONTROL      0x28
  68 #define  SDHCI_CTRL_LED         BIT(0)
  69 #define  SDHCI_CTRL_4BITBUS     BIT(1)
  70 #define  SDHCI_CTRL_HISPD       BIT(2)
  71 #define  SDHCI_CTRL_DMA_MASK    0x18
  72 #define   SDHCI_CTRL_SDMA       0x00
  73 #define   SDHCI_CTRL_ADMA1      0x08
  74 #define   SDHCI_CTRL_ADMA32     0x10
  75 #define   SDHCI_CTRL_ADMA64     0x18
  76 #define  SDHCI_CTRL_8BITBUS     BIT(5)
  77 #define  SDHCI_CTRL_CD_TEST_INS BIT(6)
  78 #define  SDHCI_CTRL_CD_TEST     BIT(7)
  79
  80 #define SDHCI_POWER_CONTROL     0x29
  81 #define  SDHCI_POWER_ON         0x01
  82 #define  SDHCI_POWER_180        0x0A
  83 #define  SDHCI_POWER_300        0x0C
  84 #define  SDHCI_POWER_330        0x0E
  85
  86 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
  87
  88 #define SDHCI_WAKE_UP_CONTROL   0x2B
  89 #define  SDHCI_WAKE_ON_INT      BIT(0)
  90 #define  SDHCI_WAKE_ON_INSERT   BIT(1)
  91 #define  SDHCI_WAKE_ON_REMOVE   BIT(2)
  92
  93 #define SDHCI_CLOCK_CONTROL     0x2C
  94 #define  SDHCI_DIVIDER_SHIFT    8
  95 #define  SDHCI_DIVIDER_HI_SHIFT 6
  96 #define  SDHCI_DIV_MASK 0xFF
  97 #define  SDHCI_DIV_MASK_LEN     8
  98 #define  SDHCI_DIV_HI_MASK      0x300
  99 #define  SDHCI_PROG_CLOCK_MODE  BIT(5)
 100 #define  SDHCI_CLOCK_CARD_EN    BIT(2)
 101 #define  SDHCI_CLOCK_INT_STABLE BIT(1)
 102 #define  SDHCI_CLOCK_INT_EN     BIT(0)
 103
 104 #define SDHCI_TIMEOUT_CONTROL   0x2E
 105
 106 #define SDHCI_SOFTWARE_RESET    0x2F
 107 #define  SDHCI_RESET_ALL        0x01
 108 #define  SDHCI_RESET_CMD        0x02
 109 #define  SDHCI_RESET_DATA       0x04
 110
 111 #define SDHCI_INT_STATUS        0x30
 112 #define SDHCI_INT_ENABLE        0x34
 113 #define SDHCI_SIGNAL_ENABLE     0x38
 114 #define  SDHCI_INT_RESPONSE     BIT(0)
 115 #define  SDHCI_INT_DATA_END     BIT(1)
 116 #define  SDHCI_INT_DMA_END      BIT(3)
 117 #define  SDHCI_INT_SPACE_AVAIL  BIT(4)
 118 #define  SDHCI_INT_DATA_AVAIL   BIT(5)
 119 #define  SDHCI_INT_CARD_INSERT  BIT(6)
 120 #define  SDHCI_INT_CARD_REMOVE  BIT(7)
 121 #define  SDHCI_INT_CARD_INT     BIT(8)
 122 #define  SDHCI_INT_ERROR        BIT(15)
 123 #define  SDHCI_INT_TIMEOUT      BIT(16)
 124 #define  SDHCI_INT_CRC          BIT(17)
 125 #define  SDHCI_INT_END_BIT      BIT(18)
 126 #define  SDHCI_INT_INDEX        BIT(19)
 127 #define  SDHCI_INT_DATA_TIMEOUT BIT(20)
 128 #define  SDHCI_INT_DATA_CRC     BIT(21)
 129 #define  SDHCI_INT_DATA_END_BIT BIT(22)
 130 #define  SDHCI_INT_BUS_POWER    BIT(23)
 131 #define  SDHCI_INT_ACMD12ERR    BIT(24)
 132 #define  SDHCI_INT_ADMA_ERROR   BIT(25)
 133
 134 #define  SDHCI_INT_NORMAL_MASK  0x00007FFF
 135 #define  SDHCI_INT_ERROR_MASK   0xFFFF8000
 136
 137 #define  SDHCI_INT_CMD_MASK     (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
 138                 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
 139 #define  SDHCI_INT_DATA_MASK    (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
 140                 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
 141                 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
 142                 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
 143 #define SDHCI_INT_ALL_MASK      ((unsigned int)-1)
 144
 145 #define SDHCI_ACMD12_ERR        0x3C
 146
 147 /* 3E-3F reserved */
 148
 149 #define SDHCI_CAPABILITIES      0x40
 150 #define  SDHCI_TIMEOUT_CLK_MASK 0x0000003F
 151 #define  SDHCI_TIMEOUT_CLK_SHIFT 0
 152 #define  SDHCI_TIMEOUT_CLK_UNIT 0x00000080
 153 #define  SDHCI_CLOCK_BASE_MASK  0x00003F00
 154 #define  SDHCI_CLOCK_V3_BASE_MASK       0x0000FF00
 155 #define  SDHCI_CLOCK_BASE_SHIFT 8
 156 #define  SDHCI_MAX_BLOCK_MASK   0x00030000
 157 #define  SDHCI_MAX_BLOCK_SHIFT  16
 158 #define  SDHCI_CAN_DO_8BIT      BIT(18)
 159 #define  SDHCI_CAN_DO_ADMA2     BIT(19)
 160 #define  SDHCI_CAN_DO_ADMA1     BIT(20)
 161 #define  SDHCI_CAN_DO_HISPD     BIT(21)
 162 #define  SDHCI_CAN_DO_SDMA      BIT(22)
 163 #define  SDHCI_CAN_VDD_330      BIT(24)
 164 #define  SDHCI_CAN_VDD_300      BIT(25)
 165 #define  SDHCI_CAN_VDD_180      BIT(26)
 166 #define  SDHCI_CAN_64BIT        BIT(28)
 167
 168 #define SDHCI_CAPABILITIES_1    0x44
 169 #define  SDHCI_SUPPORT_SDR50    0x00000001
 170 #define  SDHCI_SUPPORT_SDR104   0x00000002
 171 #define  SDHCI_SUPPORT_DDR50    0x00000004
 172 #define  SDHCI_USE_SDR50_TUNING 0x00002000
 173
 174 #define  SDHCI_CLOCK_MUL_MASK   0x00FF0000
 175 #define  SDHCI_CLOCK_MUL_SHIFT  16
 176
 177 #define SDHCI_MAX_CURRENT       0x48
 178
 179 /* 4C-4F reserved for more max current */
 180
 181 #define SDHCI_SET_ACMD12_ERROR  0x50
 182 #define SDHCI_SET_INT_ERROR     0x52
 183
 184 #define SDHCI_ADMA_ERROR        0x54
 185
 186 /* 55-57 reserved */
 187
 188 #define SDHCI_ADMA_ADDRESS      0x58
 189
 190 /* 60-FB reserved */
 191
 192 #define SDHCI_SLOT_INT_STATUS   0xFC
 193
 194 #define SDHCI_HOST_VERSION      0xFE
 195 #define  SDHCI_VENDOR_VER_MASK  0xFF00
 196 #define  SDHCI_VENDOR_VER_SHIFT 8
 197 #define  SDHCI_SPEC_VER_MASK    0x00FF
 198 #define  SDHCI_SPEC_VER_SHIFT   0
 199 #define   SDHCI_SPEC_100        0
 200 #define   SDHCI_SPEC_200        1
 201 #define   SDHCI_SPEC_300        2
 202
 203 #define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)
 204
 205 /*
 206  * End of controller registers.
 207  */
 208
 209 #define SDHCI_MAX_DIV_SPEC_200  256
 210 #define SDHCI_MAX_DIV_SPEC_300  2046
 211
 212 /*
 213  * quirks
 214  */
 215 #define SDHCI_QUIRK_32BIT_DMA_ADDR      (1 << 0)
 216 #define SDHCI_QUIRK_REG32_RW            (1 << 1)
 217 #define SDHCI_QUIRK_BROKEN_R1B          (1 << 2)
 218 #define SDHCI_QUIRK_NO_HISPD_BIT        (1 << 3)
 219 #define SDHCI_QUIRK_BROKEN_VOLTAGE      (1 << 4)
 220 /*
 221  * SDHCI_QUIRK_BROKEN_HISPD_MODE
 222  * the hardware cannot operate correctly in high-speed mode,
 223  * this quirk forces the sdhci host-controller to non high-speed mode
 224  */
 225 #define SDHCI_QUIRK_BROKEN_HISPD_MODE   BIT(5)
 226 #define SDHCI_QUIRK_WAIT_SEND_CMD       (1 << 6)
 227 #define SDHCI_QUIRK_USE_WIDE8           (1 << 8)
 228 #define SDHCI_QUIRK_NO_1_8_V            (1 << 9)
 229
 230 /* to make gcc happy */
 231 struct sdhci_host;
 232
 233 /*
 234  * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
 235  */
 236 #define SDHCI_DEFAULT_BOUNDARY_SIZE     (512 * 1024)
 237 #define SDHCI_DEFAULT_BOUNDARY_ARG      (7)
 238 struct sdhci_ops {
 239 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 240         u32     (*read_l)(struct sdhci_host *host, int reg);
 241         u16     (*read_w)(struct sdhci_host *host, int reg);
 242         u8      (*read_b)(struct sdhci_host *host, int reg);
 243         void    (*write_l)(struct sdhci_host *host, u32 val, int reg);
 244         void    (*write_w)(struct sdhci_host *host, u16 val, int reg);
 245         void    (*write_b)(struct sdhci_host *host, u8 val, int reg);
 246 #endif
 247         int     (*get_cd)(struct sdhci_host *host);
 248         void    (*set_control_reg)(struct sdhci_host *host);
 249         void    (*set_ios_post)(struct sdhci_host *host);
 250         void    (*set_clock)(struct sdhci_host *host, u32 div);
 251         int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
 252         void (*set_delay)(struct sdhci_host *host);
 253 };
 254
 255 struct sdhci_host {
 256         const char *name;
 257         void *ioaddr;
 258         unsigned int quirks;
 259         unsigned int host_caps;
 260         unsigned int version;
 261         unsigned int max_clk;   /* Maximum Base Clock frequency */
 262         unsigned int clk_mul;   /* Clock Multiplier value */
 263         unsigned int clock;
 264         struct mmc *mmc;
 265         const struct sdhci_ops *ops;
 266         int index;
 267
 268         int bus_width;
 269         struct gpio_desc pwr_gpio;      /* Power GPIO */
 270         struct gpio_desc cd_gpio;               /* Card Detect GPIO */
 271
 272         uint    voltages;
 273
 274         struct mmc_config cfg;
 275 };
 276
 277 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 278
 279 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 280 {
 281         if (unlikely(host->ops->write_l))
 282                 host->ops->write_l(host, val, reg);
 283         else
 284                 writel(val, host->ioaddr + reg);
 285 }
 286
 287 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 288 {
 289         if (unlikely(host->ops->write_w))
 290                 host->ops->write_w(host, val, reg);
 291         else
 292                 writew(val, host->ioaddr + reg);
 293 }
 294
 295 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 296 {
 297         if (unlikely(host->ops->write_b))
 298                 host->ops->write_b(host, val, reg);
 299         else
 300                 writeb(val, host->ioaddr + reg);
 301 }
 302
 303 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
 304 {
 305         if (unlikely(host->ops->read_l))
 306                 return host->ops->read_l(host, reg);
 307         else
 308                 return readl(host->ioaddr + reg);
 309 }
 310
 311 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
 312 {
 313         if (unlikely(host->ops->read_w))
 314                 return host->ops->read_w(host, reg);
 315         else
 316                 return readw(host->ioaddr + reg);
 317 }
 318
 319 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
 320 {
 321         if (unlikely(host->ops->read_b))
 322                 return host->ops->read_b(host, reg);
 323         else
 324                 return readb(host->ioaddr + reg);
 325 }
 326
 327 #else
 328
 329 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 330 {
 331         writel(val, host->ioaddr + reg);
 332 }
 333
 334 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 335 {
 336         writew(val, host->ioaddr + reg);
 337 }
 338
 339 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 340 {
 341         writeb(val, host->ioaddr + reg);
 342 }
 343 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
 344 {
 345         return readl(host->ioaddr + reg);
 346 }
 347
 348 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
 349 {
 350         return readw(host->ioaddr + reg);
 351 }
 352
 353 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
 354 {
 355         return readb(host->ioaddr + reg);
 356 }
 357 #endif
 358
 359 #ifdef CONFIG_BLK
 360 /**
 361  * sdhci_setup_cfg() - Set up the configuration for DWMMC
 362  *
 363  * This is used to set up an SDHCI device when you are using CONFIG_BLK.
 364  *
 365  * This should be called from your MMC driver's probe() method once you have
 366  * the information required.
 367  *
 368  * Generally your driver will have a platform data structure which holds both
 369  * the configuration (struct mmc_config) and the MMC device info (struct mmc).
 370  * For example:
 371  *
 372  * struct msm_sdhc_plat {
 373  *      struct mmc_config cfg;
 374  *      struct mmc mmc;
 375  * };
 376  *
 377  * ...
 378  *
 379  * Inside U_BOOT_DRIVER():
 380  *      .platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat),
 381  *
 382  * To access platform data:
 383  *      struct msm_sdhc_plat *plat = dev_get_platdata(dev);
 384  *
 385  * See msm_sdhci.c for an example.
 386  *
 387  * @cfg:        Configuration structure to fill in (generally &plat->mmc)
 388  * @host:       SDHCI host structure
 389  * @f_max:      Maximum supported clock frequency in HZ (0 for default)
 390  * @f_min:      Minimum supported clock frequency in HZ (0 for default)
 391  */
 392 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
 393                     u32 f_max, u32 f_min);
 394
 395 /**
 396  * sdhci_bind() - Set up a new MMC block device
 397  *
 398  * This is used to set up an SDHCI block device when you are using CONFIG_BLK.
 399  * It should be called from your driver's bind() method.
 400  *
 401  * See msm_sdhci.c for an example.
 402  *
 403  * @dev:        Device to set up
 404  * @mmc:        Pointer to mmc structure (normally &plat->mmc)
 405  * @cfg:        Empty configuration structure (generally &plat->cfg). This is
 406  *              normally all zeroes at this point. The only purpose of passing
 407  *              this in is to set mmc->cfg to it.
 408  * @return 0 if OK, -ve if the block device could not be created
 409  */
 410 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
 411 #else
 412
 413 /**
 414  * add_sdhci() - Add a new SDHCI interface
 415  *
 416  * This is used when you are not using CONFIG_BLK. Convert your driver over!
 417  *
 418  * @host:       SDHCI host structure
 419  * @f_max:      Maximum supported clock frequency in HZ (0 for default)
 420  * @f_min:      Minimum supported clock frequency in HZ (0 for default)
 421  * @return 0 if OK, -ve on error
 422  */
 423 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
 424 #endif /* !CONFIG_BLK */
 425
 426 #ifdef CONFIG_DM_MMC
 427 /* Export the operations to drivers */
 428 int sdhci_probe(struct udevice *dev);
 429 extern const struct dm_mmc_ops sdhci_ops;
 430 #else
 431 #endif
 432
 433 #endif /* __SDHCI_HW_H */