include/soc/arc/mcip.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * ARConnect IP Support (Multi core enabler: Cross core IPI, RTC ...)
   4  *
   5  * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
   6  */
   7
   8 #ifndef __SOC_ARC_MCIP_H
   9 #define __SOC_ARC_MCIP_H
  10
  11 #include <soc/arc/aux.h>
  12
  13 #define ARC_REG_MCIP_BCR        0x0d0
  14 #define ARC_REG_MCIP_IDU_BCR    0x0D5
  15 #define ARC_REG_GFRC_BUILD      0x0D6
  16 #define ARC_REG_MCIP_CMD        0x600
  17 #define ARC_REG_MCIP_WDATA      0x601
  18 #define ARC_REG_MCIP_READBACK   0x602
  19
  20 struct mcip_cmd {
  21 #ifdef CONFIG_CPU_BIG_ENDIAN
  22         unsigned int pad:8, param:16, cmd:8;
  23 #else
  24         unsigned int cmd:8, param:16, pad:8;
  25 #endif
  26
  27 #define CMD_INTRPT_GENERATE_IRQ         0x01
  28 #define CMD_INTRPT_GENERATE_ACK         0x02
  29 #define CMD_INTRPT_READ_STATUS          0x03
  30 #define CMD_INTRPT_CHECK_SOURCE         0x04
  31
  32 /* Semaphore Commands */
  33 #define CMD_SEMA_CLAIM_AND_READ         0x11
  34 #define CMD_SEMA_RELEASE                0x12
  35
  36 #define CMD_DEBUG_SET_MASK              0x34
  37 #define CMD_DEBUG_READ_MASK             0x35
  38 #define CMD_DEBUG_SET_SELECT            0x36
  39 #define CMD_DEBUG_READ_SELECT           0x37
  40
  41 #define CMD_GFRC_READ_LO                0x42
  42 #define CMD_GFRC_READ_HI                0x43
  43 #define CMD_GFRC_SET_CORE               0x47
  44 #define CMD_GFRC_READ_CORE              0x48
  45
  46 #define CMD_IDU_ENABLE                  0x71
  47 #define CMD_IDU_DISABLE                 0x72
  48 #define CMD_IDU_SET_MODE                0x74
  49 #define CMD_IDU_SET_DEST                0x76
  50 #define CMD_IDU_SET_MASK                0x7C
  51
  52 #define IDU_M_TRIG_LEVEL                0x0
  53 #define IDU_M_TRIG_EDGE                 0x1
  54
  55 #define IDU_M_DISTRI_RR                 0x0
  56 #define IDU_M_DISTRI_DEST               0x2
  57 };
  58
  59 struct mcip_bcr {
  60 #ifdef CONFIG_CPU_BIG_ENDIAN
  61                 unsigned int pad4:6, pw_dom:1, pad3:1,
  62                              idu:1, pad2:1, num_cores:6,
  63                              pad:1,  gfrc:1, dbg:1, pw:1,
  64                              msg:1, sem:1, ipi:1, slv:1,
  65                              ver:8;
  66 #else
  67                 unsigned int ver:8,
  68                              slv:1, ipi:1, sem:1, msg:1,
  69                              pw:1, dbg:1, gfrc:1, pad:1,
  70                              num_cores:6, pad2:1, idu:1,
  71                              pad3:1, pw_dom:1, pad4:6;
  72 #endif
  73 };
  74
  75 struct mcip_idu_bcr {
  76 #ifdef CONFIG_CPU_BIG_ENDIAN
  77         unsigned int pad:21, cirqnum:3, ver:8;
  78 #else
  79         unsigned int ver:8, cirqnum:3, pad:21;
  80 #endif
  81 };
  82
  83
  84 /*
  85  * Build register for IDU contains not an actual number of supported common
  86  * interrupts but an exponent of 2 which must be multiplied by 4 to
  87  * get a number of supported common interrupts.
  88  */
  89 #define mcip_idu_bcr_to_nr_irqs(bcr) (4 * (1 << (bcr).cirqnum))
  90
  91 /*
  92  * MCIP programming model
  93  *
  94  * - Simple commands write {cmd:8,param:16} to MCIP_CMD aux reg
  95  *   (param could be irq, common_irq, core_id ...)
  96  * - More involved commands setup MCIP_WDATA with cmd specific data
  97  *   before invoking the simple command
  98  */
  99 static inline void __mcip_cmd(unsigned int cmd, unsigned int param)
 100 {
 101         struct mcip_cmd buf;
 102
 103         buf.pad = 0;
 104         buf.cmd = cmd;
 105         buf.param = param;
 106
 107         WRITE_AUX(ARC_REG_MCIP_CMD, buf);
 108 }
 109
 110 /*
 111  * Setup additional data for a cmd
 112  * Callers need to lock to ensure atomicity
 113  */
 114 static inline void __mcip_cmd_data(unsigned int cmd, unsigned int param,
 115                                    unsigned int data)
 116 {
 117         write_aux_reg(ARC_REG_MCIP_WDATA, data);
 118
 119         __mcip_cmd(cmd, param);
 120 }
 121
 122 #endif