include/sound/sof/topology.h

   1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
   2 /*
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * Copyright(c) 2018 Intel Corporation. All rights reserved.
   7  */
   8
   9 #ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__
  10 #define __INCLUDE_SOUND_SOF_TOPOLOGY_H__
  11
  12 #include <sound/sof/header.h>
  13
  14 /*
  15  * Component
  16  */
  17
  18 /* types of component */
  19 enum sof_comp_type {
  20         SOF_COMP_NONE = 0,
  21         SOF_COMP_HOST,
  22         SOF_COMP_DAI,
  23         SOF_COMP_SG_HOST,       /**< scatter gather variant */
  24         SOF_COMP_SG_DAI,        /**< scatter gather variant */
  25         SOF_COMP_VOLUME,
  26         SOF_COMP_MIXER,
  27         SOF_COMP_MUX,
  28         SOF_COMP_SRC,
  29         SOF_COMP_SPLITTER,
  30         SOF_COMP_TONE,
  31         SOF_COMP_SWITCH,
  32         SOF_COMP_BUFFER,
  33         SOF_COMP_EQ_IIR,
  34         SOF_COMP_EQ_FIR,
  35         SOF_COMP_KEYWORD_DETECT,
  36         SOF_COMP_KPB,                   /* A key phrase buffer component */
  37         SOF_COMP_SELECTOR,              /**< channel selector component */
  38         /* keep FILEREAD/FILEWRITE as the last ones */
  39         SOF_COMP_FILEREAD = 10000,      /**< host test based file IO */
  40         SOF_COMP_FILEWRITE = 10001,     /**< host test based file IO */
  41 };
  42
  43 /* XRUN action for component */
  44 #define SOF_XRUN_STOP           1       /**< stop stream */
  45 #define SOF_XRUN_UNDER_ZERO     2       /**< send 0s to sink */
  46 #define SOF_XRUN_OVER_NULL      4       /**< send data to NULL */
  47
  48 /* create new generic component - SOF_IPC_TPLG_COMP_NEW */
  49 struct sof_ipc_comp {
  50         struct sof_ipc_cmd_hdr hdr;
  51         uint32_t id;
  52         enum sof_comp_type type;
  53         uint32_t pipeline_id;
  54
  55         /* reserved for future use */
  56         uint32_t reserved[2];
  57 } __packed;
  58
  59 /*
  60  * Component Buffers
  61  */
  62
  63 /*
  64  * SOF memory capabilities, add new ones at the end
  65  */
  66 #define SOF_MEM_CAPS_RAM                        (1 << 0)
  67 #define SOF_MEM_CAPS_ROM                        (1 << 1)
  68 #define SOF_MEM_CAPS_EXT                        (1 << 2) /**< external */
  69 #define SOF_MEM_CAPS_LP                 (1 << 3) /**< low power */
  70 #define SOF_MEM_CAPS_HP                 (1 << 4) /**< high performance */
  71 #define SOF_MEM_CAPS_DMA                        (1 << 5) /**< DMA'able */
  72 #define SOF_MEM_CAPS_CACHE                      (1 << 6) /**< cacheable */
  73 #define SOF_MEM_CAPS_EXEC                       (1 << 7) /**< executable */
  74
  75 /* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */
  76 struct sof_ipc_buffer {
  77         struct sof_ipc_comp comp;
  78         uint32_t size;          /**< buffer size in bytes */
  79         uint32_t caps;          /**< SOF_MEM_CAPS_ */
  80 } __packed;
  81
  82 /* generic component config data - must always be after struct sof_ipc_comp */
  83 struct sof_ipc_comp_config {
  84         struct sof_ipc_cmd_hdr hdr;
  85         uint32_t periods_sink;  /**< 0 means variable */
  86         uint32_t periods_source;        /**< 0 means variable */
  87         uint32_t reserved1;     /**< reserved */
  88         uint32_t frame_fmt;             /**< SOF_IPC_FRAME_ */
  89         uint32_t xrun_action;
  90
  91         /* reserved for future use */
  92         uint32_t reserved[2];
  93 } __packed;
  94
  95 /* generic host component */
  96 struct sof_ipc_comp_host {
  97         struct sof_ipc_comp comp;
  98         struct sof_ipc_comp_config config;
  99         uint32_t direction;     /**< SOF_IPC_STREAM_ */
 100         uint32_t no_irq;        /**< don't send periodic IRQ to host/DSP */
 101         uint32_t dmac_config; /**< DMA engine specific */
 102 }  __packed;
 103
 104 /* generic DAI component */
 105 struct sof_ipc_comp_dai {
 106         struct sof_ipc_comp comp;
 107         struct sof_ipc_comp_config config;
 108         uint32_t direction;     /**< SOF_IPC_STREAM_ */
 109         uint32_t dai_index;     /**< index of this type dai */
 110         uint32_t type;          /**< DAI type - SOF_DAI_ */
 111         uint32_t reserved;      /**< reserved */
 112 }  __packed;
 113
 114 /* generic mixer component */
 115 struct sof_ipc_comp_mixer {
 116         struct sof_ipc_comp comp;
 117         struct sof_ipc_comp_config config;
 118 }  __packed;
 119
 120 /* volume ramping types */
 121 enum sof_volume_ramp {
 122         SOF_VOLUME_LINEAR       = 0,
 123         SOF_VOLUME_LOG,
 124         SOF_VOLUME_LINEAR_ZC,
 125         SOF_VOLUME_LOG_ZC,
 126 };
 127
 128 /* generic volume component */
 129 struct sof_ipc_comp_volume {
 130         struct sof_ipc_comp comp;
 131         struct sof_ipc_comp_config config;
 132         uint32_t channels;
 133         uint32_t min_value;
 134         uint32_t max_value;
 135         uint32_t ramp;          /**< SOF_VOLUME_ */
 136         uint32_t initial_ramp;  /**< ramp space in ms */
 137 }  __packed;
 138
 139 /* generic SRC component */
 140 struct sof_ipc_comp_src {
 141         struct sof_ipc_comp comp;
 142         struct sof_ipc_comp_config config;
 143         /* either source or sink rate must be non zero */
 144         uint32_t source_rate;   /**< source rate or 0 for variable */
 145         uint32_t sink_rate;     /**< sink rate or 0 for variable */
 146         uint32_t rate_mask;     /**< SOF_RATE_ supported rates */
 147 } __packed;
 148
 149 /* generic MUX component */
 150 struct sof_ipc_comp_mux {
 151         struct sof_ipc_comp comp;
 152         struct sof_ipc_comp_config config;
 153 } __packed;
 154
 155 /* generic tone generator component */
 156 struct sof_ipc_comp_tone {
 157         struct sof_ipc_comp comp;
 158         struct sof_ipc_comp_config config;
 159         int32_t sample_rate;
 160         int32_t frequency;
 161         int32_t amplitude;
 162         int32_t freq_mult;
 163         int32_t ampl_mult;
 164         int32_t length;
 165         int32_t period;
 166         int32_t repeats;
 167         int32_t ramp_step;
 168 } __packed;
 169
 170 /** \brief Types of processing components */
 171 enum sof_ipc_process_type {
 172         SOF_PROCESS_NONE = 0,           /**< None */
 173         SOF_PROCESS_EQFIR,              /**< Intel FIR */
 174         SOF_PROCESS_EQIIR,              /**< Intel IIR */
 175         SOF_PROCESS_KEYWORD_DETECT,     /**< Keyword Detection */
 176         SOF_PROCESS_KPB,                /**< KeyPhrase Buffer Manager */
 177         SOF_PROCESS_CHAN_SELECTOR,      /**< Channel Selector */
 178 };
 179
 180 /* generic "effect", "codec" or proprietary processing component */
 181 struct sof_ipc_comp_process {
 182         struct sof_ipc_comp comp;
 183         struct sof_ipc_comp_config config;
 184         uint32_t size;  /**< size of bespoke data section in bytes */
 185         uint32_t type;  /**< sof_ipc_process_type */
 186
 187         /* reserved for future use */
 188         uint32_t reserved[7];
 189
 190         unsigned char data[0];
 191 } __packed;
 192
 193 /* frees components, buffers and pipelines
 194  * SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_FREE, SOF_IPC_TPLG_BUFFER_FREE
 195  */
 196 struct sof_ipc_free {
 197         struct sof_ipc_cmd_hdr hdr;
 198         uint32_t id;
 199 } __packed;
 200
 201 struct sof_ipc_comp_reply {
 202         struct sof_ipc_reply rhdr;
 203         uint32_t id;
 204         uint32_t offset;
 205 } __packed;
 206
 207 /*
 208  * Pipeline
 209  */
 210
 211 /** \brief Types of pipeline scheduling time domains */
 212 enum sof_ipc_pipe_sched_time_domain {
 213         SOF_TIME_DOMAIN_DMA = 0,        /**< DMA interrupt */
 214         SOF_TIME_DOMAIN_TIMER,          /**< Timer interrupt */
 215 };
 216
 217 /* new pipeline - SOF_IPC_TPLG_PIPE_NEW */
 218 struct sof_ipc_pipe_new {
 219         struct sof_ipc_cmd_hdr hdr;
 220         uint32_t comp_id;       /**< component id for pipeline */
 221         uint32_t pipeline_id;   /**< pipeline id */
 222         uint32_t sched_id;      /**< Scheduling component id */
 223         uint32_t core;          /**< core we run on */
 224         uint32_t period;        /**< execution period in us*/
 225         uint32_t priority;      /**< priority level 0 (low) to 10 (max) */
 226         uint32_t period_mips;   /**< worst case instruction count per period */
 227         uint32_t frames_per_sched;/**< output frames of pipeline, 0 is variable */
 228         uint32_t xrun_limit_usecs; /**< report xruns greater than limit */
 229         uint32_t time_domain;   /**< scheduling time domain */
 230 }  __packed;
 231
 232 /* pipeline construction complete - SOF_IPC_TPLG_PIPE_COMPLETE */
 233 struct sof_ipc_pipe_ready {
 234         struct sof_ipc_cmd_hdr hdr;
 235         uint32_t comp_id;
 236 }  __packed;
 237
 238 struct sof_ipc_pipe_free {
 239         struct sof_ipc_cmd_hdr hdr;
 240         uint32_t comp_id;
 241 }  __packed;
 242
 243 /* connect two components in pipeline - SOF_IPC_TPLG_COMP_CONNECT */
 244 struct sof_ipc_pipe_comp_connect {
 245         struct sof_ipc_cmd_hdr hdr;
 246         uint32_t source_id;
 247         uint32_t sink_id;
 248 }  __packed;
 249
 250 /* external events */
 251 enum sof_event_types {
 252         SOF_EVENT_NONE = 0,
 253         SOF_KEYWORD_DETECT_DAPM_EVENT,
 254 };
 255
 256 #endif