include/spd.h

   1 /*
   2  * Copyright (C) 2003 Arabella Software Ltd.
   3  * Yuli Barcohen <yuli@arabellasw.com>
   4  *
   5  * Serial Presence Detect (SPD) EEPROM format according to the
   6  * Intel's PC SDRAM Serial Presence Detect (SPD) Specification,
   7  * revision 1.2B, November 1999
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of the
  12  * License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  */
  23
  24 #ifndef _SPD_H_
  25 #define _SPD_H_
  26
  27 typedef struct spd_eeprom_s {
  28    unsigned char info_size;   /* # of bytes written into serial memory           */
  29    unsigned char chip_size;   /* Total # of bytes of SPD memory device           */
  30    unsigned char mem_type;    /* Fundamental memory type (FPM, EDO, SDRAM...)    */
  31    unsigned char nrow_addr;   /* # of Row Addresses on this assembly             */
  32    unsigned char ncol_addr;   /* # of Column Addresses on this assembly          */
  33    unsigned char nrows;       /* # of Module Rows on this assembly               */
  34    unsigned char dataw_lsb;   /* Data Width of this assembly                     */
  35    unsigned char dataw_msb;   /* ... Data Width continuation                     */
  36    unsigned char voltage;     /* Voltage interface standard of this assembly     */
  37    unsigned char clk_cycle;   /* SDRAM Cycle time at CL=X                        */
  38    unsigned char clk_access;  /* SDRAM Access from Clock at CL=X                 */
  39    unsigned char config;      /* DIMM Configuration type (non-parity, ECC)       */
  40    unsigned char refresh;     /* Refresh Rate/Type                               */
  41    unsigned char primw;       /* Primary SDRAM Width                             */
  42    unsigned char ecw;         /* Error Checking SDRAM width                      */
  43    unsigned char min_delay;   /* Min Clock Delay for Back to Back Random Address */
  44    unsigned char burstl;      /* Burst Lengths Supported                         */
  45    unsigned char nbanks;      /* # of Banks on Each SDRAM Device                 */
  46    unsigned char cas_lat;     /* CAS# Latencies Supported                        */
  47    unsigned char cs_lat;      /* CS# Latency                                     */
  48    unsigned char write_lat;   /* Write Latency (also called Write Recovery time) */
  49    unsigned char mod_attr;    /* SDRAM Module Attributes                         */
  50    unsigned char dev_attr;    /* SDRAM Device Attributes                         */
  51    unsigned char clk_cycle2;  /* Min SDRAM Cycle time at CL=X-1                  */
  52    unsigned char clk_access2; /* SDRAM Access from Clock at CL=X-1               */
  53    unsigned char clk_cycle3;  /* Min SDRAM Cycle time at CL=X-2                  */
  54    unsigned char clk_access3; /* Max SDRAM Access from Clock at CL=X-2           */
  55    unsigned char trp;         /* Min Row Precharge Time (tRP)                    */
  56    unsigned char trrd;        /* Min Row Active to Row Active (tRRD)             */
  57    unsigned char trcd;        /* Min RAS to CAS Delay (tRCD)                     */
  58    unsigned char tras;        /* Minimum RAS Pulse Width (tRAS)                  */
  59    unsigned char row_dens;    /* Density of each row on module                   */
  60    unsigned char ca_setup;    /* Command and Address signal input setup time     */
  61    unsigned char ca_hold;     /* Command and Address signal input hold time      */
  62    unsigned char data_setup;  /* Data signal input setup time                    */
  63    unsigned char data_hold;   /* Data signal input hold time                     */
  64    unsigned char sset[26];    /* Superset Information (may be used in future)    */
  65    unsigned char spd_rev;     /* SPD Data Revision Code                          */
  66    unsigned char cksum;       /* Checksum for bytes 0-62                         */
  67    unsigned char mid[8];      /* Manufacturer's JEDEC ID code per JEP-108E       */
  68    unsigned char mloc;        /* Manufacturing Location                          */
  69    unsigned char mpart[18];   /* Manufacturer's Part Number                      */
  70    unsigned char rev[2];      /* Revision Code                                   */
  71    unsigned char mdate[2];    /* Manufacturing Date                              */
  72    unsigned char sernum[4];   /* Assembly Serial Number                          */
  73    unsigned char mspec[27];   /* Manufacturer Specific Data                      */
  74    unsigned char freq;        /* Intel specification frequency                   */
  75    unsigned char intel_cas;   /* Intel Specification CAS# Latency support        */
  76 } spd_eeprom_t;
  77
  78 #endif /* _SPD_H_ */