]>
git.ipfire.org Git - thirdparty/u-boot.git/blob - include/stm32_rcc.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) STMicroelectronics SA 2017
4 * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
14 #define AHB_PSC_16 0xB
15 #define AHB_PSC_64 0xC
16 #define AHB_PSC_128 0xD
17 #define AHB_PSC_256 0xE
18 #define AHB_PSC_512 0xF
24 #define APB_PSC_16 0x7
36 struct stm32_clk_info
{
37 struct pll_psc sys_pll_psc
;
54 struct stm32_rcc_clk
{
59 struct stm32_rcc_regs
{
60 u32 cr
; /* RCC clock control */
61 u32 pllcfgr
; /* RCC PLL configuration */
62 u32 cfgr
; /* RCC clock configuration */
63 u32 cir
; /* RCC clock interrupt */
64 u32 ahb1rstr
; /* RCC AHB1 peripheral reset */
65 u32 ahb2rstr
; /* RCC AHB2 peripheral reset */
66 u32 ahb3rstr
; /* RCC AHB3 peripheral reset */
68 u32 apb1rstr
; /* RCC APB1 peripheral reset */
69 u32 apb2rstr
; /* RCC APB2 peripheral reset */
71 u32 ahb1enr
; /* RCC AHB1 peripheral clock enable */
72 u32 ahb2enr
; /* RCC AHB2 peripheral clock enable */
73 u32 ahb3enr
; /* RCC AHB3 peripheral clock enable */
75 u32 apb1enr
; /* RCC APB1 peripheral clock enable */
76 u32 apb2enr
; /* RCC APB2 peripheral clock enable */
78 u32 ahb1lpenr
; /* RCC AHB1 periph clk enable in low pwr mode */
79 u32 ahb2lpenr
; /* RCC AHB2 periph clk enable in low pwr mode */
80 u32 ahb3lpenr
; /* RCC AHB3 periph clk enable in low pwr mode */
82 u32 apb1lpenr
; /* RCC APB1 periph clk enable in low pwr mode */
83 u32 apb2lpenr
; /* RCC APB2 periph clk enable in low pwr mode */
85 u32 bdcr
; /* RCC Backup domain control */
86 u32 csr
; /* RCC clock control & status */
88 u32 sscgr
; /* RCC spread spectrum clock generation */
89 u32 plli2scfgr
; /* RCC PLLI2S configuration */
90 /* below registers are only available on STM32F46x and STM32F7 SoCs*/
91 u32 pllsaicfgr
; /* PLLSAI configuration */
92 u32 dckcfgr
; /* dedicated clocks configuration register */
93 /* Below registers are only available on STM32F7 SoCs */
94 u32 dckcfgr2
; /* dedicated clocks configuration register */
97 #endif /* __STM32_RCC_H_ */