4 * Driver for the Motorola Triple Speed Ethernet Controller
6 * This software may be used and distributed according to the
7 * terms of the GNU Public License, Version 2, incorporated
10 * Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc.
11 * (C) Copyright 2003, Motorola, Inc.
12 * maintained by Xianghua Xiao (x.xiao@motorola.com)
25 #define TSEC_SIZE 0x40000
26 #define TSEC_MDIO_OFFSET 0x40000
28 #define TSEC_SIZE 0x01000
29 #define TSEC_MDIO_OFFSET 0x01000
32 #define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
34 #define TSEC_GET_REGS(num, offset) \
35 (struct tsec __iomem *)\
36 (TSEC_BASE_ADDR + (((num) - 1) * (offset)))
38 #define TSEC_GET_REGS_BASE(num) \
39 TSEC_GET_REGS((num), TSEC_SIZE)
41 #define TSEC_GET_MDIO_REGS(num, offset) \
42 (struct tsec_mii_mng __iomem *)\
43 (CONFIG_SYS_MDIO_BASE_ADDR + ((num) - 1) * (offset))
45 #define TSEC_GET_MDIO_REGS_BASE(num) \
46 TSEC_GET_MDIO_REGS((num), TSEC_MDIO_OFFSET)
48 #define DEFAULT_MII_NAME "FSL_MDIO"
50 #define STD_TSEC_INFO(num) \
52 .regs = TSEC_GET_REGS_BASE(num), \
53 .miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num), \
54 .devname = CONFIG_TSEC##num##_NAME, \
55 .phyaddr = TSEC##num##_PHY_ADDR, \
56 .flags = TSEC##num##_FLAGS, \
57 .mii_devname = DEFAULT_MII_NAME \
60 #define SET_STD_TSEC_INFO(x, num) \
62 x.regs = TSEC_GET_REGS_BASE(num); \
63 x.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num); \
64 x.devname = CONFIG_TSEC##num##_NAME; \
65 x.phyaddr = TSEC##num##_PHY_ADDR; \
66 x.flags = TSEC##num##_FLAGS;\
67 x.mii_devname = DEFAULT_MII_NAME;\
70 #define MAC_ADDR_LEN 6
72 /* #define TSEC_TIMEOUT 1000000 */
73 #define TSEC_TIMEOUT 1000
74 #define TOUT_LOOP 1000000
76 /* TBI register addresses */
80 #define TBI_ANLPBPA 0x05
82 #define TBI_TBICON 0x11
84 /* TBI MDIO register bit fields*/
85 #define TBICON_CLK_SELECT 0x0020
86 #define TBIANA_ASYMMETRIC_PAUSE 0x0100
87 #define TBIANA_SYMMETRIC_PAUSE 0x0080
88 #define TBIANA_HALF_DUPLEX 0x0040
89 #define TBIANA_FULL_DUPLEX 0x0020
90 #define TBICR_PHY_RESET 0x8000
91 #define TBICR_ANEG_ENABLE 0x1000
92 #define TBICR_RESTART_ANEG 0x0200
93 #define TBICR_FULL_DUPLEX 0x0100
94 #define TBICR_SPEED1_SET 0x0040
97 /* MAC register bits */
98 #define MACCFG1_SOFT_RESET 0x80000000
99 #define MACCFG1_RESET_RX_MC 0x00080000
100 #define MACCFG1_RESET_TX_MC 0x00040000
101 #define MACCFG1_RESET_RX_FUN 0x00020000
102 #define MACCFG1_RESET_TX_FUN 0x00010000
103 #define MACCFG1_LOOPBACK 0x00000100
104 #define MACCFG1_RX_FLOW 0x00000020
105 #define MACCFG1_TX_FLOW 0x00000010
106 #define MACCFG1_SYNCD_RX_EN 0x00000008
107 #define MACCFG1_RX_EN 0x00000004
108 #define MACCFG1_SYNCD_TX_EN 0x00000002
109 #define MACCFG1_TX_EN 0x00000001
111 #define MACCFG2_INIT_SETTINGS 0x00007205
112 #define MACCFG2_FULL_DUPLEX 0x00000001
113 #define MACCFG2_IF 0x00000300
114 #define MACCFG2_GMII 0x00000200
115 #define MACCFG2_MII 0x00000100
117 #define ECNTRL_INIT_SETTINGS 0x00001000
118 #define ECNTRL_TBI_MODE 0x00000020
119 #define ECNTRL_REDUCED_MODE 0x00000010
120 #define ECNTRL_R100 0x00000008
121 #define ECNTRL_REDUCED_MII_MODE 0x00000004
122 #define ECNTRL_SGMII_MODE 0x00000002
124 #ifndef CONFIG_SYS_TBIPA_VALUE
125 #define CONFIG_SYS_TBIPA_VALUE 0x1f
128 #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
130 #define MINFLR_INIT_SETTINGS 0x00000040
132 #ifdef CONFIG_LS102XA
133 #define DMACTRL_INIT_SETTINGS 0x00000003
135 #define DMACTRL_INIT_SETTINGS 0x000000c3
137 #define DMACTRL_GRS 0x00000010
138 #define DMACTRL_GTS 0x00000008
139 #define DMACTRL_LE 0x00008000
141 #define TSTAT_CLEAR_THALT 0x80000000
142 #define RSTAT_CLEAR_RHALT 0x00800000
145 #define IEVENT_INIT_CLEAR 0xffffffff
146 #define IEVENT_BABR 0x80000000
147 #define IEVENT_RXC 0x40000000
148 #define IEVENT_BSY 0x20000000
149 #define IEVENT_EBERR 0x10000000
150 #define IEVENT_MSRO 0x04000000
151 #define IEVENT_GTSC 0x02000000
152 #define IEVENT_BABT 0x01000000
153 #define IEVENT_TXC 0x00800000
154 #define IEVENT_TXE 0x00400000
155 #define IEVENT_TXB 0x00200000
156 #define IEVENT_TXF 0x00100000
157 #define IEVENT_IE 0x00080000
158 #define IEVENT_LC 0x00040000
159 #define IEVENT_CRL 0x00020000
160 #define IEVENT_XFUN 0x00010000
161 #define IEVENT_RXB0 0x00008000
162 #define IEVENT_GRSC 0x00000100
163 #define IEVENT_RXF0 0x00000080
165 #define IMASK_INIT_CLEAR 0x00000000
166 #define IMASK_TXEEN 0x00400000
167 #define IMASK_TXBEN 0x00200000
168 #define IMASK_TXFEN 0x00100000
169 #define IMASK_RXFEN0 0x00000080
172 /* Default Attribute fields */
173 #define ATTR_INIT_SETTINGS 0x000000c0
174 #define ATTRELI_INIT_SETTINGS 0x00000000
177 /* TxBD status field bits */
178 #define TXBD_READY 0x8000
179 #define TXBD_PADCRC 0x4000
180 #define TXBD_WRAP 0x2000
181 #define TXBD_INTERRUPT 0x1000
182 #define TXBD_LAST 0x0800
183 #define TXBD_CRC 0x0400
184 #define TXBD_DEF 0x0200
185 #define TXBD_HUGEFRAME 0x0080
186 #define TXBD_LATECOLLISION 0x0080
187 #define TXBD_RETRYLIMIT 0x0040
188 #define TXBD_RETRYCOUNTMASK 0x003c
189 #define TXBD_UNDERRUN 0x0002
190 #define TXBD_STATS 0x03ff
192 /* RxBD status field bits */
193 #define RXBD_EMPTY 0x8000
194 #define RXBD_RO1 0x4000
195 #define RXBD_WRAP 0x2000
196 #define RXBD_INTERRUPT 0x1000
197 #define RXBD_LAST 0x0800
198 #define RXBD_FIRST 0x0400
199 #define RXBD_MISS 0x0100
200 #define RXBD_BROADCAST 0x0080
201 #define RXBD_MULTICAST 0x0040
202 #define RXBD_LARGE 0x0020
203 #define RXBD_NONOCTET 0x0010
204 #define RXBD_SHORT 0x0008
205 #define RXBD_CRCERR 0x0004
206 #define RXBD_OVERRUN 0x0002
207 #define RXBD_TRUNCATED 0x0001
208 #define RXBD_STATS 0x003f
211 uint16_t status
; /* Status Fields */
212 uint16_t length
; /* Buffer length */
213 uint32_t bufptr
; /* Buffer Pointer */
217 uint16_t status
; /* Status Fields */
218 uint16_t length
; /* Buffer Length */
219 uint32_t bufptr
; /* Buffer Pointer */
222 struct tsec_rmon_mib
{
223 /* Transmit and Receive Counters */
224 u32 tr64
; /* Tx/Rx 64-byte Frame Counter */
225 u32 tr127
; /* Tx/Rx 65-127 byte Frame Counter */
226 u32 tr255
; /* Tx/Rx 128-255 byte Frame Counter */
227 u32 tr511
; /* Tx/Rx 256-511 byte Frame Counter */
228 u32 tr1k
; /* Tx/Rx 512-1023 byte Frame Counter */
229 u32 trmax
; /* Tx/Rx 1024-1518 byte Frame Counter */
230 u32 trmgv
; /* Tx/Rx 1519-1522 byte Good VLAN Frame */
231 /* Receive Counters */
232 u32 rbyt
; /* Receive Byte Counter */
233 u32 rpkt
; /* Receive Packet Counter */
234 u32 rfcs
; /* Receive FCS Error Counter */
235 u32 rmca
; /* Receive Multicast Packet (Counter) */
236 u32 rbca
; /* Receive Broadcast Packet */
237 u32 rxcf
; /* Receive Control Frame Packet */
238 u32 rxpf
; /* Receive Pause Frame Packet */
239 u32 rxuo
; /* Receive Unknown OP Code */
240 u32 raln
; /* Receive Alignment Error */
241 u32 rflr
; /* Receive Frame Length Error */
242 u32 rcde
; /* Receive Code Error */
243 u32 rcse
; /* Receive Carrier Sense Error */
244 u32 rund
; /* Receive Undersize Packet */
245 u32 rovr
; /* Receive Oversize Packet */
246 u32 rfrg
; /* Receive Fragments */
247 u32 rjbr
; /* Receive Jabber */
248 u32 rdrp
; /* Receive Drop */
249 /* Transmit Counters */
250 u32 tbyt
; /* Transmit Byte Counter */
251 u32 tpkt
; /* Transmit Packet */
252 u32 tmca
; /* Transmit Multicast Packet */
253 u32 tbca
; /* Transmit Broadcast Packet */
254 u32 txpf
; /* Transmit Pause Control Frame */
255 u32 tdfr
; /* Transmit Deferral Packet */
256 u32 tedf
; /* Transmit Excessive Deferral Packet */
257 u32 tscl
; /* Transmit Single Collision Packet */
259 u32 tmcl
; /* Transmit Multiple Collision Packet */
260 u32 tlcl
; /* Transmit Late Collision Packet */
261 u32 txcl
; /* Transmit Excessive Collision Packet */
262 u32 tncl
; /* Transmit Total Collision */
266 u32 tdrp
; /* Transmit Drop Frame */
267 u32 tjbr
; /* Transmit Jabber Frame */
268 u32 tfcs
; /* Transmit FCS Error */
269 u32 txcf
; /* Transmit Control Frame */
270 u32 tovr
; /* Transmit Oversize Frame */
271 u32 tund
; /* Transmit Undersize Frame */
272 u32 tfrg
; /* Transmit Fragments Frame */
273 /* General Registers */
274 u32 car1
; /* Carry Register One */
275 u32 car2
; /* Carry Register Two */
276 u32 cam1
; /* Carry Register One Mask */
277 u32 cam2
; /* Carry Register Two Mask */
280 struct tsec_hash_regs
{
281 u32 iaddr0
; /* Individual Address Register 0 */
282 u32 iaddr1
; /* Individual Address Register 1 */
283 u32 iaddr2
; /* Individual Address Register 2 */
284 u32 iaddr3
; /* Individual Address Register 3 */
285 u32 iaddr4
; /* Individual Address Register 4 */
286 u32 iaddr5
; /* Individual Address Register 5 */
287 u32 iaddr6
; /* Individual Address Register 6 */
288 u32 iaddr7
; /* Individual Address Register 7 */
290 u32 gaddr0
; /* Group Address Register 0 */
291 u32 gaddr1
; /* Group Address Register 1 */
292 u32 gaddr2
; /* Group Address Register 2 */
293 u32 gaddr3
; /* Group Address Register 3 */
294 u32 gaddr4
; /* Group Address Register 4 */
295 u32 gaddr5
; /* Group Address Register 5 */
296 u32 gaddr6
; /* Group Address Register 6 */
297 u32 gaddr7
; /* Group Address Register 7 */
302 /* General Control and Status Registers (0x2_n000) */
305 u32 ievent
; /* Interrupt Event */
306 u32 imask
; /* Interrupt Mask */
307 u32 edis
; /* Error Disabled */
309 u32 ecntrl
; /* Ethernet Control */
310 u32 minflr
; /* Minimum Frame Length */
311 u32 ptv
; /* Pause Time Value */
312 u32 dmactrl
; /* DMA Control */
313 u32 tbipa
; /* TBI PHY Address */
318 /* Transmit Control and Status Registers (0x2_n100) */
319 u32 tctrl
; /* Transmit Control */
320 u32 tstat
; /* Transmit Status */
322 u32 tbdlen
; /* Tx BD Data Length */
324 u32 ctbptr
; /* Current TxBD Pointer */
326 u32 tbptr
; /* TxBD Pointer */
330 u32 tbase
; /* TxBD Base Address */
332 u32 ostbd
; /* Out of Sequence TxBD */
333 u32 ostbdp
; /* Out of Sequence Tx Data Buffer Pointer */
336 /* Receive Control and Status Registers (0x2_n300) */
337 u32 rctrl
; /* Receive Control */
338 u32 rstat
; /* Receive Status */
340 u32 rbdlen
; /* RxBD Data Length */
343 u32 crbptr
; /* Current Receive Buffer Pointer */
345 u32 mrblr
; /* Maximum Receive Buffer Length */
347 u32 rbptr
; /* RxBD Pointer */
351 u32 rbase
; /* RxBD Base Address */
354 /* MAC Registers (0x2_n500) */
355 u32 maccfg1
; /* MAC Configuration #1 */
356 u32 maccfg2
; /* MAC Configuration #2 */
357 u32 ipgifg
; /* Inter Packet Gap/Inter Frame Gap */
358 u32 hafdup
; /* Half-duplex */
359 u32 maxfrm
; /* Maximum Frame */
369 u32 ifstat
; /* Interface Status */
370 u32 macstnaddr1
; /* Station Address, part 1 */
371 u32 macstnaddr2
; /* Station Address, part 2 */
377 /* RMON MIB Registers (0x2_n680-0x2_n73c) */
378 struct tsec_rmon_mib rmon
;
381 /* Hash Function Registers (0x2_n800) */
382 struct tsec_hash_regs hash
;
386 /* Pattern Registers (0x2_nb00) */
388 u32 attr
; /* Default Attribute Register */
389 u32 attreli
; /* Default Attribute Extract Length and Index */
391 /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
395 #define TSEC_GIGABIT (1 << 0)
397 /* These flags currently only have meaning if we're using the eTSEC */
398 #define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */
399 #define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */
401 struct tsec_private
{
402 struct tsec __iomem
*regs
;
403 struct tsec_mii_mng __iomem
*phyregs_sgmii
;
404 struct phy_device
*phydev
;
405 phy_interface_t interface
;
408 char mii_devname
[16];
412 struct tsec_info_struct
{
413 struct tsec __iomem
*regs
;
414 struct tsec_mii_mng __iomem
*miiregs_sgmii
;
417 phy_interface_t interface
;
418 unsigned int phyaddr
;
422 int tsec_standard_init(bd_t
*bis
);
423 int tsec_eth_init(bd_t
*bis
, struct tsec_info_struct
*tsec_info
, int num
);
425 #endif /* __TSEC_H */