include/tsec.h

   1 /*
   2  *  tsec.h
   3  *
   4  *  Driver for the Motorola Triple Speed Ethernet Controller
   5  *
   6  *  This software may be used and distributed according to the
   7  *  terms of the GNU Public License, Version 2, incorporated
   8  *  herein by reference.
   9  *
  10  * Copyright 2004, 2007, 2009, 2011  Freescale Semiconductor, Inc.
  11  * (C) Copyright 2003, Motorola, Inc.
  12  * maintained by Xianghua Xiao (x.xiao@motorola.com)
  13  * author Andy Fleming
  14  *
  15  */
  16
  17 #ifndef __TSEC_H
  18 #define __TSEC_H
  19
  20 #include <net.h>
  21 #include <config.h>
  22 #include <phy.h>
  23 #include <asm/fsl_enet.h>
  24
  25 #define TSEC_SIZE               0x01000
  26 #define TSEC_MDIO_OFFSET        0x01000
  27
  28 #define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
  29
  30 #define DEFAULT_MII_NAME "FSL_MDIO"
  31
  32 #define STD_TSEC_INFO(num) \
  33 {                       \
  34         .regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \
  35         .miiregs_sgmii = (struct tsec_mii_mng *)(CONFIG_SYS_MDIO_BASE_ADDR \
  36                                          + (num - 1) * TSEC_MDIO_OFFSET), \
  37         .devname = CONFIG_TSEC##num##_NAME, \
  38         .phyaddr = TSEC##num##_PHY_ADDR, \
  39         .flags = TSEC##num##_FLAGS, \
  40         .mii_devname = DEFAULT_MII_NAME \
  41 }
  42
  43 #define SET_STD_TSEC_INFO(x, num) \
  44 {                       \
  45         x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \
  46         x.miiregs_sgmii = (struct tsec_mii_mng *)(CONFIG_SYS_MDIO_BASE_ADDR \
  47                                           + (num - 1) * TSEC_MDIO_OFFSET); \
  48         x.devname = CONFIG_TSEC##num##_NAME; \
  49         x.phyaddr = TSEC##num##_PHY_ADDR; \
  50         x.flags = TSEC##num##_FLAGS;\
  51         x.mii_devname = DEFAULT_MII_NAME;\
  52 }
  53
  54 #define MAC_ADDR_LEN 6
  55
  56 /* #define TSEC_TIMEOUT 1000000 */
  57 #define TSEC_TIMEOUT 1000
  58 #define TOUT_LOOP       1000000
  59
  60 /* TBI register addresses */
  61 #define TBI_CR                  0x00
  62 #define TBI_SR                  0x01
  63 #define TBI_ANA                 0x04
  64 #define TBI_ANLPBPA             0x05
  65 #define TBI_ANEX                0x06
  66 #define TBI_TBICON              0x11
  67
  68 /* TBI MDIO register bit fields*/
  69 #define TBICON_CLK_SELECT       0x0020
  70 #define TBIANA_ASYMMETRIC_PAUSE 0x0100
  71 #define TBIANA_SYMMETRIC_PAUSE  0x0080
  72 #define TBIANA_HALF_DUPLEX      0x0040
  73 #define TBIANA_FULL_DUPLEX      0x0020
  74 #define TBICR_PHY_RESET         0x8000
  75 #define TBICR_ANEG_ENABLE       0x1000
  76 #define TBICR_RESTART_ANEG      0x0200
  77 #define TBICR_FULL_DUPLEX       0x0100
  78 #define TBICR_SPEED1_SET        0x0040
  79
  80
  81 /* MAC register bits */
  82 #define MACCFG1_SOFT_RESET      0x80000000
  83 #define MACCFG1_RESET_RX_MC     0x00080000
  84 #define MACCFG1_RESET_TX_MC     0x00040000
  85 #define MACCFG1_RESET_RX_FUN    0x00020000
  86 #define MACCFG1_RESET_TX_FUN    0x00010000
  87 #define MACCFG1_LOOPBACK        0x00000100
  88 #define MACCFG1_RX_FLOW         0x00000020
  89 #define MACCFG1_TX_FLOW         0x00000010
  90 #define MACCFG1_SYNCD_RX_EN     0x00000008
  91 #define MACCFG1_RX_EN           0x00000004
  92 #define MACCFG1_SYNCD_TX_EN     0x00000002
  93 #define MACCFG1_TX_EN           0x00000001
  94
  95 #define MACCFG2_INIT_SETTINGS   0x00007205
  96 #define MACCFG2_FULL_DUPLEX     0x00000001
  97 #define MACCFG2_IF              0x00000300
  98 #define MACCFG2_GMII            0x00000200
  99 #define MACCFG2_MII             0x00000100
 100
 101 #define ECNTRL_INIT_SETTINGS    0x00001000
 102 #define ECNTRL_TBI_MODE         0x00000020
 103 #define ECNTRL_REDUCED_MODE     0x00000010
 104 #define ECNTRL_R100             0x00000008
 105 #define ECNTRL_REDUCED_MII_MODE 0x00000004
 106 #define ECNTRL_SGMII_MODE       0x00000002
 107
 108 #ifndef CONFIG_SYS_TBIPA_VALUE
 109     #define CONFIG_SYS_TBIPA_VALUE      0x1f
 110 #endif
 111
 112 #define MRBLR_INIT_SETTINGS     PKTSIZE_ALIGN
 113
 114 #define MINFLR_INIT_SETTINGS    0x00000040
 115
 116 #define DMACTRL_INIT_SETTINGS   0x000000c3
 117 #define DMACTRL_GRS             0x00000010
 118 #define DMACTRL_GTS             0x00000008
 119
 120 #define TSTAT_CLEAR_THALT       0x80000000
 121 #define RSTAT_CLEAR_RHALT       0x00800000
 122
 123
 124 #define IEVENT_INIT_CLEAR       0xffffffff
 125 #define IEVENT_BABR             0x80000000
 126 #define IEVENT_RXC              0x40000000
 127 #define IEVENT_BSY              0x20000000
 128 #define IEVENT_EBERR            0x10000000
 129 #define IEVENT_MSRO             0x04000000
 130 #define IEVENT_GTSC             0x02000000
 131 #define IEVENT_BABT             0x01000000
 132 #define IEVENT_TXC              0x00800000
 133 #define IEVENT_TXE              0x00400000
 134 #define IEVENT_TXB              0x00200000
 135 #define IEVENT_TXF              0x00100000
 136 #define IEVENT_IE               0x00080000
 137 #define IEVENT_LC               0x00040000
 138 #define IEVENT_CRL              0x00020000
 139 #define IEVENT_XFUN             0x00010000
 140 #define IEVENT_RXB0             0x00008000
 141 #define IEVENT_GRSC             0x00000100
 142 #define IEVENT_RXF0             0x00000080
 143
 144 #define IMASK_INIT_CLEAR        0x00000000
 145 #define IMASK_TXEEN             0x00400000
 146 #define IMASK_TXBEN             0x00200000
 147 #define IMASK_TXFEN             0x00100000
 148 #define IMASK_RXFEN0            0x00000080
 149
 150
 151 /* Default Attribute fields */
 152 #define ATTR_INIT_SETTINGS     0x000000c0
 153 #define ATTRELI_INIT_SETTINGS  0x00000000
 154
 155
 156 /* TxBD status field bits */
 157 #define TXBD_READY              0x8000
 158 #define TXBD_PADCRC             0x4000
 159 #define TXBD_WRAP               0x2000
 160 #define TXBD_INTERRUPT          0x1000
 161 #define TXBD_LAST               0x0800
 162 #define TXBD_CRC                0x0400
 163 #define TXBD_DEF                0x0200
 164 #define TXBD_HUGEFRAME          0x0080
 165 #define TXBD_LATECOLLISION      0x0080
 166 #define TXBD_RETRYLIMIT         0x0040
 167 #define TXBD_RETRYCOUNTMASK     0x003c
 168 #define TXBD_UNDERRUN           0x0002
 169 #define TXBD_STATS              0x03ff
 170
 171 /* RxBD status field bits */
 172 #define RXBD_EMPTY              0x8000
 173 #define RXBD_RO1                0x4000
 174 #define RXBD_WRAP               0x2000
 175 #define RXBD_INTERRUPT          0x1000
 176 #define RXBD_LAST               0x0800
 177 #define RXBD_FIRST              0x0400
 178 #define RXBD_MISS               0x0100
 179 #define RXBD_BROADCAST          0x0080
 180 #define RXBD_MULTICAST          0x0040
 181 #define RXBD_LARGE              0x0020
 182 #define RXBD_NONOCTET           0x0010
 183 #define RXBD_SHORT              0x0008
 184 #define RXBD_CRCERR             0x0004
 185 #define RXBD_OVERRUN            0x0002
 186 #define RXBD_TRUNCATED          0x0001
 187 #define RXBD_STATS              0x003f
 188
 189 typedef struct txbd8
 190 {
 191         ushort       status;         /* Status Fields */
 192         ushort       length;         /* Buffer length */
 193         uint         bufPtr;         /* Buffer Pointer */
 194 } txbd8_t;
 195
 196 typedef struct rxbd8
 197 {
 198         ushort       status;         /* Status Fields */
 199         ushort       length;         /* Buffer Length */
 200         uint         bufPtr;         /* Buffer Pointer */
 201 } rxbd8_t;
 202
 203 typedef struct rmon_mib
 204 {
 205         /* Transmit and Receive Counters */
 206         uint    tr64;           /* Transmit and Receive 64-byte Frame Counter */
 207         uint    tr127;          /* Transmit and Receive 65-127 byte Frame Counter */
 208         uint    tr255;          /* Transmit and Receive 128-255 byte Frame Counter */
 209         uint    tr511;          /* Transmit and Receive 256-511 byte Frame Counter */
 210         uint    tr1k;           /* Transmit and Receive 512-1023 byte Frame Counter */
 211         uint    trmax;          /* Transmit and Receive 1024-1518 byte Frame Counter */
 212         uint    trmgv;          /* Transmit and Receive 1519-1522 byte Good VLAN Frame */
 213         /* Receive Counters */
 214         uint    rbyt;           /* Receive Byte Counter */
 215         uint    rpkt;           /* Receive Packet Counter */
 216         uint    rfcs;           /* Receive FCS Error Counter */
 217         uint    rmca;           /* Receive Multicast Packet (Counter) */
 218         uint    rbca;           /* Receive Broadcast Packet */
 219         uint    rxcf;           /* Receive Control Frame Packet */
 220         uint    rxpf;           /* Receive Pause Frame Packet */
 221         uint    rxuo;           /* Receive Unknown OP Code */
 222         uint    raln;           /* Receive Alignment Error */
 223         uint    rflr;           /* Receive Frame Length Error */
 224         uint    rcde;           /* Receive Code Error */
 225         uint    rcse;           /* Receive Carrier Sense Error */
 226         uint    rund;           /* Receive Undersize Packet */
 227         uint    rovr;           /* Receive Oversize Packet */
 228         uint    rfrg;           /* Receive Fragments */
 229         uint    rjbr;           /* Receive Jabber */
 230         uint    rdrp;           /* Receive Drop */
 231         /* Transmit Counters */
 232         uint    tbyt;           /* Transmit Byte Counter */
 233         uint    tpkt;           /* Transmit Packet */
 234         uint    tmca;           /* Transmit Multicast Packet */
 235         uint    tbca;           /* Transmit Broadcast Packet */
 236         uint    txpf;           /* Transmit Pause Control Frame */
 237         uint    tdfr;           /* Transmit Deferral Packet */
 238         uint    tedf;           /* Transmit Excessive Deferral Packet */
 239         uint    tscl;           /* Transmit Single Collision Packet */
 240         /* (0x2_n700) */
 241         uint    tmcl;           /* Transmit Multiple Collision Packet */
 242         uint    tlcl;           /* Transmit Late Collision Packet */
 243         uint    txcl;           /* Transmit Excessive Collision Packet */
 244         uint    tncl;           /* Transmit Total Collision */
 245
 246         uint    res2;
 247
 248         uint    tdrp;           /* Transmit Drop Frame */
 249         uint    tjbr;           /* Transmit Jabber Frame */
 250         uint    tfcs;           /* Transmit FCS Error */
 251         uint    txcf;           /* Transmit Control Frame */
 252         uint    tovr;           /* Transmit Oversize Frame */
 253         uint    tund;           /* Transmit Undersize Frame */
 254         uint    tfrg;           /* Transmit Fragments Frame */
 255         /* General Registers */
 256         uint    car1;           /* Carry Register One */
 257         uint    car2;           /* Carry Register Two */
 258         uint    cam1;           /* Carry Register One Mask */
 259         uint    cam2;           /* Carry Register Two Mask */
 260 } rmon_mib_t;
 261
 262 typedef struct tsec_hash_regs
 263 {
 264         uint    iaddr0;         /* Individual Address Register 0 */
 265         uint    iaddr1;         /* Individual Address Register 1 */
 266         uint    iaddr2;         /* Individual Address Register 2 */
 267         uint    iaddr3;         /* Individual Address Register 3 */
 268         uint    iaddr4;         /* Individual Address Register 4 */
 269         uint    iaddr5;         /* Individual Address Register 5 */
 270         uint    iaddr6;         /* Individual Address Register 6 */
 271         uint    iaddr7;         /* Individual Address Register 7 */
 272         uint    res1[24];
 273         uint    gaddr0;         /* Group Address Register 0 */
 274         uint    gaddr1;         /* Group Address Register 1 */
 275         uint    gaddr2;         /* Group Address Register 2 */
 276         uint    gaddr3;         /* Group Address Register 3 */
 277         uint    gaddr4;         /* Group Address Register 4 */
 278         uint    gaddr5;         /* Group Address Register 5 */
 279         uint    gaddr6;         /* Group Address Register 6 */
 280         uint    gaddr7;         /* Group Address Register 7 */
 281         uint    res2[24];
 282 } tsec_hash_t;
 283
 284 typedef struct tsec
 285 {
 286         /* General Control and Status Registers (0x2_n000) */
 287         uint    res000[4];
 288
 289         uint    ievent;         /* Interrupt Event */
 290         uint    imask;          /* Interrupt Mask */
 291         uint    edis;           /* Error Disabled */
 292         uint    res01c;
 293         uint    ecntrl;         /* Ethernet Control */
 294         uint    minflr;         /* Minimum Frame Length */
 295         uint    ptv;            /* Pause Time Value */
 296         uint    dmactrl;        /* DMA Control */
 297         uint    tbipa;          /* TBI PHY Address */
 298
 299         uint    res034[3];
 300         uint    res040[48];
 301
 302         /* Transmit Control and Status Registers (0x2_n100) */
 303         uint    tctrl;          /* Transmit Control */
 304         uint    tstat;          /* Transmit Status */
 305         uint    res108;
 306         uint    tbdlen;         /* Tx BD Data Length */
 307         uint    res110[5];
 308         uint    ctbptr;         /* Current TxBD Pointer */
 309         uint    res128[23];
 310         uint    tbptr;          /* TxBD Pointer */
 311         uint    res188[30];
 312         /* (0x2_n200) */
 313         uint    res200;
 314         uint    tbase;          /* TxBD Base Address */
 315         uint    res208[42];
 316         uint    ostbd;          /* Out of Sequence TxBD */
 317         uint    ostbdp;         /* Out of Sequence Tx Data Buffer Pointer */
 318         uint    res2b8[18];
 319
 320         /* Receive Control and Status Registers (0x2_n300) */
 321         uint    rctrl;          /* Receive Control */
 322         uint    rstat;          /* Receive Status */
 323         uint    res308;
 324         uint    rbdlen;         /* RxBD Data Length */
 325         uint    res310[4];
 326         uint    res320;
 327         uint    crbptr; /* Current Receive Buffer Pointer */
 328         uint    res328[6];
 329         uint    mrblr;  /* Maximum Receive Buffer Length */
 330         uint    res344[16];
 331         uint    rbptr;  /* RxBD Pointer */
 332         uint    res388[30];
 333         /* (0x2_n400) */
 334         uint    res400;
 335         uint    rbase;  /* RxBD Base Address */
 336         uint    res408[62];
 337
 338         /* MAC Registers (0x2_n500) */
 339         uint    maccfg1;        /* MAC Configuration #1 */
 340         uint    maccfg2;        /* MAC Configuration #2 */
 341         uint    ipgifg;         /* Inter Packet Gap/Inter Frame Gap */
 342         uint    hafdup;         /* Half-duplex */
 343         uint    maxfrm;         /* Maximum Frame */
 344         uint    res514;
 345         uint    res518;
 346
 347         uint    res51c;
 348
 349         uint    resmdio[6];
 350
 351         uint    res538;
 352
 353         uint    ifstat;         /* Interface Status */
 354         uint    macstnaddr1;    /* Station Address, part 1 */
 355         uint    macstnaddr2;    /* Station Address, part 2 */
 356         uint    res548[46];
 357
 358         /* (0x2_n600) */
 359         uint    res600[32];
 360
 361         /* RMON MIB Registers (0x2_n680-0x2_n73c) */
 362         rmon_mib_t      rmon;
 363         uint    res740[48];
 364
 365         /* Hash Function Registers (0x2_n800) */
 366         tsec_hash_t     hash;
 367
 368         uint    res900[128];
 369
 370         /* Pattern Registers (0x2_nb00) */
 371         uint    resb00[62];
 372         uint    attr;      /* Default Attribute Register */
 373         uint    attreli;           /* Default Attribute Extract Length and Index */
 374
 375         /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
 376         uint    resc00[256];
 377 } tsec_t;
 378
 379 #define TSEC_GIGABIT (1 << 0)
 380
 381 /* These flags currently only have meaning if we're using the eTSEC */
 382 #define TSEC_REDUCED    (1 << 1)        /* MAC-PHY interface uses RGMII */
 383 #define TSEC_SGMII      (1 << 2)        /* MAC-PHY interface uses SGMII */
 384
 385 struct tsec_private {
 386         tsec_t *regs;
 387         struct tsec_mii_mng *phyregs_sgmii;
 388         struct phy_device *phydev;
 389         phy_interface_t interface;
 390         struct mii_dev *bus;
 391         uint phyaddr;
 392         char mii_devname[16];
 393         u32 flags;
 394 };
 395
 396 struct tsec_info_struct {
 397         tsec_t *regs;
 398         struct tsec_mii_mng *miiregs_sgmii;
 399         char *devname;
 400         char *mii_devname;
 401         phy_interface_t interface;
 402         unsigned int phyaddr;
 403         u32 flags;
 404 };
 405
 406 int tsec_standard_init(bd_t *bis);
 407 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num);
 408
 409 #endif /* __TSEC_H */