1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Universal Flash Storage Host controller driver
4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
8 * Santosh Yaraganavi <santosh.sy@samsung.com>
9 * Vinayak Holikatti <h.vinayak@samsung.com>
15 #include <linux/bitfield.h>
16 #include <linux/blk-crypto-profile.h>
17 #include <linux/blk-mq.h>
18 #include <linux/devfreq.h>
19 #include <linux/msi.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/dma-direction.h>
22 #include <scsi/scsi_device.h>
23 #include <ufs/unipro.h>
25 #include <ufs/ufs_quirks.h>
26 #include <ufs/ufshci.h>
28 #define UFSHCD "ufshcd"
33 DEV_CMD_TYPE_NOP
= 0x0,
34 DEV_CMD_TYPE_QUERY
= 0x1,
35 DEV_CMD_TYPE_RPMB
= 0x2,
39 /* uic specific errors */
47 UFS_EVT_AUTO_HIBERN8_ERR
,
49 UFS_EVT_LINK_STARTUP_FAIL
,
64 * struct uic_command - UIC command structure
65 * @command: UIC command
66 * @argument1: UIC command argument 1
67 * @argument2: UIC command argument 2
68 * @argument3: UIC command argument 3
69 * @cmd_active: Indicate if UIC command is outstanding
70 * @done: UIC command completion
78 struct completion done
;
81 /* Used to differentiate the power management options */
88 /* Host <-> Device UniPro Link state */
90 UIC_LINK_OFF_STATE
= 0, /* Link powered down or disabled */
91 UIC_LINK_ACTIVE_STATE
= 1, /* Link is in Fast/Slow/Sleep state */
92 UIC_LINK_HIBERN8_STATE
= 2, /* Link is in Hibernate state */
93 UIC_LINK_BROKEN_STATE
= 3, /* Link is in broken state */
96 #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE)
97 #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \
98 UIC_LINK_ACTIVE_STATE)
99 #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \
100 UIC_LINK_HIBERN8_STATE)
101 #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \
102 UIC_LINK_BROKEN_STATE)
103 #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE)
104 #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \
105 UIC_LINK_ACTIVE_STATE)
106 #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \
107 UIC_LINK_HIBERN8_STATE)
108 #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \
109 UIC_LINK_BROKEN_STATE)
111 #define ufshcd_set_ufs_dev_active(h) \
112 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
113 #define ufshcd_set_ufs_dev_sleep(h) \
114 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
115 #define ufshcd_set_ufs_dev_poweroff(h) \
116 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
117 #define ufshcd_set_ufs_dev_deepsleep(h) \
118 ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE)
119 #define ufshcd_is_ufs_dev_active(h) \
120 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
121 #define ufshcd_is_ufs_dev_sleep(h) \
122 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
123 #define ufshcd_is_ufs_dev_poweroff(h) \
124 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
125 #define ufshcd_is_ufs_dev_deepsleep(h) \
126 ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE)
129 * UFS Power management levels.
130 * Each level is in increasing order of power savings, except DeepSleep
131 * which is lower than PowerDown with power on but not PowerDown with
145 struct ufs_pm_lvl_states
{
146 enum ufs_dev_pwr_mode dev_state
;
147 enum uic_link_state link_state
;
151 * struct ufshcd_lrb - local reference block
152 * @utr_descriptor_ptr: UTRD address of the command
153 * @ucd_req_ptr: UCD address of the command
154 * @ucd_rsp_ptr: Response UPIU address for this command
155 * @ucd_prdt_ptr: PRDT address of the command
156 * @utrd_dma_addr: UTRD dma address for debug
157 * @ucd_prdt_dma_addr: PRDT dma address for debug
158 * @ucd_rsp_dma_addr: UPIU response dma address for debug
159 * @ucd_req_dma_addr: UPIU request dma address for debug
160 * @cmd: pointer to SCSI command
161 * @scsi_status: SCSI status of the command
162 * @command_type: SCSI, UFS, Query.
163 * @task_tag: Task tag of the command
164 * @lun: LUN of the command
165 * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation)
166 * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC)
167 * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock)
168 * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC)
169 * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock)
170 * @crypto_key_slot: the key slot to use for inline crypto (-1 if none)
171 * @data_unit_num: the data unit number for the first block for inline crypto
172 * @req_abort_skip: skip request abort task flag
175 struct utp_transfer_req_desc
*utr_descriptor_ptr
;
176 struct utp_upiu_req
*ucd_req_ptr
;
177 struct utp_upiu_rsp
*ucd_rsp_ptr
;
178 struct ufshcd_sg_entry
*ucd_prdt_ptr
;
180 dma_addr_t utrd_dma_addr
;
181 dma_addr_t ucd_req_dma_addr
;
182 dma_addr_t ucd_rsp_dma_addr
;
183 dma_addr_t ucd_prdt_dma_addr
;
185 struct scsi_cmnd
*cmd
;
190 u8 lun
; /* UPIU LUN id field is only 8-bit wide */
192 ktime_t issue_time_stamp
;
193 u64 issue_time_stamp_local_clock
;
194 ktime_t compl_time_stamp
;
195 u64 compl_time_stamp_local_clock
;
196 #ifdef CONFIG_SCSI_UFS_CRYPTO
205 * struct ufs_query - holds relevant data structures for query request
206 * @request: request upiu and function
207 * @descriptor: buffer for sending/receiving descriptor
208 * @response: response upiu and response
211 struct ufs_query_req request
;
213 struct ufs_query_res response
;
217 * struct ufs_dev_cmd - all assosiated fields with device management commands
218 * @type: device management command type - Query, NOP OUT
219 * @lock: lock to allow one command at a time
220 * @complete: internal commands completion
221 * @query: Device management query information
224 enum dev_cmd_type type
;
226 struct completion
*complete
;
227 struct ufs_query query
;
228 struct cq_entry
*cqe
;
232 * struct ufs_clk_info - UFS clock related info
233 * @list: list headed by hba->clk_list_head
236 * @max_freq: maximum frequency supported by the clock
237 * @min_freq: min frequency that can be used for clock scaling
238 * @curr_freq: indicates the current frequency that it is set to
239 * @keep_link_active: indicates that the clk should not be disabled if
241 * @enabled: variable to check against multiple enable/disable
243 struct ufs_clk_info
{
244 struct list_head list
;
250 bool keep_link_active
;
254 enum ufs_notify_change_status
{
259 struct ufs_pa_layer_attr
{
269 struct ufs_pwr_mode_info
{
271 struct ufs_pa_layer_attr info
;
275 * struct ufs_hba_variant_ops - variant specific callbacks
276 * @name: variant name
277 * @init: called when the driver is initialized
278 * @exit: called to cleanup everything done in init
279 * @get_ufs_hci_version: called to get UFS HCI version
280 * @clk_scale_notify: notifies that clks are scaled up/down
281 * @setup_clocks: called before touching any of the controller registers
282 * @hce_enable_notify: called before and after HCE enable bit is set to allow
283 * variant specific Uni-Pro initialization.
284 * @link_startup_notify: called before and after Link startup is carried out
285 * to allow variant specific Uni-Pro initialization.
286 * @pwr_change_notify: called before and after a power mode change
287 * is carried out to allow vendor spesific capabilities
289 * @setup_xfer_req: called before any transfer request is issued
291 * @setup_task_mgmt: called before any task management request is issued
293 * @hibern8_notify: called around hibern8 enter/exit
294 * @apply_dev_quirks: called to apply device specific quirks
295 * @fixup_dev_quirks: called to modify device specific quirks
296 * @suspend: called during host controller PM callback
297 * @resume: called during host controller PM callback
298 * @dbg_register_dump: used to dump controller debug information
299 * @phy_initialization: used to initialize phys
300 * @device_reset: called to issue a reset pulse on the UFS device
301 * @config_scaling_param: called to configure clock scaling parameters
302 * @program_key: program or evict an inline encryption key
303 * @event_notify: called to notify important events
304 * @reinit_notify: called to notify reinit of UFSHCD during max gear switch
305 * @mcq_config_resource: called to configure MCQ platform resources
306 * @get_hba_mac: called to get vendor specific mac value, mandatory for mcq mode
307 * @op_runtime_config: called to config Operation and runtime regs Pointers
308 * @get_outstanding_cqs: called to get outstanding completion queues
309 * @config_esi: called to config Event Specific Interrupt
311 struct ufs_hba_variant_ops
{
313 int (*init
)(struct ufs_hba
*);
314 void (*exit
)(struct ufs_hba
*);
315 u32 (*get_ufs_hci_version
)(struct ufs_hba
*);
316 int (*clk_scale_notify
)(struct ufs_hba
*, bool,
317 enum ufs_notify_change_status
);
318 int (*setup_clocks
)(struct ufs_hba
*, bool,
319 enum ufs_notify_change_status
);
320 int (*hce_enable_notify
)(struct ufs_hba
*,
321 enum ufs_notify_change_status
);
322 int (*link_startup_notify
)(struct ufs_hba
*,
323 enum ufs_notify_change_status
);
324 int (*pwr_change_notify
)(struct ufs_hba
*,
325 enum ufs_notify_change_status status
,
326 struct ufs_pa_layer_attr
*,
327 struct ufs_pa_layer_attr
*);
328 void (*setup_xfer_req
)(struct ufs_hba
*hba
, int tag
,
330 void (*setup_task_mgmt
)(struct ufs_hba
*, int, u8
);
331 void (*hibern8_notify
)(struct ufs_hba
*, enum uic_cmd_dme
,
332 enum ufs_notify_change_status
);
333 int (*apply_dev_quirks
)(struct ufs_hba
*hba
);
334 void (*fixup_dev_quirks
)(struct ufs_hba
*hba
);
335 int (*suspend
)(struct ufs_hba
*, enum ufs_pm_op
,
336 enum ufs_notify_change_status
);
337 int (*resume
)(struct ufs_hba
*, enum ufs_pm_op
);
338 void (*dbg_register_dump
)(struct ufs_hba
*hba
);
339 int (*phy_initialization
)(struct ufs_hba
*);
340 int (*device_reset
)(struct ufs_hba
*hba
);
341 void (*config_scaling_param
)(struct ufs_hba
*hba
,
342 struct devfreq_dev_profile
*profile
,
343 struct devfreq_simple_ondemand_data
*data
);
344 int (*program_key
)(struct ufs_hba
*hba
,
345 const union ufs_crypto_cfg_entry
*cfg
, int slot
);
346 void (*event_notify
)(struct ufs_hba
*hba
,
347 enum ufs_event_type evt
, void *data
);
348 void (*reinit_notify
)(struct ufs_hba
*);
349 int (*mcq_config_resource
)(struct ufs_hba
*hba
);
350 int (*get_hba_mac
)(struct ufs_hba
*hba
);
351 int (*op_runtime_config
)(struct ufs_hba
*hba
);
352 int (*get_outstanding_cqs
)(struct ufs_hba
*hba
,
353 unsigned long *ocqs
);
354 int (*config_esi
)(struct ufs_hba
*hba
);
357 /* clock gating state */
358 enum clk_gating_state
{
366 * struct ufs_clk_gating - UFS clock gating related info
367 * @gate_work: worker to turn off clocks after some delay as specified in
369 * @ungate_work: worker to turn on clocks that will be used in case of
371 * @state: the current clocks state
372 * @delay_ms: gating delay in ms
373 * @is_suspended: clk gating is suspended when set to 1 which can be used
374 * during suspend/resume
375 * @delay_attr: sysfs attribute to control delay_attr
376 * @enable_attr: sysfs attribute to enable/disable clock gating
377 * @is_enabled: Indicates the current status of clock gating
378 * @is_initialized: Indicates whether clock gating is initialized or not
379 * @active_reqs: number of requests that are pending and should be waited for
380 * completion before gating clocks.
381 * @clk_gating_workq: workqueue for clock gating work.
383 struct ufs_clk_gating
{
384 struct delayed_work gate_work
;
385 struct work_struct ungate_work
;
386 enum clk_gating_state state
;
387 unsigned long delay_ms
;
389 struct device_attribute delay_attr
;
390 struct device_attribute enable_attr
;
394 struct workqueue_struct
*clk_gating_workq
;
397 struct ufs_saved_pwr_info
{
398 struct ufs_pa_layer_attr info
;
403 * struct ufs_clk_scaling - UFS clock scaling related data
404 * @active_reqs: number of requests that are pending. If this is zero when
405 * devfreq ->target() function is called then schedule "suspend_work" to
407 * @tot_busy_t: Total busy time in current polling window
408 * @window_start_t: Start time (in jiffies) of the current polling window
409 * @busy_start_t: Start time of current busy period
410 * @enable_attr: sysfs attribute to enable/disable clock scaling
411 * @saved_pwr_info: UFS power mode may also be changed during scaling and this
412 * one keeps track of previous power mode.
413 * @workq: workqueue to schedule devfreq suspend/resume work
414 * @suspend_work: worker to suspend devfreq
415 * @resume_work: worker to resume devfreq
416 * @min_gear: lowest HS gear to scale down to
417 * @is_enabled: tracks if scaling is currently enabled or not, controlled by
418 * clkscale_enable sysfs node
419 * @is_allowed: tracks if scaling is currently allowed or not, used to block
420 * clock scaling which is not invoked from devfreq governor
421 * @is_initialized: Indicates whether clock scaling is initialized or not
422 * @is_busy_started: tracks if busy period has started or not
423 * @is_suspended: tracks if devfreq is suspended or not
425 struct ufs_clk_scaling
{
427 unsigned long tot_busy_t
;
428 ktime_t window_start_t
;
429 ktime_t busy_start_t
;
430 struct device_attribute enable_attr
;
431 struct ufs_saved_pwr_info saved_pwr_info
;
432 struct workqueue_struct
*workq
;
433 struct work_struct suspend_work
;
434 struct work_struct resume_work
;
439 bool is_busy_started
;
443 #define UFS_EVENT_HIST_LENGTH 8
445 * struct ufs_event_hist - keeps history of errors
446 * @pos: index to indicate cyclic buffer position
447 * @val: cyclic buffer for registers value
448 * @tstamp: cyclic buffer for time stamp
449 * @cnt: error counter
451 struct ufs_event_hist
{
453 u32 val
[UFS_EVENT_HIST_LENGTH
];
454 u64 tstamp
[UFS_EVENT_HIST_LENGTH
];
455 unsigned long long cnt
;
459 * struct ufs_stats - keeps usage/err statistics
460 * @last_intr_status: record the last interrupt status.
461 * @last_intr_ts: record the last interrupt timestamp.
462 * @hibern8_exit_cnt: Counter to keep track of number of exits,
463 * reset this after link-startup.
464 * @last_hibern8_exit_tstamp: Set time after the hibern8 exit.
465 * Clear after the first successful command completion.
466 * @event: array with event history.
469 u32 last_intr_status
;
472 u32 hibern8_exit_cnt
;
473 u64 last_hibern8_exit_tstamp
;
474 struct ufs_event_hist event
[UFS_EVT_CNT
];
478 * enum ufshcd_state - UFS host controller state
479 * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command
481 * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process
483 * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled.
484 * SCSI commands may be submitted to the controller.
485 * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail
486 * newly submitted SCSI commands with error code DID_BAD_TARGET.
487 * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery
488 * failed. Fail all SCSI commands with error code DID_ERROR.
492 UFSHCD_STATE_OPERATIONAL
,
493 UFSHCD_STATE_EH_SCHEDULED_NON_FATAL
,
494 UFSHCD_STATE_EH_SCHEDULED_FATAL
,
499 /* Interrupt aggregation support is broken */
500 UFSHCD_QUIRK_BROKEN_INTR_AGGR
= 1 << 0,
503 * delay before each dme command is required as the unipro
504 * layer has shown instabilities
506 UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
= 1 << 1,
509 * If UFS host controller is having issue in processing LCC (Line
510 * Control Command) coming from device then enable this quirk.
511 * When this quirk is enabled, host controller driver should disable
512 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
513 * attribute of device to 0).
515 UFSHCD_QUIRK_BROKEN_LCC
= 1 << 2,
518 * The attribute PA_RXHSUNTERMCAP specifies whether or not the
519 * inbound Link supports unterminated line in HS mode. Setting this
520 * attribute to 1 fixes moving to HS gear.
522 UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
= 1 << 3,
525 * This quirk needs to be enabled if the host controller only allows
526 * accessing the peer dme attributes in AUTO mode (FAST AUTO or
529 UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
= 1 << 4,
532 * This quirk needs to be enabled if the host controller doesn't
533 * advertise the correct version in UFS_VER register. If this quirk
534 * is enabled, standard UFS host driver will call the vendor specific
535 * ops (get_ufs_hci_version) to get the correct version.
537 UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION
= 1 << 5,
540 * Clear handling for transfer/task request list is just opposite.
542 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR
= 1 << 6,
545 * This quirk needs to be enabled if host controller doesn't allow
546 * that the interrupt aggregation timer and counter are reset by s/w.
548 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR
= 1 << 7,
551 * This quirks needs to be enabled if host controller cannot be
552 * enabled via HCE register.
554 UFSHCI_QUIRK_BROKEN_HCE
= 1 << 8,
557 * This quirk needs to be enabled if the host controller regards
558 * resolution of the values of PRDTO and PRDTL in UTRD as byte.
560 UFSHCD_QUIRK_PRDT_BYTE_GRAN
= 1 << 9,
563 * This quirk needs to be enabled if the host controller reports
564 * OCS FATAL ERROR with device error through sense data
566 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR
= 1 << 10,
569 * This quirk needs to be enabled if the host controller has
570 * auto-hibernate capability but it doesn't work.
572 UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8
= 1 << 11,
575 * This quirk needs to disable manual flush for write booster
577 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL
= 1 << 12,
580 * This quirk needs to disable unipro timeout values
581 * before power mode change
583 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING
= 1 << 13,
586 * Align DMA SG entries on a 4 KiB boundary.
588 UFSHCD_QUIRK_4KB_DMA_ALIGNMENT
= 1 << 14,
591 * This quirk needs to be enabled if the host controller does not
592 * support UIC command
594 UFSHCD_QUIRK_BROKEN_UIC_CMD
= 1 << 15,
597 * This quirk needs to be enabled if the host controller cannot
598 * support physical host configuration.
600 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION
= 1 << 16,
603 * This quirk needs to be enabled if the host controller has
604 * 64-bit addressing supported capability but it doesn't work.
606 UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS
= 1 << 17,
609 * This quirk needs to be enabled if the host controller has
610 * auto-hibernate capability but it's FASTAUTO only.
612 UFSHCD_QUIRK_HIBERN_FASTAUTO
= 1 << 18,
615 * This quirk needs to be enabled if the host controller needs
616 * to reinit the device after switching to maximum gear.
618 UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH
= 1 << 19,
622 /* Allow dynamic clk gating */
623 UFSHCD_CAP_CLK_GATING
= 1 << 0,
625 /* Allow hiberb8 with clk gating */
626 UFSHCD_CAP_HIBERN8_WITH_CLK_GATING
= 1 << 1,
628 /* Allow dynamic clk scaling */
629 UFSHCD_CAP_CLK_SCALING
= 1 << 2,
631 /* Allow auto bkops to enabled during runtime suspend */
632 UFSHCD_CAP_AUTO_BKOPS_SUSPEND
= 1 << 3,
635 * This capability allows host controller driver to use the UFS HCI's
636 * interrupt aggregation capability.
637 * CAUTION: Enabling this might reduce overall UFS throughput.
639 UFSHCD_CAP_INTR_AGGR
= 1 << 4,
642 * This capability allows the device auto-bkops to be always enabled
643 * except during suspend (both runtime and suspend).
644 * Enabling this capability means that device will always be allowed
645 * to do background operation when it's active but it might degrade
646 * the performance of ongoing read/write operations.
648 UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND
= 1 << 5,
651 * This capability allows host controller driver to automatically
652 * enable runtime power management by itself instead of waiting
653 * for userspace to control the power management.
655 UFSHCD_CAP_RPM_AUTOSUSPEND
= 1 << 6,
658 * This capability allows the host controller driver to turn-on
659 * WriteBooster, if the underlying device supports it and is
660 * provisioned to be used. This would increase the write performance.
662 UFSHCD_CAP_WB_EN
= 1 << 7,
665 * This capability allows the host controller driver to use the
666 * inline crypto engine, if it is present
668 UFSHCD_CAP_CRYPTO
= 1 << 8,
671 * This capability allows the controller regulators to be put into
672 * lpm mode aggressively during clock gating.
673 * This would increase power savings.
675 UFSHCD_CAP_AGGR_POWER_COLLAPSE
= 1 << 9,
678 * This capability allows the host controller driver to use DeepSleep,
679 * if it is supported by the UFS device. The host controller driver must
680 * support device hardware reset via the hba->device_reset() callback,
681 * in order to exit DeepSleep state.
683 UFSHCD_CAP_DEEPSLEEP
= 1 << 10,
686 * This capability allows the host controller driver to use temperature
687 * notification if it is supported by the UFS device.
689 UFSHCD_CAP_TEMP_NOTIF
= 1 << 11,
692 * Enable WriteBooster when scaling up the clock and disable
693 * WriteBooster when scaling the clock down.
695 UFSHCD_CAP_WB_WITH_CLK_SCALING
= 1 << 12,
698 struct ufs_hba_variant_params
{
699 struct devfreq_dev_profile devfreq_profile
;
700 struct devfreq_simple_ondemand_data ondemand_data
;
701 u16 hba_enable_delay_us
;
702 u32 wb_flush_threshold
;
705 #ifdef CONFIG_SCSI_UFS_HPB
707 * struct ufshpb_dev_info - UFSHPB device related info
708 * @num_lu: the number of user logical unit to check whether all lu finished
710 * @rgn_size: device reported HPB region size
711 * @srgn_size: device reported HPB sub-region size
712 * @slave_conf_cnt: counter to check all lu finished initialization
713 * @hpb_disabled: flag to check if HPB is disabled
714 * @max_hpb_single_cmd: device reported bMAX_DATA_SIZE_FOR_SINGLE_CMD value
715 * @is_legacy: flag to check HPB 1.0
716 * @control_mode: either host or device
718 struct ufshpb_dev_info
{
722 atomic_t slave_conf_cnt
;
724 u8 max_hpb_single_cmd
;
730 struct ufs_hba_monitor
{
731 unsigned long chunk_size
;
733 unsigned long nr_sec_rw
[2];
734 ktime_t total_busy
[2];
736 unsigned long nr_req
[2];
743 ktime_t busy_start_ts
[2];
750 * struct ufshcd_res_info_t - MCQ related resource regions
752 * @name: resource name
753 * @resource: pointer to resource region
754 * @base: register base address
756 struct ufshcd_res_info
{
758 struct resource
*resource
;
774 * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers
776 * @offset: Doorbell Address Offset
777 * @stride: Steps proportional to queue [0...31]
778 * @base: base address
780 struct ufshcd_mcq_opr_info_t
{
781 unsigned long offset
;
782 unsigned long stride
;
786 enum ufshcd_mcq_opr
{
795 * struct ufs_hba - per adapter private structure
796 * @mmio_base: UFSHCI base register address
797 * @ucdl_base_addr: UFS Command Descriptor base address
798 * @utrdl_base_addr: UTP Transfer Request Descriptor base address
799 * @utmrdl_base_addr: UTP Task Management Descriptor base address
800 * @ucdl_dma_addr: UFS Command Descriptor DMA address
801 * @utrdl_dma_addr: UTRDL DMA address
802 * @utmrdl_dma_addr: UTMRDL DMA address
803 * @host: Scsi_Host instance of the driver
804 * @dev: device handle
805 * @ufs_device_wlun: WLUN that controls the entire UFS device.
806 * @hwmon_device: device instance registered with the hwmon core.
807 * @curr_dev_pwr_mode: active UFS device power mode.
808 * @uic_link_state: active state of the link to the UFS device.
809 * @rpm_lvl: desired UFS power management level during runtime PM.
810 * @spm_lvl: desired UFS power management level during system PM.
811 * @pm_op_in_progress: whether or not a PM operation is in progress.
812 * @ahit: value of Auto-Hibernate Idle Timer register.
813 * @lrb: local reference block
814 * @outstanding_tasks: Bits representing outstanding task requests
815 * @outstanding_lock: Protects @outstanding_reqs.
816 * @outstanding_reqs: Bits representing outstanding transfer requests
817 * @capabilities: UFS Controller Capabilities
818 * @mcq_capabilities: UFS Multi Circular Queue capabilities
819 * @nutrs: Transfer Request Queue depth supported by controller
820 * @nutmrs: Task Management Queue depth supported by controller
821 * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock.
822 * @ufs_version: UFS Version to which controller complies
823 * @vops: pointer to variant specific operations
824 * @vps: pointer to variant specific parameters
825 * @priv: pointer to variant specific private data
826 * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields)
827 * @irq: Irq number of the controller
828 * @is_irq_enabled: whether or not the UFS controller interrupt is enabled.
829 * @dev_ref_clk_freq: reference clock frequency
830 * @quirks: bitmask with information about deviations from the UFSHCI standard.
831 * @dev_quirks: bitmask with information about deviations from the UFS standard.
832 * @tmf_tag_set: TMF tag set.
833 * @tmf_queue: Used to allocate TMF tags.
834 * @tmf_rqs: array with pointers to TMF requests while these are in progress.
835 * @active_uic_cmd: handle of active UIC command
836 * @uic_cmd_mutex: mutex for UIC command
837 * @uic_async_done: completion used during UIC processing
838 * @ufshcd_state: UFSHCD state
839 * @eh_flags: Error handling flags
840 * @intr_mask: Interrupt Mask Bits
841 * @ee_ctrl_mask: Exception event control mask
842 * @ee_drv_mask: Exception event mask for driver
843 * @ee_usr_mask: Exception event mask for user (set via debugfs)
844 * @ee_ctrl_mutex: Used to serialize exception event information.
845 * @is_powered: flag to check if HBA is powered
846 * @shutting_down: flag to check if shutdown has been invoked
847 * @host_sem: semaphore used to serialize concurrent contexts
848 * @eh_wq: Workqueue that eh_work works on
849 * @eh_work: Worker to handle UFS errors that require s/w attention
850 * @eeh_work: Worker to handle exception events
851 * @errors: HBA errors
852 * @uic_error: UFS interconnect layer error status
853 * @saved_err: sticky error mask
854 * @saved_uic_err: sticky UIC error mask
855 * @ufs_stats: various error counters
856 * @force_reset: flag to force eh_work perform a full reset
857 * @force_pmc: flag to force a power mode change
858 * @silence_err_logs: flag to silence error logs
859 * @dev_cmd: ufs device management command information
860 * @last_dme_cmd_tstamp: time stamp of the last completed DME command
861 * @nop_out_timeout: NOP OUT timeout value
862 * @dev_info: information about the UFS device
863 * @auto_bkops_enabled: to track whether bkops is enabled in device
864 * @vreg_info: UFS device voltage regulator information
865 * @clk_list_head: UFS host controller clocks list node head
866 * @req_abort_count: number of times ufshcd_abort() has been called
867 * @lanes_per_direction: number of lanes per data direction between the UFS
868 * controller and the UFS device.
869 * @pwr_info: holds current power mode
870 * @max_pwr_info: keeps the device max valid pwm
871 * @clk_gating: information related to clock gating
872 * @caps: bitmask with information about UFS controller capabilities
873 * @devfreq: frequency scaling information owned by the devfreq core
874 * @clk_scaling: frequency scaling information owned by the UFS driver
875 * @system_suspending: system suspend has been started and system resume has
877 * @is_sys_suspended: UFS device has been suspended because of system suspend
878 * @urgent_bkops_lvl: keeps track of urgent bkops level for device
879 * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for
880 * device is known or not.
881 * @wb_mutex: used to serialize devfreq and sysfs write booster toggling
882 * @clk_scaling_lock: used to serialize device commands and clock scaling
883 * @desc_size: descriptor sizes reported by device
884 * @scsi_block_reqs_cnt: reference counting for scsi block requests
885 * @bsg_dev: struct device associated with the BSG queue
886 * @bsg_queue: BSG queue associated with the UFS controller
887 * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power
888 * management) after the UFS device has finished a WriteBooster buffer
889 * flush or auto BKOP.
890 * @ufshpb_dev: information related to HPB (Host Performance Booster).
891 * @monitor: statistics about UFS commands
892 * @crypto_capabilities: Content of crypto capabilities register (0x100)
893 * @crypto_cap_array: Array of crypto capabilities
894 * @crypto_cfg_register: Start of the crypto cfg array
895 * @crypto_profile: the crypto profile of this hba (if applicable)
896 * @debugfs_root: UFS controller debugfs root directory
897 * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay
898 * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore
900 * @luns_avail: number of regular and well known LUNs supported by the UFS
902 * @nr_hw_queues: number of hardware queues configured
903 * @nr_queues: number of Queues of different queue types
904 * @complete_put: whether or not to call ufshcd_rpm_put() from inside
905 * ufshcd_resume_complete()
906 * @ext_iid_sup: is EXT_IID is supported by UFSHC
907 * @mcq_sup: is mcq supported by UFSHC
908 * @mcq_enabled: is mcq ready to accept requests
909 * @res: array of resource info of MCQ registers
910 * @mcq_base: Multi circular queue registers base address
911 * @uhq: array of supported hardware queues
912 * @dev_cmd_queue: Queue for issuing device management commands
915 void __iomem
*mmio_base
;
917 /* Virtual memory reference */
918 struct utp_transfer_cmd_desc
*ucdl_base_addr
;
919 struct utp_transfer_req_desc
*utrdl_base_addr
;
920 struct utp_task_req_desc
*utmrdl_base_addr
;
922 /* DMA memory reference */
923 dma_addr_t ucdl_dma_addr
;
924 dma_addr_t utrdl_dma_addr
;
925 dma_addr_t utmrdl_dma_addr
;
927 struct Scsi_Host
*host
;
929 struct scsi_device
*ufs_device_wlun
;
931 #ifdef CONFIG_SCSI_UFS_HWMON
932 struct device
*hwmon_device
;
935 enum ufs_dev_pwr_mode curr_dev_pwr_mode
;
936 enum uic_link_state uic_link_state
;
937 /* Desired UFS power management level during runtime PM */
938 enum ufs_pm_level rpm_lvl
;
939 /* Desired UFS power management level during system PM */
940 enum ufs_pm_level spm_lvl
;
941 int pm_op_in_progress
;
943 /* Auto-Hibernate Idle Timer register value */
946 struct ufshcd_lrb
*lrb
;
948 unsigned long outstanding_tasks
;
949 spinlock_t outstanding_lock
;
950 unsigned long outstanding_reqs
;
954 u32 mcq_capabilities
;
958 const struct ufs_hba_variant_ops
*vops
;
959 struct ufs_hba_variant_params
*vps
;
961 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE
962 size_t sg_entry_size
;
966 enum ufs_ref_clk_freq dev_ref_clk_freq
;
968 unsigned int quirks
; /* Deviations from standard UFSHCI spec. */
970 /* Device deviations from standard UFS device spec. */
971 unsigned int dev_quirks
;
973 struct blk_mq_tag_set tmf_tag_set
;
974 struct request_queue
*tmf_queue
;
975 struct request
**tmf_rqs
;
977 struct uic_command
*active_uic_cmd
;
978 struct mutex uic_cmd_mutex
;
979 struct completion
*uic_async_done
;
981 enum ufshcd_state ufshcd_state
;
987 struct mutex ee_ctrl_mutex
;
990 struct semaphore host_sem
;
993 struct workqueue_struct
*eh_wq
;
994 struct work_struct eh_work
;
995 struct work_struct eeh_work
;
1002 struct ufs_stats ufs_stats
;
1005 bool silence_err_logs
;
1007 /* Device management request data */
1008 struct ufs_dev_cmd dev_cmd
;
1009 ktime_t last_dme_cmd_tstamp
;
1010 int nop_out_timeout
;
1012 /* Keeps information of the UFS device connected to this host */
1013 struct ufs_dev_info dev_info
;
1014 bool auto_bkops_enabled
;
1015 struct ufs_vreg_info vreg_info
;
1016 struct list_head clk_list_head
;
1018 /* Number of requests aborts */
1019 int req_abort_count
;
1021 /* Number of lanes available (1 or 2) for Rx/Tx */
1022 u32 lanes_per_direction
;
1023 struct ufs_pa_layer_attr pwr_info
;
1024 struct ufs_pwr_mode_info max_pwr_info
;
1026 struct ufs_clk_gating clk_gating
;
1027 /* Control to enable/disable host capabilities */
1030 struct devfreq
*devfreq
;
1031 struct ufs_clk_scaling clk_scaling
;
1032 bool system_suspending
;
1033 bool is_sys_suspended
;
1035 enum bkops_status urgent_bkops_lvl
;
1036 bool is_urgent_bkops_lvl_checked
;
1038 struct mutex wb_mutex
;
1039 struct rw_semaphore clk_scaling_lock
;
1040 atomic_t scsi_block_reqs_cnt
;
1042 struct device bsg_dev
;
1043 struct request_queue
*bsg_queue
;
1044 struct delayed_work rpm_dev_flush_recheck_work
;
1046 #ifdef CONFIG_SCSI_UFS_HPB
1047 struct ufshpb_dev_info ufshpb_dev
;
1050 struct ufs_hba_monitor monitor
;
1052 #ifdef CONFIG_SCSI_UFS_CRYPTO
1053 union ufs_crypto_capabilities crypto_capabilities
;
1054 union ufs_crypto_cap_entry
*crypto_cap_array
;
1055 u32 crypto_cfg_register
;
1056 struct blk_crypto_profile crypto_profile
;
1058 #ifdef CONFIG_DEBUG_FS
1059 struct dentry
*debugfs_root
;
1060 struct delayed_work debugfs_ee_work
;
1061 u32 debugfs_ee_rate_limit_ms
;
1064 unsigned int nr_hw_queues
;
1065 unsigned int nr_queues
[HCTX_MAX_TYPES
];
1068 bool scsi_host_added
;
1071 struct ufshcd_res_info res
[RES_MAX
];
1072 void __iomem
*mcq_base
;
1073 struct ufs_hw_queue
*uhq
;
1074 struct ufs_hw_queue
*dev_cmd_queue
;
1075 struct ufshcd_mcq_opr_info_t mcq_opr
[OPR_MAX
];
1079 * struct ufs_hw_queue - per hardware queue structure
1080 * @mcq_sq_head: base address of submission queue head pointer
1081 * @mcq_sq_tail: base address of submission queue tail pointer
1082 * @mcq_cq_head: base address of completion queue head pointer
1083 * @mcq_cq_tail: base address of completion queue tail pointer
1084 * @sqe_base_addr: submission queue entry base address
1085 * @sqe_dma_addr: submission queue dma address
1086 * @cqe_base_addr: completion queue base address
1087 * @cqe_dma_addr: completion queue dma address
1088 * @max_entries: max number of slots in this hardware queue
1089 * @id: hardware queue ID
1090 * @sq_tp_slot: current slot to which SQ tail pointer is pointing
1091 * @sq_lock: serialize submission queue access
1092 * @cq_tail_slot: current slot to which CQ tail pointer is pointing
1093 * @cq_head_slot: current slot to which CQ head pointer is pointing
1094 * @cq_lock: Synchronize between multiple polling instances
1096 struct ufs_hw_queue
{
1097 void __iomem
*mcq_sq_head
;
1098 void __iomem
*mcq_sq_tail
;
1099 void __iomem
*mcq_cq_head
;
1100 void __iomem
*mcq_cq_tail
;
1102 void *sqe_base_addr
;
1103 dma_addr_t sqe_dma_addr
;
1104 struct cq_entry
*cqe_base_addr
;
1105 dma_addr_t cqe_dma_addr
;
1115 static inline bool is_mcq_enabled(struct ufs_hba
*hba
)
1117 return hba
->mcq_enabled
;
1120 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE
1121 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba
*hba
)
1123 return hba
->sg_entry_size
;
1126 static inline void ufshcd_set_sg_entry_size(struct ufs_hba
*hba
, size_t sg_entry_size
)
1128 WARN_ON_ONCE(sg_entry_size
< sizeof(struct ufshcd_sg_entry
));
1129 hba
->sg_entry_size
= sg_entry_size
;
1132 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba
*hba
)
1134 return sizeof(struct ufshcd_sg_entry
);
1137 #define ufshcd_set_sg_entry_size(hba, sg_entry_size) \
1138 ({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); })
1141 static inline size_t sizeof_utp_transfer_cmd_desc(const struct ufs_hba
*hba
)
1143 return sizeof(struct utp_transfer_cmd_desc
) + SG_ALL
* ufshcd_sg_entry_size(hba
);
1146 /* Returns true if clocks can be gated. Otherwise false */
1147 static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba
*hba
)
1149 return hba
->caps
& UFSHCD_CAP_CLK_GATING
;
1151 static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba
*hba
)
1153 return hba
->caps
& UFSHCD_CAP_HIBERN8_WITH_CLK_GATING
;
1155 static inline int ufshcd_is_clkscaling_supported(struct ufs_hba
*hba
)
1157 return hba
->caps
& UFSHCD_CAP_CLK_SCALING
;
1159 static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba
*hba
)
1161 return hba
->caps
& UFSHCD_CAP_AUTO_BKOPS_SUSPEND
;
1163 static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba
*hba
)
1165 return hba
->caps
& UFSHCD_CAP_RPM_AUTOSUSPEND
;
1168 static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba
*hba
)
1170 return (hba
->caps
& UFSHCD_CAP_INTR_AGGR
) &&
1171 !(hba
->quirks
& UFSHCD_QUIRK_BROKEN_INTR_AGGR
);
1174 static inline bool ufshcd_can_aggressive_pc(struct ufs_hba
*hba
)
1176 return !!(ufshcd_is_link_hibern8(hba
) &&
1177 (hba
->caps
& UFSHCD_CAP_AGGR_POWER_COLLAPSE
));
1180 static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba
*hba
)
1182 return (hba
->capabilities
& MASK_AUTO_HIBERN8_SUPPORT
) &&
1183 !(hba
->quirks
& UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8
);
1186 static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba
*hba
)
1188 return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK
, hba
->ahit
);
1191 static inline bool ufshcd_is_wb_allowed(struct ufs_hba
*hba
)
1193 return hba
->caps
& UFSHCD_CAP_WB_EN
;
1196 static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba
*hba
)
1198 return hba
->caps
& UFSHCD_CAP_WB_WITH_CLK_SCALING
;
1201 #define ufsmcq_writel(hba, val, reg) \
1202 writel((val), (hba)->mcq_base + (reg))
1203 #define ufsmcq_readl(hba, reg) \
1204 readl((hba)->mcq_base + (reg))
1206 #define ufsmcq_writelx(hba, val, reg) \
1207 writel_relaxed((val), (hba)->mcq_base + (reg))
1208 #define ufsmcq_readlx(hba, reg) \
1209 readl_relaxed((hba)->mcq_base + (reg))
1211 #define ufshcd_writel(hba, val, reg) \
1212 writel((val), (hba)->mmio_base + (reg))
1213 #define ufshcd_readl(hba, reg) \
1214 readl((hba)->mmio_base + (reg))
1217 * ufshcd_rmwl - perform read/modify/write for a controller register
1218 * @hba: per adapter instance
1219 * @mask: mask to apply on read value
1220 * @val: actual value to write
1221 * @reg: register address
1223 static inline void ufshcd_rmwl(struct ufs_hba
*hba
, u32 mask
, u32 val
, u32 reg
)
1227 tmp
= ufshcd_readl(hba
, reg
);
1229 tmp
|= (val
& mask
);
1230 ufshcd_writel(hba
, tmp
, reg
);
1233 int ufshcd_alloc_host(struct device
*, struct ufs_hba
**);
1234 void ufshcd_dealloc_host(struct ufs_hba
*);
1235 int ufshcd_hba_enable(struct ufs_hba
*hba
);
1236 int ufshcd_init(struct ufs_hba
*, void __iomem
*, unsigned int);
1237 int ufshcd_link_recovery(struct ufs_hba
*hba
);
1238 int ufshcd_make_hba_operational(struct ufs_hba
*hba
);
1239 void ufshcd_remove(struct ufs_hba
*);
1240 int ufshcd_uic_hibern8_enter(struct ufs_hba
*hba
);
1241 int ufshcd_uic_hibern8_exit(struct ufs_hba
*hba
);
1242 void ufshcd_delay_us(unsigned long us
, unsigned long tolerance
);
1243 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba
*hba
, struct clk
*refclk
);
1244 void ufshcd_update_evt_hist(struct ufs_hba
*hba
, u32 id
, u32 val
);
1245 void ufshcd_hba_stop(struct ufs_hba
*hba
);
1246 void ufshcd_schedule_eh_work(struct ufs_hba
*hba
);
1247 void ufshcd_mcq_write_cqis(struct ufs_hba
*hba
, u32 val
, int i
);
1248 unsigned long ufshcd_mcq_poll_cqe_nolock(struct ufs_hba
*hba
,
1249 struct ufs_hw_queue
*hwq
);
1250 void ufshcd_mcq_enable_esi(struct ufs_hba
*hba
);
1251 void ufshcd_mcq_config_esi(struct ufs_hba
*hba
, struct msi_msg
*msg
);
1254 * ufshcd_set_variant - set variant specific data to the hba
1255 * @hba: per adapter instance
1256 * @variant: pointer to variant specific data
1258 static inline void ufshcd_set_variant(struct ufs_hba
*hba
, void *variant
)
1261 hba
->priv
= variant
;
1265 * ufshcd_get_variant - get variant specific data from the hba
1266 * @hba: per adapter instance
1268 static inline void *ufshcd_get_variant(struct ufs_hba
*hba
)
1275 extern int ufshcd_runtime_suspend(struct device
*dev
);
1276 extern int ufshcd_runtime_resume(struct device
*dev
);
1278 #ifdef CONFIG_PM_SLEEP
1279 extern int ufshcd_system_suspend(struct device
*dev
);
1280 extern int ufshcd_system_resume(struct device
*dev
);
1281 extern int ufshcd_system_freeze(struct device
*dev
);
1282 extern int ufshcd_system_thaw(struct device
*dev
);
1283 extern int ufshcd_system_restore(struct device
*dev
);
1285 extern int ufshcd_shutdown(struct ufs_hba
*hba
);
1287 extern int ufshcd_dme_configure_adapt(struct ufs_hba
*hba
,
1290 extern int ufshcd_dme_set_attr(struct ufs_hba
*hba
, u32 attr_sel
,
1291 u8 attr_set
, u32 mib_val
, u8 peer
);
1292 extern int ufshcd_dme_get_attr(struct ufs_hba
*hba
, u32 attr_sel
,
1293 u32
*mib_val
, u8 peer
);
1294 extern int ufshcd_config_pwr_mode(struct ufs_hba
*hba
,
1295 struct ufs_pa_layer_attr
*desired_pwr_mode
);
1296 extern int ufshcd_uic_change_pwr_mode(struct ufs_hba
*hba
, u8 mode
);
1298 /* UIC command interfaces for DME primitives */
1301 #define ATTR_SET_NOR 0 /* NORMAL */
1302 #define ATTR_SET_ST 1 /* STATIC */
1304 static inline int ufshcd_dme_set(struct ufs_hba
*hba
, u32 attr_sel
,
1307 return ufshcd_dme_set_attr(hba
, attr_sel
, ATTR_SET_NOR
,
1308 mib_val
, DME_LOCAL
);
1311 static inline int ufshcd_dme_st_set(struct ufs_hba
*hba
, u32 attr_sel
,
1314 return ufshcd_dme_set_attr(hba
, attr_sel
, ATTR_SET_ST
,
1315 mib_val
, DME_LOCAL
);
1318 static inline int ufshcd_dme_peer_set(struct ufs_hba
*hba
, u32 attr_sel
,
1321 return ufshcd_dme_set_attr(hba
, attr_sel
, ATTR_SET_NOR
,
1325 static inline int ufshcd_dme_peer_st_set(struct ufs_hba
*hba
, u32 attr_sel
,
1328 return ufshcd_dme_set_attr(hba
, attr_sel
, ATTR_SET_ST
,
1332 static inline int ufshcd_dme_get(struct ufs_hba
*hba
,
1333 u32 attr_sel
, u32
*mib_val
)
1335 return ufshcd_dme_get_attr(hba
, attr_sel
, mib_val
, DME_LOCAL
);
1338 static inline int ufshcd_dme_peer_get(struct ufs_hba
*hba
,
1339 u32 attr_sel
, u32
*mib_val
)
1341 return ufshcd_dme_get_attr(hba
, attr_sel
, mib_val
, DME_PEER
);
1344 static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr
*pwr_info
)
1346 return (pwr_info
->pwr_rx
== FAST_MODE
||
1347 pwr_info
->pwr_rx
== FASTAUTO_MODE
) &&
1348 (pwr_info
->pwr_tx
== FAST_MODE
||
1349 pwr_info
->pwr_tx
== FASTAUTO_MODE
);
1352 static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba
*hba
)
1354 return ufshcd_dme_set(hba
, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE
), 0);
1357 void ufshcd_auto_hibern8_enable(struct ufs_hba
*hba
);
1358 void ufshcd_auto_hibern8_update(struct ufs_hba
*hba
, u32 ahit
);
1359 void ufshcd_fixup_dev_quirks(struct ufs_hba
*hba
,
1360 const struct ufs_dev_quirk
*fixups
);
1361 #define SD_ASCII_STD true
1362 #define SD_RAW false
1363 int ufshcd_read_string_desc(struct ufs_hba
*hba
, u8 desc_index
,
1364 u8
**buf
, bool ascii
);
1366 int ufshcd_hold(struct ufs_hba
*hba
, bool async
);
1367 void ufshcd_release(struct ufs_hba
*hba
);
1369 void ufshcd_clkgate_delay_set(struct device
*dev
, unsigned long value
);
1371 u32
ufshcd_get_local_unipro_ver(struct ufs_hba
*hba
);
1373 int ufshcd_get_vreg(struct device
*dev
, struct ufs_vreg
*vreg
);
1375 int ufshcd_send_uic_cmd(struct ufs_hba
*hba
, struct uic_command
*uic_cmd
);
1377 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba
*hba
,
1378 struct utp_upiu_req
*req_upiu
,
1379 struct utp_upiu_req
*rsp_upiu
,
1381 u8
*desc_buff
, int *buff_len
,
1382 enum query_opcode desc_op
);
1383 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba
*hba
, struct utp_upiu_req
*req_upiu
,
1384 struct utp_upiu_req
*rsp_upiu
, struct ufs_ehs
*ehs_req
,
1385 struct ufs_ehs
*ehs_rsp
, int sg_cnt
,
1386 struct scatterlist
*sg_list
, enum dma_data_direction dir
);
1387 int ufshcd_wb_toggle(struct ufs_hba
*hba
, bool enable
);
1388 int ufshcd_wb_toggle_buf_flush(struct ufs_hba
*hba
, bool enable
);
1389 int ufshcd_suspend_prepare(struct device
*dev
);
1390 int __ufshcd_suspend_prepare(struct device
*dev
, bool rpm_ok_for_spm
);
1391 void ufshcd_resume_complete(struct device
*dev
);
1393 /* Wrapper functions for safely calling variant operations */
1394 static inline int ufshcd_vops_init(struct ufs_hba
*hba
)
1396 if (hba
->vops
&& hba
->vops
->init
)
1397 return hba
->vops
->init(hba
);
1402 static inline int ufshcd_vops_phy_initialization(struct ufs_hba
*hba
)
1404 if (hba
->vops
&& hba
->vops
->phy_initialization
)
1405 return hba
->vops
->phy_initialization(hba
);
1410 extern const struct ufs_pm_lvl_states ufs_pm_lvl_states
[];
1412 int ufshcd_dump_regs(struct ufs_hba
*hba
, size_t offset
, size_t len
,
1413 const char *prefix
);
1415 int __ufshcd_write_ee_control(struct ufs_hba
*hba
, u32 ee_ctrl_mask
);
1416 int ufshcd_write_ee_control(struct ufs_hba
*hba
);
1417 int ufshcd_update_ee_control(struct ufs_hba
*hba
, u16
*mask
,
1418 const u16
*other_mask
, u16 set
, u16 clr
);
1420 #endif /* End of Header */