include/virtex2.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2002
   4  * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
   5  * Keith Outwater, keith_outwater@mvis.com
   6  */
   7
   8 #ifndef _VIRTEX2_H_
   9 #define _VIRTEX2_H_
  10
  11 #include <xilinx.h>
  12
  13 /*
  14  * Slave SelectMap or Serial Implementation function table.
  15  */
  16 typedef struct {
  17         xilinx_pre_fn   pre;
  18         xilinx_pgm_fn   pgm;
  19         xilinx_init_fn  init;
  20         xilinx_err_fn   err;
  21         xilinx_done_fn  done;
  22         xilinx_clk_fn   clk;
  23         xilinx_cs_fn    cs;
  24         xilinx_wr_fn    wr;
  25         xilinx_rdata_fn rdata;
  26         xilinx_wdata_fn wdata;
  27         xilinx_bwr_fn   wbulkdata;
  28         xilinx_busy_fn  busy;
  29         xilinx_abort_fn abort;
  30         xilinx_post_fn  post;
  31 } xilinx_virtex2_slave_fns;
  32
  33 #if defined(CONFIG_FPGA_VIRTEX2)
  34 extern struct xilinx_fpga_op virtex2_op;
  35 # define FPGA_VIRTEX2_OPS       &virtex2_op
  36 #else
  37 # define FPGA_VIRTEX2_OPS       NULL
  38 #endif
  39
  40 /* Device Image Sizes (in bytes)
  41  *********************************************************************/
  42 #define XILINX_XC2V40_SIZE      (338208 / 8)
  43 #define XILINX_XC2V80_SIZE      (597408 / 8)
  44 #define XILINX_XC2V250_SIZE     (1591584 / 8)
  45 #define XILINX_XC2V500_SIZE     (2557857 / 8)
  46 #define XILINX_XC2V1000_SIZE    (3749408 / 8)
  47 #define XILINX_XC2V1500_SIZE    (5166240 / 8)
  48 #define XILINX_XC2V2000_SIZE    (6808352 / 8)
  49 #define XILINX_XC2V3000_SIZE    (9589408 / 8)
  50 #define XILINX_XC2V4000_SIZE    (14220192 / 8)
  51 #define XILINX_XC2V6000_SIZE    (19752096 / 8)
  52 #define XILINX_XC2V8000_SIZE    (26185120 / 8)
  53 #define XILINX_XC2V10000_SIZE   (33519264 / 8)
  54
  55 /* Descriptor Macros
  56  *********************************************************************/
  57 #define XILINX_XC2V40_DESC(iface, fn_table, cookie)     \
  58 { xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \
  59         FPGA_VIRTEX2_OPS }
  60
  61 #define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
  62 { xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \
  63         FPGA_VIRTEX2_OPS }
  64
  65 #define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
  66 { xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \
  67         FPGA_VIRTEX2_OPS }
  68
  69 #define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
  70 { xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \
  71         FPGA_VIRTEX2_OPS }
  72
  73 #define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
  74 { xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \
  75         FPGA_VIRTEX2_OPS }
  76
  77 #define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
  78 { xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \
  79         FPGA_VIRTEX2_OPS }
  80
  81 #define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
  82 { xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \
  83         FPGA_VIRTEX2_OPS }
  84
  85 #define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
  86 { xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \
  87         FPGA_VIRTEX2_OPS }
  88
  89 #define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
  90 { xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \
  91         FPGA_VIRTEX2_OPS }
  92
  93 #define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
  94 { xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \
  95         FPGA_VIRTEX2_OPS }
  96
  97 #define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
  98 { xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \
  99         FPGA_VIRTEX2_OPS }
 100
 101 #define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
 102 { xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \
 103         FPGA_VIRTEX2_OPS }
 104
 105 #endif /* _VIRTEX2_H_ */