2 * Copyright 2013, 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
6 * Driver for the Vitesse VSC9953 L2 Switch
14 #include <asm/types.h>
16 #define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)
18 #define VSC9953_SYS_OFFSET 0x010000
19 #define VSC9953_REW_OFFSET 0x030000
20 #define VSC9953_DEV_GMII_OFFSET 0x100000
21 #define VSC9953_QSYS_OFFSET 0x200000
22 #define VSC9953_ANA_OFFSET 0x280000
23 #define VSC9953_DEVCPU_GCB 0x070000
24 #define VSC9953_ES0 0x040000
25 #define VSC9953_IS1 0x050000
26 #define VSC9953_IS2 0x060000
28 #define T1040_SWITCH_GMII_DEV_OFFSET 0x010000
29 #define VSC9953_PHY_REGS_OFFST 0x0000AC
31 /* Macros for vsc9953_chip_regs.soft_rst register */
32 #define VSC9953_SOFT_SWC_RST_ENA 0x00000001
34 /* Macros for vsc9953_sys_sys.reset_cfg register */
35 #define VSC9953_CORE_ENABLE 0x80
36 #define VSC9953_MEM_ENABLE 0x40
37 #define VSC9953_MEM_INIT 0x20
39 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */
40 #define VSC9953_MAC_ENA_CFG 0x00000011
42 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */
43 #define VSC9953_MAC_MODE_CFG 0x00000011
45 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */
46 #define VSC9953_MAC_IFG_CFG 0x00000515
48 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */
49 #define VSC9953_MAC_HDX_CFG 0x00001043
51 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */
52 #define VSC9953_MAC_MAX_LEN 0x000005ee
54 /* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */
55 #define VSC9953_CLOCK_CFG 0x00000001
56 #define VSC9953_CLOCK_CFG_1000M 0x00000001
58 /* Macros for vsc9953_sys_sys.front_port_mode register */
59 #define VSC9953_FRONT_PORT_MODE 0x00000000
61 /* Macros for vsc9953_ana_pfc.pfc_cfg register */
62 #define VSC9953_PFC_FC 0x00000001
63 #define VSC9953_PFC_FC_QSGMII 0x00000000
65 /* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */
66 #define VSC9953_MAC_FC_CFG 0x04700000
67 #define VSC9953_MAC_FC_CFG_QSGMII 0x00700000
69 /* Macros for vsc9953_sys_pause_cfg.pause_cfg register */
70 #define VSC9953_PAUSE_CFG 0x001ffffe
72 /* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */
73 #define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff
75 /* Macros for vsc9953_sys_sys.stat_cfg register */
76 #define VSC9953_STAT_CLEAR_RX 0x00000400
77 #define VSC9953_STAT_CLEAR_TX 0x00000800
78 #define VSC9953_STAT_CLEAR_DR 0x00001000
80 /* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */
81 #define VSC9953_VCAP_MV_CFG 0x0000ffff
82 #define VSC9953_VCAP_UPDATE_CTRL 0x01000004
84 /* Macros for register vsc9953_ana_ana_tables.mac_access register */
85 #define VSC9953_MAC_CMD_IDLE 0x00000000
86 #define VSC9953_MAC_CMD_LEARN 0x00000001
87 #define VSC9953_MAC_CMD_FORGET 0x00000002
88 #define VSC9953_MAC_CMD_AGE 0x00000003
89 #define VSC9953_MAC_CMD_NEXT 0x00000004
90 #define VSC9953_MAC_CMD_READ 0x00000006
91 #define VSC9953_MAC_CMD_WRITE 0x00000007
92 #define VSC9953_MAC_CMD_MASK 0x00000007
93 #define VSC9953_MAC_CMD_VALID 0x00000800
94 #define VSC9953_MAC_ENTRYTYPE_NORMAL 0x00000000
95 #define VSC9953_MAC_ENTRYTYPE_LOCKED 0x00000200
96 #define VSC9953_MAC_ENTRYTYPE_IPV4MCAST 0x00000400
97 #define VSC9953_MAC_ENTRYTYPE_IPV6MCAST 0x00000600
98 #define VSC9953_MAC_ENTRYTYPE_MASK 0x00000600
99 #define VSC9953_MAC_DESTIDX_MASK 0x000001f8
100 #define VSC9953_MAC_VID_MASK 0x1fff0000
101 #define VSC9953_MAC_MACH_MASK 0x0000ffff
103 /* Macros for vsc9953_ana_port.vlan_cfg register */
104 #define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000
105 #define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000
106 #define VSC9953_VLAN_CFG_POP_CNT_NONE 0x00000000
107 #define VSC9953_VLAN_CFG_POP_CNT_ONE 0x00040000
108 #define VSC9953_VLAN_CFG_VID_MASK 0x00000fff
110 /* Macros for vsc9953_rew_port.port_vlan_cfg register */
111 #define VSC9953_PORT_VLAN_CFG_VID_MASK 0x00000fff
113 /* Macros for vsc9953_ana_ana_tables.vlan_tidx register */
114 #define VSC9953_ANA_TBL_VID_MASK 0x00000fff
116 /* Macros for vsc9953_ana_ana_tables.vlan_access register */
117 #define VSC9953_VLAN_PORT_MASK 0x00001ffc
118 #define VSC9953_VLAN_CMD_MASK 0x00000003
119 #define VSC9953_VLAN_CMD_IDLE 0x00000000
120 #define VSC9953_VLAN_CMD_READ 0x00000001
121 #define VSC9953_VLAN_CMD_WRITE 0x00000002
122 #define VSC9953_VLAN_CMD_INIT 0x00000003
124 /* Macros for vsc9953_ana_port.port_cfg register */
125 #define VSC9953_PORT_CFG_LEARN_ENA 0x00000080
126 #define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100
127 #define VSC9953_PORT_CFG_LEARN_CPU 0x00000200
128 #define VSC9953_PORT_CFG_LEARN_DROP 0x00000400
129 #define VSC9953_PORT_CFG_PORTID_MASK 0x0000003c
131 /* Macros for vsc9953_qsys_sys.switch_port_mode register */
132 #define VSC9953_PORT_ENA 0x00002000
134 /* Macros for vsc9953_ana_ana.agen_ctrl register */
135 #define VSC9953_FID_MASK_ALL 0x00fff000
137 /* Macros for vsc9953_ana_ana.adv_learn register */
138 #define VSC9953_VLAN_CHK 0x00000400
140 /* Macros for vsc9953_ana_ana.auto_age register */
141 #define VSC9953_AUTOAGE_PERIOD_MASK 0x001ffffe
143 /* Macros for vsc9953_rew_port.port_tag_cfg register */
144 #define VSC9953_TAG_CFG_MASK 0x00000180
145 #define VSC9953_TAG_CFG_NONE 0x00000000
146 #define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080
147 #define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100
148 #define VSC9953_TAG_CFG_ALL 0x00000180
149 #define VSC9953_TAG_VID_PVID 0x00000010
151 /* Macros for vsc9953_ana_ana.anag_efil register */
152 #define VSC9953_AGE_PORT_EN 0x00080000
153 #define VSC9953_AGE_PORT_MASK 0x0007c000
154 #define VSC9953_AGE_VID_EN 0x00002000
155 #define VSC9953_AGE_VID_MASK 0x00001fff
157 /* Macros for vsc9953_ana_ana_tables.mach_data register */
158 #define VSC9953_MACHDATA_VID_MASK 0x1fff0000
160 /* Macros for vsc9953_ana_common.aggr_cfg register */
161 #define VSC9953_AC_RND_ENA 0x00000080
162 #define VSC9953_AC_DMAC_ENA 0x00000040
163 #define VSC9953_AC_SMAC_ENA 0x00000020
164 #define VSC9953_AC_IP6_LBL_ENA 0x00000010
165 #define VSC9953_AC_IP6_TCPUDP_ENA 0x00000008
166 #define VSC9953_AC_IP4_SIPDIP_ENA 0x00000004
167 #define VSC9953_AC_IP4_TCPUDP_ENA 0x00000002
168 #define VSC9953_AC_MASK 0x000000fe
170 /* Macros for vsc9953_ana_pgid.port_grp_id[] registers */
171 #define VSC9953_PGID_PORT_MASK 0x000003ff
173 #define VSC9953_MAX_PORTS 10
174 #define VSC9953_PORT_CHECK(port) \
175 (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
176 #define VSC9953_INTERNAL_PORT_CHECK(port) ( \
178 (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \
181 #define VSC9953_MAX_VLAN 4096
182 #define VSC9953_VLAN_CHECK(vid) \
183 (((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1)
184 #define VSC9953_DEFAULT_AGE_TIME 300
186 #define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0"
188 #define MIIMIND_OPR_PEND 0x00000004
190 struct vsc9953_mdio_info
{
191 struct vsc9953_mii_mng
*regs
;
195 /* VSC9953 ANA structure */
197 struct vsc9953_ana_port
{
202 u32 vcap_s1_key_cfg
[3];
204 u32 qos_pcp_dei_map_cfg
[16];
206 u32 cpu_fwd_bpdu_cfg
;
207 u32 cpu_fwd_garp_cfg
;
214 struct vsc9953_ana_pol
{
223 struct vsc9953_ana_ana_tables
{
234 struct vsc9953_ana_ana
{
240 u32 storm_limit_burst
;
241 u32 storm_limit_cfg
[4];
256 #define PGID_DST_START 0
257 #define PGID_AGGR_START 64
258 #define PGID_SRC_START 80
260 struct vsc9953_ana_pgid
{
264 struct vsc9953_ana_pfc
{
269 struct vsc9953_ana_pol_misc
{
275 struct vsc9953_ana_common
{
281 u32 vcap_rng_type_cfg
;
282 u32 vcap_rng_val_cfg
;
287 struct vsc9953_analyzer
{
288 struct vsc9953_ana_port port
[11];
290 struct vsc9953_ana_pol pol
[164];
291 struct vsc9953_ana_ana_tables ana_tables
;
293 struct vsc9953_ana_ana ana
;
295 struct vsc9953_ana_pgid port_id_tbl
;
297 struct vsc9953_ana_pfc pfc
[10];
298 struct vsc9953_ana_pol_misc pol_misc
;
300 struct vsc9953_ana_common common
;
302 /* END VSC9953 ANA structure t*/
304 /* VSC9953 DEV_GMII structure */
306 struct vsc9953_dev_gmii_port_mode
{
313 struct vsc9953_dev_gmii_mac_cfg_status
{
321 u32 mac_fc_mac_low_cfg
;
322 u32 mac_fc_mac_high_cfg
;
326 struct vsc9953_dev_gmii
{
327 struct vsc9953_dev_gmii_port_mode port_mode
;
328 struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status
;
331 /* END VSC9953 DEV_GMII structure */
333 /* VSC9953 QSYS structure */
335 struct vsc9953_qsys_hsch
{
344 struct vsc9953_qsys_sys
{
346 u32 switch_port_mode
[11];
358 struct vsc9953_qsys_qos_cfg
{
363 struct vsc9953_qsys_drop_cfg
{
367 struct vsc9953_qsys_mmgt
{
372 struct vsc9953_qsys_hsch_misc
{
377 struct vsc9953_qsys_res_ctrl
{
383 struct vsc9953_qsys_reg
{
384 struct vsc9953_qsys_hsch hsch
[108];
385 struct vsc9953_qsys_sys sys
;
386 struct vsc9953_qsys_qos_cfg qos_cfg
;
387 struct vsc9953_qsys_drop_cfg drop_cfg
;
388 struct vsc9953_qsys_mmgt mmgt
;
389 struct vsc9953_qsys_hsch_misc hsch_misc
;
390 struct vsc9953_qsys_res_ctrl res_ctrl
[1024];
393 /* END VSC9953 QSYS structure */
395 /* VSC9953 SYS structure */
397 struct vsc9953_rx_cntrs
{
411 u32 c_rx_sz_512_1023
;
412 u32 c_rx_sz_1024_1526
;
426 u32 c_rx_yellow_prio_0
;
427 u32 c_rx_yellow_prio_1
;
428 u32 c_rx_yellow_prio_2
;
429 u32 c_rx_yellow_prio_3
;
430 u32 c_rx_yellow_prio_4
;
431 u32 c_rx_yellow_prio_5
;
432 u32 c_rx_yellow_prio_6
;
433 u32 c_rx_yellow_prio_7
;
434 u32 c_rx_green_prio_0
;
435 u32 c_rx_green_prio_1
;
436 u32 c_rx_green_prio_2
;
437 u32 c_rx_green_prio_3
;
438 u32 c_rx_green_prio_4
;
439 u32 c_rx_green_prio_5
;
440 u32 c_rx_green_prio_6
;
441 u32 c_rx_green_prio_7
;
445 struct vsc9953_tx_cntrs
{
457 u32 c_tx_sz_512_1023
;
458 u32 c_tx_sz_1024_1526
;
460 u32 c_tx_yellow_prio_0
;
461 u32 c_tx_yellow_prio_1
;
462 u32 c_tx_yellow_prio_2
;
463 u32 c_tx_yellow_prio_3
;
464 u32 c_tx_yellow_prio_4
;
465 u32 c_tx_yellow_prio_5
;
466 u32 c_tx_yellow_prio_6
;
467 u32 c_tx_yellow_prio_7
;
468 u32 c_tx_green_prio_0
;
469 u32 c_tx_green_prio_1
;
470 u32 c_tx_green_prio_2
;
471 u32 c_tx_green_prio_3
;
472 u32 c_tx_green_prio_4
;
473 u32 c_tx_green_prio_5
;
474 u32 c_tx_green_prio_6
;
475 u32 c_tx_green_prio_7
;
480 struct vsc9953_drop_cntrs
{
483 u32 c_dr_yellow_prio_0
;
484 u32 c_dr_yellow_prio_1
;
485 u32 c_dr_yellow_prio_2
;
486 u32 c_dr_yellow_prio_3
;
487 u32 c_dr_yellow_prio_4
;
488 u32 c_dr_yellow_prio_5
;
489 u32 c_dr_yellow_prio_6
;
490 u32 c_dr_yellow_prio_7
;
491 u32 c_dr_green_prio_0
;
492 u32 c_dr_green_prio_1
;
493 u32 c_dr_green_prio_2
;
494 u32 c_dr_green_prio_3
;
495 u32 c_dr_green_prio_4
;
496 u32 c_dr_green_prio_5
;
497 u32 c_dr_green_prio_6
;
498 u32 c_dr_green_prio_7
;
502 struct vsc9953_sys_stat
{
503 struct vsc9953_rx_cntrs rx_cntrs
;
504 struct vsc9953_tx_cntrs tx_cntrs
;
505 struct vsc9953_drop_cntrs drop_cntrs
;
509 struct vsc9953_sys_sys
{
514 u32 front_port_mode
[10];
520 struct vsc9953_sys_pause_cfg
{
523 u32 tail_drop_level
[11];
524 u32 tot_tail_drop_lvl
;
528 struct vsc9953_sys_mmgt
{
532 struct vsc9953_system_reg
{
533 struct vsc9953_sys_stat stat
;
534 struct vsc9953_sys_sys sys
;
535 struct vsc9953_sys_pause_cfg pause_cfg
;
536 struct vsc9953_sys_mmgt mmgt
;
539 /* END VSC9953 SYS structure */
541 /* VSC9953 REW structure */
543 struct vsc9953_rew_port
{
548 u32 port_pcp_dei_qos_map_cfg
[16];
552 struct vsc9953_rew_common
{
554 u32 dscp_remap_dp1_cfg
[64];
555 u32 dscp_remap_cfg
[64];
558 struct vsc9953_rew_reg
{
559 struct vsc9953_rew_port port
[12];
560 struct vsc9953_rew_common common
;
563 /* END VSC9953 REW structure */
565 /* VSC9953 DEVCPU_GCB structure */
567 struct vsc9953_chip_regs
{
573 struct vsc9953_gpio
{
574 u32 gpio_out_set
[10];
575 u32 gpio_out_clr
[10];
580 struct vsc9953_mii_mng
{
588 u32 miiscan_lst_rslts
;
589 u32 miiscan_lst_rslts_valid
;
592 struct vsc9953_mii_read_scan
{
593 u32 mii_scan_results_sticky
[2];
596 struct vsc9953_devcpu_gcb
{
597 struct vsc9953_chip_regs chip_regs
;
598 struct vsc9953_gpio gpio
;
599 struct vsc9953_mii_mng mii_mng
[2];
600 struct vsc9953_mii_read_scan mii_read_scan
;
603 /* END VSC9953 DEVCPU_GCB structure */
605 /* VSC9953 IS* structure */
607 struct vsc9953_vcap_core_cfg
{
608 u32 vcap_update_ctrl
;
612 struct vsc9953_vcap
{
613 struct vsc9953_vcap_core_cfg vcap_core_cfg
;
616 /* END VSC9953 IS* structure */
618 #define VSC9953_PORT_INFO_INITIALIZER(idx) \
624 .enet_if = PHY_INTERFACE_MODE_NONE, \
629 /* Structure to describe a VSC9953 port */
630 struct vsc9953_port_info
{
635 phy_interface_t enet_if
;
637 struct phy_device
*phydev
;
640 /* Structure to describe a VSC9953 switch */
641 struct vsc9953_info
{
642 struct vsc9953_port_info port
[VSC9953_MAX_PORTS
];
645 void vsc9953_init(bd_t
*bis
);
647 void vsc9953_port_info_set_mdio(int port_no
, struct mii_dev
*bus
);
648 void vsc9953_port_info_set_phy_address(int port_no
, int address
);
649 void vsc9953_port_enable(int port_no
);
650 void vsc9953_port_disable(int port_no
);
651 void vsc9953_port_info_set_phy_int(int port_no
, phy_interface_t phy_int
);
653 #endif /* _VSC9953_H_ */