include/vsc9953.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2013, 2015 Freescale Semiconductor, Inc.
   4  *
   5  * Driver for the Vitesse VSC9953 L2 Switch
   6  */
   7
   8 #ifndef _VSC9953_H_
   9 #define _VSC9953_H_
  10
  11 #include <config.h>
  12 #include <miiphy.h>
  13 #include <asm/types.h>
  14 #include <linux/bitops.h>
  15
  16 #define VSC9953_OFFSET                  (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)
  17
  18 #define VSC9953_SYS_OFFSET              0x010000
  19 #define VSC9953_REW_OFFSET              0x030000
  20 #define VSC9953_DEV_GMII_OFFSET         0x100000
  21 #define VSC9953_QSYS_OFFSET             0x200000
  22 #define VSC9953_ANA_OFFSET              0x280000
  23 #define VSC9953_DEVCPU_GCB              0x070000
  24 #define VSC9953_ES0                     0x040000
  25 #define VSC9953_IS1                     0x050000
  26 #define VSC9953_IS2                     0x060000
  27
  28 #define T1040_SWITCH_GMII_DEV_OFFSET    0x010000
  29 #define VSC9953_PHY_REGS_OFFST          0x0000AC
  30
  31 /* Macros for vsc9953_chip_regs.soft_rst register */
  32 #define VSC9953_SOFT_SWC_RST_ENA        0x00000001
  33
  34 /* Macros for vsc9953_sys_sys.reset_cfg register */
  35 #define VSC9953_CORE_ENABLE             0x80
  36 #define VSC9953_MEM_ENABLE              0x40
  37 #define VSC9953_MEM_INIT                0x20
  38
  39 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */
  40 #define VSC9953_MAC_ENA_CFG             0x00000011
  41
  42 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */
  43 #define VSC9953_MAC_MODE_CFG            0x00000011
  44
  45 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */
  46 #define VSC9953_MAC_IFG_CFG             0x00000515
  47
  48 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */
  49 #define VSC9953_MAC_HDX_CFG             0x00001043
  50
  51 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */
  52 #define VSC9953_MAC_MAX_LEN             0x000005ee
  53
  54 /* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */
  55 #define VSC9953_CLOCK_CFG               0x00000001
  56 #define VSC9953_CLOCK_CFG_1000M         0x00000001
  57
  58 /* Macros for vsc9953_sys_sys.front_port_mode register */
  59 #define VSC9953_FRONT_PORT_MODE 0x00000000
  60
  61 /* Macros for vsc9953_ana_pfc.pfc_cfg register */
  62 #define VSC9953_PFC_FC                  0x00000001
  63 #define VSC9953_PFC_FC_QSGMII           0x00000000
  64
  65 /* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */
  66 #define VSC9953_MAC_FC_CFG              0x04700000
  67 #define VSC9953_MAC_FC_CFG_QSGMII       0x00700000
  68
  69 /* Macros for vsc9953_sys_pause_cfg.pause_cfg register */
  70 #define VSC9953_PAUSE_CFG               0x001ffffe
  71
  72 /* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */
  73 #define VSC9953_TOT_TAIL_DROP_LVL       0x000003ff
  74
  75 /* Macros for vsc9953_sys_sys.stat_cfg register */
  76 #define VSC9953_STAT_CLEAR_RX           0x00000400
  77 #define VSC9953_STAT_CLEAR_TX           0x00000800
  78 #define VSC9953_STAT_CLEAR_DR           0x00001000
  79
  80 /* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */
  81 #define VSC9953_VCAP_MV_CFG             0x0000ffff
  82 #define VSC9953_VCAP_UPDATE_CTRL        0x01000004
  83
  84 /* Macros for register vsc9953_ana_ana_tables.mac_access register */
  85 #define VSC9953_MAC_CMD_IDLE            0x00000000
  86 #define VSC9953_MAC_CMD_LEARN           0x00000001
  87 #define VSC9953_MAC_CMD_FORGET          0x00000002
  88 #define VSC9953_MAC_CMD_AGE             0x00000003
  89 #define VSC9953_MAC_CMD_NEXT            0x00000004
  90 #define VSC9953_MAC_CMD_READ            0x00000006
  91 #define VSC9953_MAC_CMD_WRITE           0x00000007
  92 #define VSC9953_MAC_CMD_MASK            0x00000007
  93 #define VSC9953_MAC_CMD_VALID           0x00000800
  94 #define VSC9953_MAC_ENTRYTYPE_NORMAL    0x00000000
  95 #define VSC9953_MAC_ENTRYTYPE_LOCKED    0x00000200
  96 #define VSC9953_MAC_ENTRYTYPE_IPV4MCAST 0x00000400
  97 #define VSC9953_MAC_ENTRYTYPE_IPV6MCAST 0x00000600
  98 #define VSC9953_MAC_ENTRYTYPE_MASK      0x00000600
  99 #define VSC9953_MAC_DESTIDX_MASK        0x000001f8
 100 #define VSC9953_MAC_VID_MASK            0x1fff0000
 101 #define VSC9953_MAC_MACH_MASK           0x0000ffff
 102
 103 /* Macros for vsc9953_ana_port.vlan_cfg register */
 104 #define VSC9953_VLAN_CFG_AWARE_ENA      0x00100000
 105 #define VSC9953_VLAN_CFG_POP_CNT_MASK   0x000c0000
 106 #define VSC9953_VLAN_CFG_POP_CNT_NONE   0x00000000
 107 #define VSC9953_VLAN_CFG_POP_CNT_ONE    0x00040000
 108 #define VSC9953_VLAN_CFG_VID_MASK       0x00000fff
 109
 110 /* Macros for vsc9953_rew_port.port_vlan_cfg register */
 111 #define VSC9953_PORT_VLAN_CFG_VID_MASK  0x00000fff
 112
 113 /* Macros for vsc9953_ana_ana_tables.vlan_tidx register */
 114 #define VSC9953_ANA_TBL_VID_MASK        0x00000fff
 115
 116 /* Macros for vsc9953_ana_ana_tables.vlan_access register */
 117 #define VSC9953_VLAN_PORT_MASK          0x00001ffc
 118 #define VSC9953_VLAN_CMD_MASK           0x00000003
 119 #define VSC9953_VLAN_CMD_IDLE           0x00000000
 120 #define VSC9953_VLAN_CMD_READ           0x00000001
 121 #define VSC9953_VLAN_CMD_WRITE          0x00000002
 122 #define VSC9953_VLAN_CMD_INIT           0x00000003
 123
 124 /* Macros for vsc9953_ana_port.port_cfg register */
 125 #define VSC9953_PORT_CFG_LEARN_ENA      0x00000080
 126 #define VSC9953_PORT_CFG_LEARN_AUTO     0x00000100
 127 #define VSC9953_PORT_CFG_LEARN_CPU      0x00000200
 128 #define VSC9953_PORT_CFG_LEARN_DROP     0x00000400
 129 #define VSC9953_PORT_CFG_PORTID_MASK    0x0000003c
 130
 131 /* Macros for vsc9953_qsys_sys.switch_port_mode register */
 132 #define VSC9953_PORT_ENA                0x00002000
 133
 134 /* Macros for vsc9953_ana_ana.agen_ctrl register */
 135 #define VSC9953_FID_MASK_ALL            0x00fff000
 136
 137 /* Macros for vsc9953_ana_ana.adv_learn register */
 138 #define VSC9953_VLAN_CHK                0x00000400
 139
 140 /* Macros for vsc9953_ana_ana.auto_age register */
 141 #define VSC9953_AUTOAGE_PERIOD_MASK     0x001ffffe
 142
 143 /* Macros for vsc9953_rew_port.port_tag_cfg register */
 144 #define VSC9953_TAG_CFG_MASK            0x00000180
 145 #define VSC9953_TAG_CFG_NONE            0x00000000
 146 #define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO       0x00000080
 147 #define VSC9953_TAG_CFG_ALL_BUT_ZERO            0x00000100
 148 #define VSC9953_TAG_CFG_ALL             0x00000180
 149 #define VSC9953_TAG_VID_PVID            0x00000010
 150
 151 /* Macros for vsc9953_ana_ana.anag_efil register */
 152 #define VSC9953_AGE_PORT_EN             0x00080000
 153 #define VSC9953_AGE_PORT_MASK           0x0007c000
 154 #define VSC9953_AGE_VID_EN              0x00002000
 155 #define VSC9953_AGE_VID_MASK            0x00001fff
 156
 157 /* Macros for vsc9953_ana_ana_tables.mach_data register */
 158 #define VSC9953_MACHDATA_VID_MASK       0x1fff0000
 159
 160 /* Macros for vsc9953_ana_common.aggr_cfg register */
 161 #define VSC9953_AC_RND_ENA              0x00000080
 162 #define VSC9953_AC_DMAC_ENA             0x00000040
 163 #define VSC9953_AC_SMAC_ENA             0x00000020
 164 #define VSC9953_AC_IP6_LBL_ENA          0x00000010
 165 #define VSC9953_AC_IP6_TCPUDP_ENA       0x00000008
 166 #define VSC9953_AC_IP4_SIPDIP_ENA       0x00000004
 167 #define VSC9953_AC_IP4_TCPUDP_ENA       0x00000002
 168 #define VSC9953_AC_MASK                 0x000000fe
 169
 170 /* Macros for vsc9953_ana_pgid.port_grp_id[] registers */
 171 #define VSC9953_PGID_PORT_MASK          0x000003ff
 172
 173 #define VSC9953_MAX_PORTS               10
 174 #define VSC9953_PORT_CHECK(port)        \
 175         (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
 176 #define VSC9953_INTERNAL_PORT_CHECK(port) ( \
 177         ( \
 178                 (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \
 179         ) ? 0 : 1 \
 180 )
 181 #define VSC9953_MAX_VLAN                4096
 182 #define VSC9953_VLAN_CHECK(vid) \
 183         (((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1)
 184 #define VSC9953_DEFAULT_AGE_TIME        300
 185
 186 #define DEFAULT_VSC9953_MDIO_NAME       "VSC9953_MDIO0"
 187
 188 #define MIIMIND_OPR_PEND                0x00000004
 189
 190 #define VSC9953_BITMASK(offset)         ((BIT(offset)) - 1)
 191 #define VSC9953_ENC_BITFIELD(target, offset, width) \
 192         (((target) & VSC9953_BITMASK(width)) << (offset))
 193
 194 #define VSC9953_IO_ADDR(target, offset)         ((target) + (offset << 2))
 195
 196 #define VSC9953_IO_REG(target, offset)  (VSC9953_IO_ADDR(target, offset))
 197 #define VSC9953_VCAP_CACHE_ENTRY_DAT(target, ri)  \
 198         VSC9953_IO_REG(target, (0x2 + (ri)))
 199
 200 #define VSC9953_VCAP_CACHE_MASK_DAT(target, ri) \
 201         VSC9953_IO_REG(target, (0x42 + (ri)))
 202
 203 #define VSC9953_VCAP_CACHE_TG_DAT(target)       VSC9953_IO_REG(target, 0xe2)
 204 #define VSC9953_VCAP_CFG_MV_CFG(target) VSC9953_IO_REG(target, 0x1)
 205 #define VSC9953_VCAP_CFG_MV_CFG_SIZE(target) \
 206         VSC9953_ENC_BITFIELD(target, 0, 16)
 207
 208 #define VSC9953_VCAP_CFG_UPDATE_CTRL(target)    VSC9953_IO_REG(target, 0x0)
 209 #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_CMD(target) \
 210         VSC9953_ENC_BITFIELD(target, 22, 3)
 211
 212 #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ADDR(target) \
 213         VSC9953_ENC_BITFIELD(target, 3, 16)
 214
 215 #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_SHOT    BIT(2)
 216 #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS       BIT(21)
 217 #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS      BIT(20)
 218 #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_CNT_DIS         BIT(19)
 219 #define VSC9953_VCAP_CACHE_ACTION_DAT(target, ri) \
 220         VSC9953_IO_REG(target, (0x82 + (ri)))
 221
 222 #define VSC9953_VCAP_CACHE_CNT_DAT(target, ri)  \
 223         VSC9953_IO_REG(target, (0xc2 + (ri)))
 224
 225 #define VSC9953_PORT_OFFSET             1
 226 #define VSC9953_IS1_CNT                 256
 227 #define VSC9953_IS2_CNT                 1024
 228 #define VSC9953_ES0_CNT                 1024
 229
 230 #define BITS_TO_DWORD(in)               (1 + (((in) - 1) / 32))
 231 #define ENTRY_WORDS_ES0         BITS_TO_DWORD(29)
 232 #define ENTRY_WORDS_IS1         BITS_TO_DWORD(376)
 233 #define ENTRY_WORDS_IS2         BITS_TO_DWORD(376)
 234 #define ES0_ACT_WIDTH           BITS_TO_DWORD(91)
 235 #define ES0_CNT_WIDTH           BITS_TO_DWORD(1)
 236 #define IS1_ACT_WIDTH           BITS_TO_DWORD(320)
 237 #define IS1_CNT_WIDTH           BITS_TO_DWORD(4)
 238 #define IS2_ACT_WIDTH           BITS_TO_DWORD(103 - 2 * VSC9953_PORT_OFFSET)
 239 #define IS2_CNT_WIDTH           BITS_TO_DWORD(4 * 32)
 240 #define ES0_ACT_COUNT           (VSC9953_ES0_CNT + VSC9953_MAX_PORTS)
 241 #define IS1_ACT_COUNT           (VSC9953_IS1_CNT + 1)
 242 #define IS2_ACT_COUNT           (VSC9953_IS2_CNT + VSC9953_MAX_PORTS + 2)
 243
 244 /* TCAM entries */
 245 enum tcam_sel {
 246         TCAM_SEL_ENTRY   = BIT(0),
 247         TCAM_SEL_ACTION  = BIT(1),
 248         TCAM_SEL_COUNTER = BIT(2),
 249         TCAM_SEL_ALL     = VSC9953_BITMASK(3),
 250 };
 251
 252 enum tcam_cmd {
 253         TCAM_CMD_WRITE      = 0,
 254         TCAM_CMD_READ       = 1,
 255         TCAM_CMD_MOVE_UP    = 2,
 256         TCAM_CMD_MOVE_DOWN  = 3,
 257         TCAM_CMD_INITIALIZE = 4,
 258 };
 259
 260 struct vsc9953_mdio_info {
 261         struct vsc9953_mii_mng  *regs;
 262         char    *name;
 263 };
 264
 265 /* VSC9953 ANA structure */
 266
 267 struct vsc9953_ana_port {
 268         u32     vlan_cfg;
 269         u32     drop_cfg;
 270         u32     qos_cfg;
 271         u32     vcap_cfg;
 272         u32     vcap_s1_key_cfg[3];
 273         u32     vcap_s2_cfg;
 274         u32     qos_pcp_dei_map_cfg[16];
 275         u32     cpu_fwd_cfg;
 276         u32     cpu_fwd_bpdu_cfg;
 277         u32     cpu_fwd_garp_cfg;
 278         u32     cpu_fwd_ccm_cfg;
 279         u32     port_cfg;
 280         u32     pol_cfg;
 281         u32     reserved[34];
 282 };
 283
 284 struct vsc9953_ana_pol {
 285         u32     pol_pir_cfg;
 286         u32     pol_cir_cfg;
 287         u32     pol_mode_cfg;
 288         u32     pol_pir_state;
 289         u32     pol_cir_state;
 290         u32     reserved1[3];
 291 };
 292
 293 struct vsc9953_ana_ana_tables {
 294         u32     entry_lim[11];
 295         u32     an_moved;
 296         u32     mach_data;
 297         u32     macl_data;
 298         u32     mac_access;
 299         u32     mact_indx;
 300         u32     vlan_access;
 301         u32     vlan_tidx;
 302 };
 303
 304 struct vsc9953_ana_ana {
 305         u32     adv_learn;
 306         u32     vlan_mask;
 307         u32     reserved;
 308         u32     anag_efil;
 309         u32     an_events;
 310         u32     storm_limit_burst;
 311         u32     storm_limit_cfg[4];
 312         u32     isolated_prts;
 313         u32     community_ports;
 314         u32     auto_age;
 315         u32     mac_options;
 316         u32     learn_disc;
 317         u32     agen_ctrl;
 318         u32     mirror_ports;
 319         u32     emirror_ports;
 320         u32     flooding;
 321         u32     flooding_ipmc;
 322         u32     sflow_cfg[11];
 323         u32     port_mode[12];
 324 };
 325
 326 #define PGID_DST_START          0
 327 #define PGID_AGGR_START         64
 328 #define PGID_SRC_START          80
 329
 330 struct vsc9953_ana_pgid {
 331         u32     port_grp_id[91];
 332 };
 333
 334 struct vsc9953_ana_pfc {
 335         u32     pfc_cfg;
 336         u32     reserved1[15];
 337 };
 338
 339 struct vsc9953_ana_pol_misc {
 340         u32     pol_flowc[10];
 341         u32     reserved1[17];
 342         u32     pol_hyst;
 343 };
 344
 345 struct vsc9953_ana_common {
 346         u32     aggr_cfg;
 347         u32     cpuq_cfg;
 348         u32     cpuq_8021_cfg;
 349         u32     dscp_cfg;
 350         u32     dscp_rewr_cfg;
 351         u32     vcap_rng_type_cfg;
 352         u32     vcap_rng_val_cfg;
 353         u32     discard_cfg;
 354         u32     fid_cfg;
 355 };
 356
 357 struct vsc9953_analyzer {
 358         struct vsc9953_ana_port port[11];
 359         u32     reserved1[9536];
 360         struct vsc9953_ana_pol  pol[164];
 361         struct vsc9953_ana_ana_tables   ana_tables;
 362         u32     reserved2[14];
 363         struct vsc9953_ana_ana  ana;
 364         u32     reserved3[21];
 365         struct vsc9953_ana_pgid port_id_tbl;
 366         u32     reserved4[549];
 367         struct vsc9953_ana_pfc  pfc[10];
 368         struct vsc9953_ana_pol_misc     pol_misc;
 369         u32     reserved5[196];
 370         struct vsc9953_ana_common       common;
 371 };
 372 /* END VSC9953 ANA structure t*/
 373
 374 /* VSC9953 DEV_GMII structure */
 375
 376 struct vsc9953_dev_gmii_port_mode {
 377         u32     clock_cfg;
 378         u32     port_misc;
 379         u32     reserved1;
 380         u32     eee_cfg;
 381 };
 382
 383 struct vsc9953_dev_gmii_mac_cfg_status {
 384         u32     mac_ena_cfg;
 385         u32     mac_mode_cfg;
 386         u32     mac_maxlen_cfg;
 387         u32     mac_tags_cfg;
 388         u32     mac_adv_chk_cfg;
 389         u32     mac_ifg_cfg;
 390         u32     mac_hdx_cfg;
 391         u32     mac_fc_mac_low_cfg;
 392         u32     mac_fc_mac_high_cfg;
 393         u32     mac_sticky;
 394 };
 395
 396 struct vsc9953_dev_gmii {
 397         struct vsc9953_dev_gmii_port_mode       port_mode;
 398         struct vsc9953_dev_gmii_mac_cfg_status  mac_cfg_status;
 399 };
 400
 401 /* END VSC9953 DEV_GMII structure */
 402
 403 /* VSC9953 QSYS structure */
 404
 405 struct vsc9953_qsys_hsch {
 406         u32     cir_cfg;
 407         u32     reserved1;
 408         u32     se_cfg;
 409         u32     se_dwrr_cfg[8];
 410         u32     cir_state;
 411         u32     reserved2[20];
 412 };
 413
 414 struct vsc9953_qsys_sys {
 415         u32     port_mode[12];
 416         u32     switch_port_mode[11];
 417         u32     stat_cnt_cfg;
 418         u32     eee_cfg[10];
 419         u32     eee_thrs;
 420         u32     igr_no_sharing;
 421         u32     egr_no_sharing;
 422         u32     sw_status[11];
 423         u32     ext_cpu_cfg;
 424         u32     cpu_group_map;
 425         u32     reserved1[23];
 426 };
 427
 428 struct vsc9953_qsys_qos_cfg {
 429         u32     red_profile[16];
 430         u32     res_qos_mode;
 431 };
 432
 433 struct vsc9953_qsys_drop_cfg {
 434         u32     egr_drop_mode;
 435 };
 436
 437 struct vsc9953_qsys_mmgt {
 438         u32     eq_cntrl;
 439         u32     reserved1;
 440 };
 441
 442 struct vsc9953_qsys_hsch_misc {
 443         u32     hsch_misc_cfg;
 444         u32     reserved1[546];
 445 };
 446
 447 struct vsc9953_qsys_res_ctrl {
 448         u32     res_cfg;
 449         u32     res_stat;
 450
 451 };
 452
 453 struct vsc9953_qsys_reg {
 454         struct vsc9953_qsys_hsch        hsch[108];
 455         struct vsc9953_qsys_sys sys;
 456         struct vsc9953_qsys_qos_cfg     qos_cfg;
 457         struct vsc9953_qsys_drop_cfg    drop_cfg;
 458         struct vsc9953_qsys_mmgt        mmgt;
 459         struct vsc9953_qsys_hsch_misc   hsch_misc;
 460         struct vsc9953_qsys_res_ctrl    res_ctrl[1024];
 461 };
 462
 463 /* END VSC9953 QSYS structure */
 464
 465 /* VSC9953 SYS structure */
 466
 467 struct vsc9953_rx_cntrs {
 468         u32     c_rx_oct;
 469         u32     c_rx_uc;
 470         u32     c_rx_mc;
 471         u32     c_rx_bc;
 472         u32     c_rx_short;
 473         u32     c_rx_frag;
 474         u32     c_rx_jabber;
 475         u32     c_rx_crc;
 476         u32     c_rx_symbol_err;
 477         u32     c_rx_sz_64;
 478         u32     c_rx_sz_65_127;
 479         u32     c_rx_sz_128_255;
 480         u32     c_rx_sz_256_511;
 481         u32     c_rx_sz_512_1023;
 482         u32     c_rx_sz_1024_1526;
 483         u32     c_rx_sz_jumbo;
 484         u32     c_rx_pause;
 485         u32     c_rx_control;
 486         u32     c_rx_long;
 487         u32     c_rx_cat_drop;
 488         u32     c_rx_red_prio_0;
 489         u32     c_rx_red_prio_1;
 490         u32     c_rx_red_prio_2;
 491         u32     c_rx_red_prio_3;
 492         u32     c_rx_red_prio_4;
 493         u32     c_rx_red_prio_5;
 494         u32     c_rx_red_prio_6;
 495         u32     c_rx_red_prio_7;
 496         u32     c_rx_yellow_prio_0;
 497         u32     c_rx_yellow_prio_1;
 498         u32     c_rx_yellow_prio_2;
 499         u32     c_rx_yellow_prio_3;
 500         u32     c_rx_yellow_prio_4;
 501         u32     c_rx_yellow_prio_5;
 502         u32     c_rx_yellow_prio_6;
 503         u32     c_rx_yellow_prio_7;
 504         u32     c_rx_green_prio_0;
 505         u32     c_rx_green_prio_1;
 506         u32     c_rx_green_prio_2;
 507         u32     c_rx_green_prio_3;
 508         u32     c_rx_green_prio_4;
 509         u32     c_rx_green_prio_5;
 510         u32     c_rx_green_prio_6;
 511         u32     c_rx_green_prio_7;
 512         u32     reserved[20];
 513 };
 514
 515 struct vsc9953_tx_cntrs {
 516         u32     c_tx_oct;
 517         u32     c_tx_uc;
 518         u32     c_tx_mc;
 519         u32     c_tx_bc;
 520         u32     c_tx_col;
 521         u32     c_tx_drop;
 522         u32     c_tx_pause;
 523         u32     c_tx_sz_64;
 524         u32     c_tx_sz_65_127;
 525         u32     c_tx_sz_128_255;
 526         u32     c_tx_sz_256_511;
 527         u32     c_tx_sz_512_1023;
 528         u32     c_tx_sz_1024_1526;
 529         u32     c_tx_sz_jumbo;
 530         u32     c_tx_yellow_prio_0;
 531         u32     c_tx_yellow_prio_1;
 532         u32     c_tx_yellow_prio_2;
 533         u32     c_tx_yellow_prio_3;
 534         u32     c_tx_yellow_prio_4;
 535         u32     c_tx_yellow_prio_5;
 536         u32     c_tx_yellow_prio_6;
 537         u32     c_tx_yellow_prio_7;
 538         u32     c_tx_green_prio_0;
 539         u32     c_tx_green_prio_1;
 540         u32     c_tx_green_prio_2;
 541         u32     c_tx_green_prio_3;
 542         u32     c_tx_green_prio_4;
 543         u32     c_tx_green_prio_5;
 544         u32     c_tx_green_prio_6;
 545         u32     c_tx_green_prio_7;
 546         u32     c_tx_aged;
 547         u32     reserved[33];
 548 };
 549
 550 struct vsc9953_drop_cntrs {
 551         u32     c_dr_local;
 552         u32     c_dr_tail;
 553         u32     c_dr_yellow_prio_0;
 554         u32     c_dr_yellow_prio_1;
 555         u32     c_dr_yellow_prio_2;
 556         u32     c_dr_yellow_prio_3;
 557         u32     c_dr_yellow_prio_4;
 558         u32     c_dr_yellow_prio_5;
 559         u32     c_dr_yellow_prio_6;
 560         u32     c_dr_yellow_prio_7;
 561         u32     c_dr_green_prio_0;
 562         u32     c_dr_green_prio_1;
 563         u32     c_dr_green_prio_2;
 564         u32     c_dr_green_prio_3;
 565         u32     c_dr_green_prio_4;
 566         u32     c_dr_green_prio_5;
 567         u32     c_dr_green_prio_6;
 568         u32     c_dr_green_prio_7;
 569         u32     reserved[46];
 570 };
 571
 572 struct vsc9953_sys_stat {
 573         struct vsc9953_rx_cntrs rx_cntrs;
 574         struct vsc9953_tx_cntrs tx_cntrs;
 575         struct vsc9953_drop_cntrs       drop_cntrs;
 576         u32     reserved1[6];
 577 };
 578
 579 struct vsc9953_sys_sys {
 580         u32     reset_cfg;
 581         u32     reserved1;
 582         u32     vlan_etype_cfg;
 583         u32     port_mode[12];
 584         u32     front_port_mode[10];
 585         u32     frame_aging;
 586         u32     stat_cfg;
 587         u32     reserved2[50];
 588 };
 589
 590 struct vsc9953_sys_pause_cfg {
 591         u32     pause_cfg[11];
 592         u32     pause_tot_cfg;
 593         u32     tail_drop_level[11];
 594         u32     tot_tail_drop_lvl;
 595         u32     mac_fc_cfg[10];
 596 };
 597
 598 struct vsc9953_sys_mmgt {
 599         u16     free_cnt;
 600 };
 601
 602 struct vsc9953_system_reg {
 603         struct vsc9953_sys_stat stat;
 604         struct vsc9953_sys_sys  sys;
 605         struct vsc9953_sys_pause_cfg    pause_cfg;
 606         struct vsc9953_sys_mmgt mmgt;
 607 };
 608
 609 /* END VSC9953 SYS structure */
 610
 611 /* VSC9953 REW structure */
 612
 613 struct  vsc9953_rew_port {
 614         u32     port_vlan_cfg;
 615         u32     port_tag_cfg;
 616         u32     port_port_cfg;
 617         u32     port_dscp_cfg;
 618         u32     port_pcp_dei_qos_map_cfg[16];
 619         u32     reserved[12];
 620 };
 621
 622 struct  vsc9953_rew_common {
 623         u32     reserve[4];
 624         u32     dscp_remap_dp1_cfg[64];
 625         u32     dscp_remap_cfg[64];
 626 };
 627
 628 struct  vsc9953_rew_reg {
 629         struct vsc9953_rew_port port[12];
 630         struct vsc9953_rew_common       common;
 631 };
 632
 633 /* END VSC9953 REW structure */
 634
 635 /* VSC9953 DEVCPU_GCB structure */
 636
 637 struct vsc9953_chip_regs {
 638         u32     chipd_id;
 639         u32     gpr;
 640         u32     soft_rst;
 641 };
 642
 643 struct vsc9953_gpio {
 644         u32     gpio_out_set[10];
 645         u32     gpio_out_clr[10];
 646         u32     gpio_out[10];
 647         u32     gpio_in[10];
 648 };
 649
 650 struct vsc9953_mii_mng {
 651         u32     miimstatus;
 652         u32     reserved1;
 653         u32     miimcmd;
 654         u32     miimdata;
 655         u32     miimcfg;
 656         u32     miimscan_0;
 657         u32     miimscan_1;
 658         u32     miiscan_lst_rslts;
 659         u32     miiscan_lst_rslts_valid;
 660 };
 661
 662 struct vsc9953_mii_read_scan {
 663         u32     mii_scan_results_sticky[2];
 664 };
 665
 666 struct vsc9953_devcpu_gcb {
 667         struct vsc9953_chip_regs        chip_regs;
 668         struct vsc9953_gpio             gpio;
 669         struct vsc9953_mii_mng  mii_mng[2];
 670         struct vsc9953_mii_read_scan    mii_read_scan;
 671 };
 672
 673 /* END VSC9953 DEVCPU_GCB structure */
 674
 675 /* VSC9953 IS* structure */
 676
 677 struct vsc9953_vcap_core_cfg {
 678         u32     vcap_update_ctrl;
 679         u32     vcap_mv_cfg;
 680 };
 681
 682 struct vsc9953_vcap {
 683         struct vsc9953_vcap_core_cfg    vcap_core_cfg;
 684 };
 685
 686 /* END VSC9953 IS* structure */
 687
 688 #define VSC9953_PORT_INFO_INITIALIZER(idx) \
 689 {                                                                       \
 690         .enabled        = 0,                                            \
 691         .phyaddr        = 0,                                            \
 692         .index          = idx,                                          \
 693         .phy_regs       = NULL,                                         \
 694         .enet_if        = PHY_INTERFACE_MODE_NA,                        \
 695         .bus            = NULL,                                         \
 696         .phydev         = NULL,                                         \
 697 }
 698
 699 /* Structure to describe a VSC9953 port */
 700 struct vsc9953_port_info {
 701         u8      enabled;
 702         u8      phyaddr;
 703         int     index;
 704         void    *phy_regs;
 705         phy_interface_t enet_if;
 706         struct mii_dev  *bus;
 707         struct phy_device       *phydev;
 708 };
 709
 710 /* Structure to describe a VSC9953 switch */
 711 struct vsc9953_info {
 712         struct vsc9953_port_info        port[VSC9953_MAX_PORTS];
 713 };
 714
 715 void vsc9953_init(struct bd_info *bis);
 716
 717 void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus);
 718 void vsc9953_port_info_set_phy_address(int port_no, int address);
 719 void vsc9953_port_enable(int port_no);
 720 void vsc9953_port_disable(int port_no);
 721 void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int);
 722
 723 #endif /* _VSC9953_H_ */