1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2013, 2015 Freescale Semiconductor, Inc.
5 * Driver for the Vitesse VSC9953 L2 Switch
13 #include <asm/types.h>
15 #define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)
17 #define VSC9953_SYS_OFFSET 0x010000
18 #define VSC9953_REW_OFFSET 0x030000
19 #define VSC9953_DEV_GMII_OFFSET 0x100000
20 #define VSC9953_QSYS_OFFSET 0x200000
21 #define VSC9953_ANA_OFFSET 0x280000
22 #define VSC9953_DEVCPU_GCB 0x070000
23 #define VSC9953_ES0 0x040000
24 #define VSC9953_IS1 0x050000
25 #define VSC9953_IS2 0x060000
27 #define T1040_SWITCH_GMII_DEV_OFFSET 0x010000
28 #define VSC9953_PHY_REGS_OFFST 0x0000AC
30 /* Macros for vsc9953_chip_regs.soft_rst register */
31 #define VSC9953_SOFT_SWC_RST_ENA 0x00000001
33 /* Macros for vsc9953_sys_sys.reset_cfg register */
34 #define VSC9953_CORE_ENABLE 0x80
35 #define VSC9953_MEM_ENABLE 0x40
36 #define VSC9953_MEM_INIT 0x20
38 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */
39 #define VSC9953_MAC_ENA_CFG 0x00000011
41 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */
42 #define VSC9953_MAC_MODE_CFG 0x00000011
44 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */
45 #define VSC9953_MAC_IFG_CFG 0x00000515
47 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */
48 #define VSC9953_MAC_HDX_CFG 0x00001043
50 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */
51 #define VSC9953_MAC_MAX_LEN 0x000005ee
53 /* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */
54 #define VSC9953_CLOCK_CFG 0x00000001
55 #define VSC9953_CLOCK_CFG_1000M 0x00000001
57 /* Macros for vsc9953_sys_sys.front_port_mode register */
58 #define VSC9953_FRONT_PORT_MODE 0x00000000
60 /* Macros for vsc9953_ana_pfc.pfc_cfg register */
61 #define VSC9953_PFC_FC 0x00000001
62 #define VSC9953_PFC_FC_QSGMII 0x00000000
64 /* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */
65 #define VSC9953_MAC_FC_CFG 0x04700000
66 #define VSC9953_MAC_FC_CFG_QSGMII 0x00700000
68 /* Macros for vsc9953_sys_pause_cfg.pause_cfg register */
69 #define VSC9953_PAUSE_CFG 0x001ffffe
71 /* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */
72 #define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff
74 /* Macros for vsc9953_sys_sys.stat_cfg register */
75 #define VSC9953_STAT_CLEAR_RX 0x00000400
76 #define VSC9953_STAT_CLEAR_TX 0x00000800
77 #define VSC9953_STAT_CLEAR_DR 0x00001000
79 /* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */
80 #define VSC9953_VCAP_MV_CFG 0x0000ffff
81 #define VSC9953_VCAP_UPDATE_CTRL 0x01000004
83 /* Macros for register vsc9953_ana_ana_tables.mac_access register */
84 #define VSC9953_MAC_CMD_IDLE 0x00000000
85 #define VSC9953_MAC_CMD_LEARN 0x00000001
86 #define VSC9953_MAC_CMD_FORGET 0x00000002
87 #define VSC9953_MAC_CMD_AGE 0x00000003
88 #define VSC9953_MAC_CMD_NEXT 0x00000004
89 #define VSC9953_MAC_CMD_READ 0x00000006
90 #define VSC9953_MAC_CMD_WRITE 0x00000007
91 #define VSC9953_MAC_CMD_MASK 0x00000007
92 #define VSC9953_MAC_CMD_VALID 0x00000800
93 #define VSC9953_MAC_ENTRYTYPE_NORMAL 0x00000000
94 #define VSC9953_MAC_ENTRYTYPE_LOCKED 0x00000200
95 #define VSC9953_MAC_ENTRYTYPE_IPV4MCAST 0x00000400
96 #define VSC9953_MAC_ENTRYTYPE_IPV6MCAST 0x00000600
97 #define VSC9953_MAC_ENTRYTYPE_MASK 0x00000600
98 #define VSC9953_MAC_DESTIDX_MASK 0x000001f8
99 #define VSC9953_MAC_VID_MASK 0x1fff0000
100 #define VSC9953_MAC_MACH_MASK 0x0000ffff
102 /* Macros for vsc9953_ana_port.vlan_cfg register */
103 #define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000
104 #define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000
105 #define VSC9953_VLAN_CFG_POP_CNT_NONE 0x00000000
106 #define VSC9953_VLAN_CFG_POP_CNT_ONE 0x00040000
107 #define VSC9953_VLAN_CFG_VID_MASK 0x00000fff
109 /* Macros for vsc9953_rew_port.port_vlan_cfg register */
110 #define VSC9953_PORT_VLAN_CFG_VID_MASK 0x00000fff
112 /* Macros for vsc9953_ana_ana_tables.vlan_tidx register */
113 #define VSC9953_ANA_TBL_VID_MASK 0x00000fff
115 /* Macros for vsc9953_ana_ana_tables.vlan_access register */
116 #define VSC9953_VLAN_PORT_MASK 0x00001ffc
117 #define VSC9953_VLAN_CMD_MASK 0x00000003
118 #define VSC9953_VLAN_CMD_IDLE 0x00000000
119 #define VSC9953_VLAN_CMD_READ 0x00000001
120 #define VSC9953_VLAN_CMD_WRITE 0x00000002
121 #define VSC9953_VLAN_CMD_INIT 0x00000003
123 /* Macros for vsc9953_ana_port.port_cfg register */
124 #define VSC9953_PORT_CFG_LEARN_ENA 0x00000080
125 #define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100
126 #define VSC9953_PORT_CFG_LEARN_CPU 0x00000200
127 #define VSC9953_PORT_CFG_LEARN_DROP 0x00000400
128 #define VSC9953_PORT_CFG_PORTID_MASK 0x0000003c
130 /* Macros for vsc9953_qsys_sys.switch_port_mode register */
131 #define VSC9953_PORT_ENA 0x00002000
133 /* Macros for vsc9953_ana_ana.agen_ctrl register */
134 #define VSC9953_FID_MASK_ALL 0x00fff000
136 /* Macros for vsc9953_ana_ana.adv_learn register */
137 #define VSC9953_VLAN_CHK 0x00000400
139 /* Macros for vsc9953_ana_ana.auto_age register */
140 #define VSC9953_AUTOAGE_PERIOD_MASK 0x001ffffe
142 /* Macros for vsc9953_rew_port.port_tag_cfg register */
143 #define VSC9953_TAG_CFG_MASK 0x00000180
144 #define VSC9953_TAG_CFG_NONE 0x00000000
145 #define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080
146 #define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100
147 #define VSC9953_TAG_CFG_ALL 0x00000180
148 #define VSC9953_TAG_VID_PVID 0x00000010
150 /* Macros for vsc9953_ana_ana.anag_efil register */
151 #define VSC9953_AGE_PORT_EN 0x00080000
152 #define VSC9953_AGE_PORT_MASK 0x0007c000
153 #define VSC9953_AGE_VID_EN 0x00002000
154 #define VSC9953_AGE_VID_MASK 0x00001fff
156 /* Macros for vsc9953_ana_ana_tables.mach_data register */
157 #define VSC9953_MACHDATA_VID_MASK 0x1fff0000
159 /* Macros for vsc9953_ana_common.aggr_cfg register */
160 #define VSC9953_AC_RND_ENA 0x00000080
161 #define VSC9953_AC_DMAC_ENA 0x00000040
162 #define VSC9953_AC_SMAC_ENA 0x00000020
163 #define VSC9953_AC_IP6_LBL_ENA 0x00000010
164 #define VSC9953_AC_IP6_TCPUDP_ENA 0x00000008
165 #define VSC9953_AC_IP4_SIPDIP_ENA 0x00000004
166 #define VSC9953_AC_IP4_TCPUDP_ENA 0x00000002
167 #define VSC9953_AC_MASK 0x000000fe
169 /* Macros for vsc9953_ana_pgid.port_grp_id[] registers */
170 #define VSC9953_PGID_PORT_MASK 0x000003ff
172 #define VSC9953_MAX_PORTS 10
173 #define VSC9953_PORT_CHECK(port) \
174 (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
175 #define VSC9953_INTERNAL_PORT_CHECK(port) ( \
177 (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \
180 #define VSC9953_MAX_VLAN 4096
181 #define VSC9953_VLAN_CHECK(vid) \
182 (((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1)
183 #define VSC9953_DEFAULT_AGE_TIME 300
185 #define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0"
187 #define MIIMIND_OPR_PEND 0x00000004
189 #define VSC9953_BITMASK(offset) ((BIT(offset)) - 1)
190 #define VSC9953_ENC_BITFIELD(target, offset, width) \
191 (((target) & VSC9953_BITMASK(width)) << (offset))
193 #define VSC9953_IO_ADDR(target, offset) ((target) + (offset << 2))
195 #define VSC9953_IO_REG(target, offset) (VSC9953_IO_ADDR(target, offset))
196 #define VSC9953_VCAP_CACHE_ENTRY_DAT(target, ri) \
197 VSC9953_IO_REG(target, (0x2 + (ri)))
199 #define VSC9953_VCAP_CACHE_MASK_DAT(target, ri) \
200 VSC9953_IO_REG(target, (0x42 + (ri)))
202 #define VSC9953_VCAP_CACHE_TG_DAT(target) VSC9953_IO_REG(target, 0xe2)
203 #define VSC9953_VCAP_CFG_MV_CFG(target) VSC9953_IO_REG(target, 0x1)
204 #define VSC9953_VCAP_CFG_MV_CFG_SIZE(target) \
205 VSC9953_ENC_BITFIELD(target, 0, 16)
207 #define VSC9953_VCAP_CFG_UPDATE_CTRL(target) VSC9953_IO_REG(target, 0x0)
208 #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_CMD(target) \
209 VSC9953_ENC_BITFIELD(target, 22, 3)
211 #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ADDR(target) \
212 VSC9953_ENC_BITFIELD(target, 3, 16)
214 #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_SHOT BIT(2)
215 #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21)
216 #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20)
217 #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19)
218 #define VSC9953_VCAP_CACHE_ACTION_DAT(target, ri) \
219 VSC9953_IO_REG(target, (0x82 + (ri)))
221 #define VSC9953_VCAP_CACHE_CNT_DAT(target, ri) \
222 VSC9953_IO_REG(target, (0xc2 + (ri)))
224 #define VSC9953_PORT_OFFSET 1
225 #define VSC9953_IS1_CNT 256
226 #define VSC9953_IS2_CNT 1024
227 #define VSC9953_ES0_CNT 1024
229 #define BITS_TO_DWORD(in) (1 + (((in) - 1) / 32))
230 #define ENTRY_WORDS_ES0 BITS_TO_DWORD(29)
231 #define ENTRY_WORDS_IS1 BITS_TO_DWORD(376)
232 #define ENTRY_WORDS_IS2 BITS_TO_DWORD(376)
233 #define ES0_ACT_WIDTH BITS_TO_DWORD(91)
234 #define ES0_CNT_WIDTH BITS_TO_DWORD(1)
235 #define IS1_ACT_WIDTH BITS_TO_DWORD(320)
236 #define IS1_CNT_WIDTH BITS_TO_DWORD(4)
237 #define IS2_ACT_WIDTH BITS_TO_DWORD(103 - 2 * VSC9953_PORT_OFFSET)
238 #define IS2_CNT_WIDTH BITS_TO_DWORD(4 * 32)
239 #define ES0_ACT_COUNT (VSC9953_ES0_CNT + VSC9953_MAX_PORTS)
240 #define IS1_ACT_COUNT (VSC9953_IS1_CNT + 1)
241 #define IS2_ACT_COUNT (VSC9953_IS2_CNT + VSC9953_MAX_PORTS + 2)
245 TCAM_SEL_ENTRY
= BIT(0),
246 TCAM_SEL_ACTION
= BIT(1),
247 TCAM_SEL_COUNTER
= BIT(2),
248 TCAM_SEL_ALL
= VSC9953_BITMASK(3),
254 TCAM_CMD_MOVE_UP
= 2,
255 TCAM_CMD_MOVE_DOWN
= 3,
256 TCAM_CMD_INITIALIZE
= 4,
259 struct vsc9953_mdio_info
{
260 struct vsc9953_mii_mng
*regs
;
264 /* VSC9953 ANA structure */
266 struct vsc9953_ana_port
{
271 u32 vcap_s1_key_cfg
[3];
273 u32 qos_pcp_dei_map_cfg
[16];
275 u32 cpu_fwd_bpdu_cfg
;
276 u32 cpu_fwd_garp_cfg
;
283 struct vsc9953_ana_pol
{
292 struct vsc9953_ana_ana_tables
{
303 struct vsc9953_ana_ana
{
309 u32 storm_limit_burst
;
310 u32 storm_limit_cfg
[4];
325 #define PGID_DST_START 0
326 #define PGID_AGGR_START 64
327 #define PGID_SRC_START 80
329 struct vsc9953_ana_pgid
{
333 struct vsc9953_ana_pfc
{
338 struct vsc9953_ana_pol_misc
{
344 struct vsc9953_ana_common
{
350 u32 vcap_rng_type_cfg
;
351 u32 vcap_rng_val_cfg
;
356 struct vsc9953_analyzer
{
357 struct vsc9953_ana_port port
[11];
359 struct vsc9953_ana_pol pol
[164];
360 struct vsc9953_ana_ana_tables ana_tables
;
362 struct vsc9953_ana_ana ana
;
364 struct vsc9953_ana_pgid port_id_tbl
;
366 struct vsc9953_ana_pfc pfc
[10];
367 struct vsc9953_ana_pol_misc pol_misc
;
369 struct vsc9953_ana_common common
;
371 /* END VSC9953 ANA structure t*/
373 /* VSC9953 DEV_GMII structure */
375 struct vsc9953_dev_gmii_port_mode
{
382 struct vsc9953_dev_gmii_mac_cfg_status
{
390 u32 mac_fc_mac_low_cfg
;
391 u32 mac_fc_mac_high_cfg
;
395 struct vsc9953_dev_gmii
{
396 struct vsc9953_dev_gmii_port_mode port_mode
;
397 struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status
;
400 /* END VSC9953 DEV_GMII structure */
402 /* VSC9953 QSYS structure */
404 struct vsc9953_qsys_hsch
{
413 struct vsc9953_qsys_sys
{
415 u32 switch_port_mode
[11];
427 struct vsc9953_qsys_qos_cfg
{
432 struct vsc9953_qsys_drop_cfg
{
436 struct vsc9953_qsys_mmgt
{
441 struct vsc9953_qsys_hsch_misc
{
446 struct vsc9953_qsys_res_ctrl
{
452 struct vsc9953_qsys_reg
{
453 struct vsc9953_qsys_hsch hsch
[108];
454 struct vsc9953_qsys_sys sys
;
455 struct vsc9953_qsys_qos_cfg qos_cfg
;
456 struct vsc9953_qsys_drop_cfg drop_cfg
;
457 struct vsc9953_qsys_mmgt mmgt
;
458 struct vsc9953_qsys_hsch_misc hsch_misc
;
459 struct vsc9953_qsys_res_ctrl res_ctrl
[1024];
462 /* END VSC9953 QSYS structure */
464 /* VSC9953 SYS structure */
466 struct vsc9953_rx_cntrs
{
480 u32 c_rx_sz_512_1023
;
481 u32 c_rx_sz_1024_1526
;
495 u32 c_rx_yellow_prio_0
;
496 u32 c_rx_yellow_prio_1
;
497 u32 c_rx_yellow_prio_2
;
498 u32 c_rx_yellow_prio_3
;
499 u32 c_rx_yellow_prio_4
;
500 u32 c_rx_yellow_prio_5
;
501 u32 c_rx_yellow_prio_6
;
502 u32 c_rx_yellow_prio_7
;
503 u32 c_rx_green_prio_0
;
504 u32 c_rx_green_prio_1
;
505 u32 c_rx_green_prio_2
;
506 u32 c_rx_green_prio_3
;
507 u32 c_rx_green_prio_4
;
508 u32 c_rx_green_prio_5
;
509 u32 c_rx_green_prio_6
;
510 u32 c_rx_green_prio_7
;
514 struct vsc9953_tx_cntrs
{
526 u32 c_tx_sz_512_1023
;
527 u32 c_tx_sz_1024_1526
;
529 u32 c_tx_yellow_prio_0
;
530 u32 c_tx_yellow_prio_1
;
531 u32 c_tx_yellow_prio_2
;
532 u32 c_tx_yellow_prio_3
;
533 u32 c_tx_yellow_prio_4
;
534 u32 c_tx_yellow_prio_5
;
535 u32 c_tx_yellow_prio_6
;
536 u32 c_tx_yellow_prio_7
;
537 u32 c_tx_green_prio_0
;
538 u32 c_tx_green_prio_1
;
539 u32 c_tx_green_prio_2
;
540 u32 c_tx_green_prio_3
;
541 u32 c_tx_green_prio_4
;
542 u32 c_tx_green_prio_5
;
543 u32 c_tx_green_prio_6
;
544 u32 c_tx_green_prio_7
;
549 struct vsc9953_drop_cntrs
{
552 u32 c_dr_yellow_prio_0
;
553 u32 c_dr_yellow_prio_1
;
554 u32 c_dr_yellow_prio_2
;
555 u32 c_dr_yellow_prio_3
;
556 u32 c_dr_yellow_prio_4
;
557 u32 c_dr_yellow_prio_5
;
558 u32 c_dr_yellow_prio_6
;
559 u32 c_dr_yellow_prio_7
;
560 u32 c_dr_green_prio_0
;
561 u32 c_dr_green_prio_1
;
562 u32 c_dr_green_prio_2
;
563 u32 c_dr_green_prio_3
;
564 u32 c_dr_green_prio_4
;
565 u32 c_dr_green_prio_5
;
566 u32 c_dr_green_prio_6
;
567 u32 c_dr_green_prio_7
;
571 struct vsc9953_sys_stat
{
572 struct vsc9953_rx_cntrs rx_cntrs
;
573 struct vsc9953_tx_cntrs tx_cntrs
;
574 struct vsc9953_drop_cntrs drop_cntrs
;
578 struct vsc9953_sys_sys
{
583 u32 front_port_mode
[10];
589 struct vsc9953_sys_pause_cfg
{
592 u32 tail_drop_level
[11];
593 u32 tot_tail_drop_lvl
;
597 struct vsc9953_sys_mmgt
{
601 struct vsc9953_system_reg
{
602 struct vsc9953_sys_stat stat
;
603 struct vsc9953_sys_sys sys
;
604 struct vsc9953_sys_pause_cfg pause_cfg
;
605 struct vsc9953_sys_mmgt mmgt
;
608 /* END VSC9953 SYS structure */
610 /* VSC9953 REW structure */
612 struct vsc9953_rew_port
{
617 u32 port_pcp_dei_qos_map_cfg
[16];
621 struct vsc9953_rew_common
{
623 u32 dscp_remap_dp1_cfg
[64];
624 u32 dscp_remap_cfg
[64];
627 struct vsc9953_rew_reg
{
628 struct vsc9953_rew_port port
[12];
629 struct vsc9953_rew_common common
;
632 /* END VSC9953 REW structure */
634 /* VSC9953 DEVCPU_GCB structure */
636 struct vsc9953_chip_regs
{
642 struct vsc9953_gpio
{
643 u32 gpio_out_set
[10];
644 u32 gpio_out_clr
[10];
649 struct vsc9953_mii_mng
{
657 u32 miiscan_lst_rslts
;
658 u32 miiscan_lst_rslts_valid
;
661 struct vsc9953_mii_read_scan
{
662 u32 mii_scan_results_sticky
[2];
665 struct vsc9953_devcpu_gcb
{
666 struct vsc9953_chip_regs chip_regs
;
667 struct vsc9953_gpio gpio
;
668 struct vsc9953_mii_mng mii_mng
[2];
669 struct vsc9953_mii_read_scan mii_read_scan
;
672 /* END VSC9953 DEVCPU_GCB structure */
674 /* VSC9953 IS* structure */
676 struct vsc9953_vcap_core_cfg
{
677 u32 vcap_update_ctrl
;
681 struct vsc9953_vcap
{
682 struct vsc9953_vcap_core_cfg vcap_core_cfg
;
685 /* END VSC9953 IS* structure */
687 #define VSC9953_PORT_INFO_INITIALIZER(idx) \
693 .enet_if = PHY_INTERFACE_MODE_NONE, \
698 /* Structure to describe a VSC9953 port */
699 struct vsc9953_port_info
{
704 phy_interface_t enet_if
;
706 struct phy_device
*phydev
;
709 /* Structure to describe a VSC9953 switch */
710 struct vsc9953_info
{
711 struct vsc9953_port_info port
[VSC9953_MAX_PORTS
];
714 void vsc9953_init(bd_t
*bis
);
716 void vsc9953_port_info_set_mdio(int port_no
, struct mii_dev
*bus
);
717 void vsc9953_port_info_set_phy_address(int port_no
, int address
);
718 void vsc9953_port_enable(int port_no
);
719 void vsc9953_port_disable(int port_no
);
720 void vsc9953_port_info_set_phy_int(int port_no
, phy_interface_t phy_int
);
722 #endif /* _VSC9953_H_ */