include/zynqmppl.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * (C) Copyright 2015 Xilinx, Inc,
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #ifndef _ZYNQMPPL_H_
   8 #define _ZYNQMPPL_H_
   9
  10 #include <xilinx.h>
  11 #include <linux/bitops.h>
  12
  13 #define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID           0xC2000018
  14 #define ZYNQMP_SIP_SVC_PM_FPGA_LOAD             0xC2000016
  15 #define ZYNQMP_SIP_SVC_PM_FPGA_STATUS           0xC2000017
  16 #define ZYNQMP_FPGA_OP_INIT                     (1 << 0)
  17 #define ZYNQMP_FPGA_OP_LOAD                     (1 << 1)
  18 #define ZYNQMP_FPGA_OP_DONE                     (1 << 2)
  19
  20 #define ZYNQMP_FPGA_FLAG_AUTHENTICATED          BIT(2)
  21 #define ZYNQMP_FPGA_FLAG_ENCRYPTED              BIT(3)
  22
  23 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT     15
  24 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK      (0xf << \
  25                                         ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
  26 #define ZYNQMP_CSU_IDCODE_SVD_SHIFT     12
  27 #define ZYNQMP_CSU_IDCODE_SVD_MASK      (0x7 << ZYNQMP_CSU_IDCODE_SVD_SHIFT)
  28
  29 extern struct xilinx_fpga_op zynqmp_op;
  30
  31 #define XILINX_ZYNQMP_DESC \
  32 { xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op }
  33
  34 #endif /* _ZYNQMPPL_H_ */