include/zynqpl.h

   1 /*
   2  * (C) Copyright 2012-2013, Xilinx, Michal Simek
   3  *
   4  * (C) Copyright 2012
   5  * Joe Hershberger <joe.hershberger@ni.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef _ZYNQPL_H_
  11 #define _ZYNQPL_H_
  12
  13 #include <xilinx.h>
  14
  15 #if defined(CONFIG_FPGA_ZYNQPL)
  16 extern struct xilinx_fpga_op zynq_op;
  17 # define FPGA_ZYNQPL_OPS        &zynq_op
  18 #else
  19 # define FPGA_ZYNQPL_OPS        NULL
  20 #endif
  21
  22 #define XILINX_ZYNQ_7007S       0x3
  23 #define XILINX_ZYNQ_7010        0x2
  24 #define XILINX_ZYNQ_7012S       0x1c
  25 #define XILINX_ZYNQ_7014S       0x8
  26 #define XILINX_ZYNQ_7015        0x1b
  27 #define XILINX_ZYNQ_7020        0x7
  28 #define XILINX_ZYNQ_7030        0xc
  29 #define XILINX_ZYNQ_7035        0x12
  30 #define XILINX_ZYNQ_7045        0x11
  31 #define XILINX_ZYNQ_7100        0x16
  32
  33 /* Device Image Sizes */
  34 #define XILINX_XC7Z007S_SIZE    16669920/8
  35 #define XILINX_XC7Z010_SIZE     16669920/8
  36 #define XILINX_XC7Z012S_SIZE    28085344/8
  37 #define XILINX_XC7Z014S_SIZE    32364512/8
  38 #define XILINX_XC7Z015_SIZE     28085344/8
  39 #define XILINX_XC7Z020_SIZE     32364512/8
  40 #define XILINX_XC7Z030_SIZE     47839328/8
  41 #define XILINX_XC7Z035_SIZE     106571232/8
  42 #define XILINX_XC7Z045_SIZE     106571232/8
  43 #define XILINX_XC7Z100_SIZE     139330784/8
  44
  45 /* Descriptor Macros */
  46 #define XILINX_XC7Z007S_DESC(cookie) \
  47 { xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
  48         "7z007s" }
  49
  50 #define XILINX_XC7Z010_DESC(cookie) \
  51 { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
  52         "7z010" }
  53
  54 #define XILINX_XC7Z012S_DESC(cookie) \
  55 { xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
  56         "7z012s" }
  57
  58 #define XILINX_XC7Z014S_DESC(cookie) \
  59 { xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
  60         "7z014s" }
  61
  62 #define XILINX_XC7Z015_DESC(cookie) \
  63 { xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
  64         "7z015" }
  65
  66 #define XILINX_XC7Z020_DESC(cookie) \
  67 { xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
  68         "7z020" }
  69
  70 #define XILINX_XC7Z030_DESC(cookie) \
  71 { xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
  72         "7z030" }
  73
  74 #define XILINX_XC7Z035_DESC(cookie) \
  75 { xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
  76         "7z035" }
  77
  78 #define XILINX_XC7Z045_DESC(cookie) \
  79 { xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
  80         "7z045" }
  81
  82 #define XILINX_XC7Z100_DESC(cookie) \
  83 { xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
  84         "7z100" }
  85
  86 #endif /* _ZYNQPL_H_ */