lib_blackfin/u-boot.lds.S

   1 /*
   2  * U-boot - u-boot.lds.S
   3  *
   4  * Copyright (c) 2005-2008 Analog Device Inc.
   5  *
   6  * (C) Copyright 2000-2004
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <config.h>
  29 #include <asm/blackfin.h>
  30 #undef ALIGN
  31 #undef ENTRY
  32 #undef bfin
  33
  34 #ifndef LDS_BOARD_TEXT
  35 # define LDS_BOARD_TEXT
  36 #endif
  37
  38 /* If we don't actually load anything into L1 data, this will avoid
  39  * a syntax error.  If we do actually load something into L1 data,
  40  * we'll get a linker memory load error (which is what we'd want).
  41  * This is here in the first place so we can quickly test building
  42  * for different CPU's which may lack non-cache L1 data.
  43  */
  44 #ifndef L1_DATA_B_SRAM
  45 # define L1_DATA_B_SRAM      CONFIG_SYS_MONITOR_BASE
  46 # define L1_DATA_B_SRAM_SIZE 0
  47 #endif
  48
  49 /* The 0xC offset is so we don't clobber the tiny LDR jump block. */
  50 #ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
  51 # define L1_CODE_ORIGIN L1_INST_SRAM
  52 #else
  53 # define L1_CODE_ORIGIN L1_INST_SRAM + 0xC
  54 #endif
  55
  56 OUTPUT_ARCH(bfin)
  57
  58 MEMORY
  59 {
  60         ram     : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
  61         l1_code : ORIGIN = L1_CODE_ORIGIN,          LENGTH = L1_INST_SRAM_SIZE
  62         l1_data : ORIGIN = L1_DATA_B_SRAM,          LENGTH = L1_DATA_B_SRAM_SIZE
  63 }
  64
  65 ENTRY(_start)
  66 SECTIONS
  67 {
  68         .text :
  69         {
  70                 cpu/blackfin/start.o (.text .text.*)
  71
  72                 LDS_BOARD_TEXT
  73
  74                 __initcode_start = .;
  75                 cpu/blackfin/initcode.o (.text .text.*)
  76                 __initcode_end = .;
  77
  78                 *(.text .text.*)
  79         } >ram
  80
  81         .rodata :
  82         {
  83                 . = ALIGN(4);
  84                 *(.rodata .rodata.*)
  85                 *(.rodata1)
  86                 *(.eh_frame)
  87                 . = ALIGN(4);
  88         } >ram
  89
  90         .data :
  91         {
  92                 . = ALIGN(256);
  93                 *(.data .data.*)
  94                 *(.data1)
  95                 *(.sdata)
  96                 *(.sdata2)
  97                 *(.dynamic)
  98                 CONSTRUCTORS
  99         } >ram
 100
 101         .u_boot_cmd :
 102         {
 103                 ___u_boot_cmd_start = .;
 104                 *(.u_boot_cmd)
 105                 ___u_boot_cmd_end = .;
 106         } >ram
 107
 108         .text_l1 :
 109         {
 110                 . = ALIGN(4);
 111                 __stext_l1 = .;
 112                 *(.l1.text)
 113                 . = ALIGN(4);
 114                 __etext_l1 = .;
 115         } >l1_code AT>ram
 116         __stext_l1_lma = LOADADDR(.text_l1);
 117
 118         .data_l1 :
 119         {
 120                 . = ALIGN(4);
 121                 __sdata_l1 = .;
 122                 *(.l1.data)
 123                 *(.l1.bss)
 124                 . = ALIGN(4);
 125                 __edata_l1 = .;
 126         } >l1_data AT>ram
 127         __sdata_l1_lma = LOADADDR(.data_l1);
 128
 129         .bss :
 130         {
 131                 . = ALIGN(4);
 132                 __bss_start = .;
 133                 *(.sbss) *(.scommon)
 134                 *(.dynbss)
 135                 *(.bss .bss.*)
 136                 *(COMMON)
 137                 __bss_end = .;
 138         } >ram
 139 }