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1 /*
2 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 *
4 * (C) Copyright 2000
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26 #include <common.h>
27
28 #include <asm/mcftimer.h>
29
30 #ifdef CONFIG_M5271
31 #include <asm/m5271.h>
32 #include <asm/immap_5271.h>
33 #endif
34
35 #ifdef CONFIG_M5272
36 #include <asm/m5272.h>
37 #include <asm/immap_5272.h>
38 #endif
39
40 #ifdef CONFIG_M5282
41 #include <asm/m5282.h>
42 #endif
43
44 #ifdef CONFIG_M5249
45 #include <asm/m5249.h>
46 #include <asm/immap_5249.h>
47 #endif
48
49
50 static ulong timestamp;
51 #if defined(CONFIG_M5282) || defined(CONFIG_M5271)
52 static unsigned short lastinc;
53 #endif
54
55
56 #if defined(CONFIG_M5272)
57 /*
58 * We use timer 3 which is running with a period of 1 us
59 */
60 void udelay(unsigned long usec)
61 {
62 volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE3);
63 uint start, now, tmp;
64
65 while (usec > 0) {
66 if (usec > 65000)
67 tmp = 65000;
68 else
69 tmp = usec;
70 usec = usec - tmp;
71
72 /* Set up TIMER 3 as timebase clock */
73 timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
74 timerp->timer_tcn = 0;
75 /* set period to 1 us */
76 timerp->timer_tmr = (((CFG_CLK / 1000000) - 1) << 8) | MCFTIMER_TMR_CLK1 |
77 MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE;
78
79 start = now = timerp->timer_tcn;
80 while (now < start + tmp)
81 now = timerp->timer_tcn;
82 }
83 }
84
85 void mcf_timer_interrupt (void * not_used){
86 volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4);
87 volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
88
89 /* check for timer 4 interrupts */
90 if ((intp->int_isr & 0x01000000) != 0) {
91 return;
92 }
93
94 /* reset timer */
95 timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
96 timestamp ++;
97 }
98
99 void timer_init (void) {
100 volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4);
101 volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
102
103 timestamp = 0;
104
105 /* Set up TIMER 4 as clock */
106 timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
107
108 /* initialize and enable timer 4 interrupt */
109 irq_install_handler (72, mcf_timer_interrupt, 0);
110 intp->int_icr1 |= 0x0000000d;
111
112 timerp->timer_tcn = 0;
113 timerp->timer_trr = 1000; /* Interrupt every ms */
114 /* set a period of 1us, set timer mode to restart and enable timer and interrupt */
115 timerp->timer_tmr = (((CFG_CLK / 1000000) - 1) << 8) | MCFTIMER_TMR_CLK1 |
116 MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE;
117 }
118
119 void reset_timer (void)
120 {
121 timestamp = 0;
122 }
123
124 ulong get_timer (ulong base)
125 {
126 return (timestamp - base);
127 }
128
129 void set_timer (ulong t)
130 {
131 timestamp = t;
132 }
133 #endif
134
135 #if defined(CONFIG_M5282) || defined(CONFIG_M5271)
136
137 void udelay(unsigned long usec)
138 {
139 volatile unsigned short *timerp;
140 uint tmp;
141
142 timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE3);
143
144 while (usec > 0) {
145 if (usec > 65000)
146 tmp = 65000;
147 else
148 tmp = usec;
149 usec = usec - tmp;
150
151 /* Set up TIMER 3 as timebase clock */
152 timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
153 timerp[MCFTIMER_PMR] = 0;
154 /* set period to 1 us */
155 timerp[MCFTIMER_PCSR] =
156 (5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
157
158 timerp[MCFTIMER_PMR] = tmp;
159 while (timerp[MCFTIMER_PCNTR] > 0);
160 }
161 }
162
163 void timer_init (void)
164 {
165 volatile unsigned short *timerp;
166
167 timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
168 timestamp = 0;
169
170 /* Set up TIMER 4 as poll clock */
171 timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
172 timerp[MCFTIMER_PMR] = lastinc = 0;
173 timerp[MCFTIMER_PCSR] =
174 (5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
175 }
176
177 void set_timer (ulong t)
178 {
179 volatile unsigned short *timerp;
180
181 timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
182 timestamp = 0;
183 timerp[MCFTIMER_PMR] = lastinc = 0;
184 }
185
186 ulong get_timer (ulong base)
187 {
188 unsigned short now, diff;
189 volatile unsigned short *timerp;
190
191 timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
192 now = timerp[MCFTIMER_PCNTR];
193 diff = -(now - lastinc);
194
195 timestamp += diff;
196 lastinc = now;
197 return timestamp - base;
198 }
199
200 void wait_ticks (unsigned long ticks)
201 {
202 set_timer (0);
203 while (get_timer (0) < ticks);
204 }
205 #endif
206
207
208 #if defined(CONFIG_M5249)
209 /*
210 * We use timer 1 which is running with a period of 1 us
211 */
212 void udelay(unsigned long usec)
213 {
214 volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE1);
215 uint start, now, tmp;
216
217 while (usec > 0) {
218 if (usec > 65000)
219 tmp = 65000;
220 else
221 tmp = usec;
222 usec = usec - tmp;
223
224 /* Set up TIMER 1 as timebase clock */
225 timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
226 timerp->timer_tcn = 0;
227 /* set period to 1 us */
228 /* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
229 timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) | MCFTIMER_TMR_CLK1 |
230 MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE;
231
232 start = now = timerp->timer_tcn;
233 while (now < start + tmp)
234 now = timerp->timer_tcn;
235 }
236 }
237
238 void mcf_timer_interrupt (void * not_used){
239 volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2);
240
241 /* check for timer 2 interrupts */
242 if ((mbar_readLong(MCFSIM_IPR) & 0x00000400) == 0) {
243 return;
244 }
245
246 /* reset timer */
247 timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
248 timestamp ++;
249 }
250
251 void timer_init (void) {
252 volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2);
253
254 timestamp = 0;
255
256 /* Set up TIMER 2 as clock */
257 timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
258
259 /* initialize and enable timer 2 interrupt */
260 irq_install_handler (31, mcf_timer_interrupt, 0);
261 mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
262 mbar_writeByte(MCFSIM_TIMER2ICR, MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3);
263
264 timerp->timer_tcn = 0;
265 timerp->timer_trr = 1000; /* Interrupt every ms */
266 /* set a period of 1us, set timer mode to restart and enable timer and interrupt */
267 /* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
268 timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) | MCFTIMER_TMR_CLK1 |
269 MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE;
270 }
271
272 void reset_timer (void)
273 {
274 timestamp = 0;
275 }
276
277 ulong get_timer (ulong base)
278 {
279 return (timestamp - base);
280 }
281
282 void set_timer (ulong t)
283 {
284 timestamp = t;
285 }
286 #endif
287
288
289 /*
290 * This function is derived from PowerPC code (read timebase as long long).
291 * On M68K it just returns the timer value.
292 */
293 unsigned long long get_ticks(void)
294 {
295 return get_timer(0);
296 }
297
298 /*
299 * This function is derived from PowerPC code (timebase clock frequency).
300 * On M68K it returns the number of timer ticks per second.
301 */
302 ulong get_tbclk (void)
303 {
304 ulong tbclk;
305 tbclk = CFG_HZ;
306 return tbclk;
307 }