libgcc/config/rl78/mulsi3.S

   1 ;   Copyright (C) 2011-2013 Free Software Foundation, Inc.
   2 ;   Contributed by Red Hat.
   3 ;
   4 ; This file is free software; you can redistribute it and/or modify it
   5 ; under the terms of the GNU General Public License as published by the
   6 ; Free Software Foundation; either version 3, or (at your option) any
   7 ; later version.
   8 ;
   9 ; This file is distributed in the hope that it will be useful, but
  10 ; WITHOUT ANY WARRANTY; without even the implied warranty of
  11 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12 ; General Public License for more details.
  13 ;
  14 ; Under Section 7 of GPL version 3, you are granted additional
  15 ; permissions described in the GCC Runtime Library Exception, version
  16 ; 3.1, as published by the Free Software Foundation.
  17 ;
  18 ; You should have received a copy of the GNU General Public License and
  19 ; a copy of the GCC Runtime Library Exception along with this program;
  20 ; see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
  21 ; <http://www.gnu.org/licenses/>.
  22
  23 ;; 32x32=32 multiply
  24
  25 ; real
  26 ; GAS defines r0..r7 as aliases for real registers; we want the saddr
  27 ; forms here.
  28 r_0     =       0xffef8
  29 r_1     =       0xffef9
  30 r_2     =       0xffefa
  31 r_3     =       0xffefb
  32 r_4     =       0xffefc
  33 r_5     =       0xffefd
  34 r_6     =       0xffefe
  35 r_7     =       0xffeff
  36 ; clobberable
  37 r8      =       0xffef0
  38 r9      =       0xffef1
  39 r10     =       0xffef2
  40 r11     =       0xffef3
  41 r12     =       0xffef4
  42 r13     =       0xffef5
  43 r14     =       0xffef6
  44 r15     =       0xffef7
  45 ; preserved
  46 r16     =       0xffee8
  47 r17     =       0xffee9
  48 r18     =       0xffeea
  49 r19     =       0xffeeb
  50 r20     =       0xffeec
  51 r21     =       0xffeed
  52 r22     =       0xffeee
  53 r23     =       0xffeef
  54
  55
  56 ;----------------------------------------------------------------------
  57
  58 ; Register use:
  59 ;       RB0     RB1     RB2
  60 ; AX    op2L    res32L  res32H
  61 ; BC    op2H    (resH)  op1
  62 ; DE    count   (resL-tmp)
  63 ; HL    [sp+4]
  64
  65         .text
  66         nop
  67         .global ___mulsi3               ; (USI a, USI b)
  68 ___mulsi3:
  69         ;; A is at [sp+4]
  70         ;; B is at [sp+8]
  71         ;; result is in R8..R11
  72
  73         sel     rb2
  74         push    ax
  75         push    bc
  76         sel     rb0
  77
  78         clrw    ax
  79         movw    r8, ax
  80         movw    r16, ax
  81
  82         movw    ax, [sp+14]
  83         cmpw    ax, #0
  84         bz      $1f
  85         cmpw    ax, #0xffff
  86         bnz     $2f
  87         movw    ax, [sp+8]
  88         sel     rb1
  89         subw    ax, r_0
  90         sel     rb0
  91         br      $1f
  92 2:
  93         movw    bc, ax
  94         movw    ax, [sp+8]
  95         cmpw    ax, #0
  96         skz
  97         call    !.Lmul_hi
  98 1:
  99
 100         movw    ax, [sp+10]
 101         cmpw    ax, #0
 102         bz      $1f
 103         cmpw    ax, #0xffff
 104         bnz     $2f
 105         movw    ax, [sp+12]
 106         sel     rb1
 107         subw    ax, r_0
 108         sel     rb0
 109         br      $1f
 110 2:
 111         movw    bc, ax
 112         movw    ax, [sp+12]
 113         cmpw    ax, #0
 114         skz
 115         call    !.Lmul_hi
 116 1:
 117
 118         movw    ax, r8
 119         movw    r16, ax
 120         clrw    ax
 121         movw    r8, ax
 122
 123         ;; now do R16:R8 += op1L * op2L
 124
 125         ;; op1 is in AX.0 (needs to shrw)
 126         ;; op2 is in BC.2 and BC.1 (bc can shlw/rolcw)
 127         ;; res is in AX.2 and AX.1 (needs to addw)
 128
 129         movw    ax, [sp+8]
 130         movw    r10, ax         ; BC.1
 131         movw    ax, [sp+12]
 132
 133         cmpw    ax, r10
 134         bc      $.Lmul_hisi_top
 135         movw    bc, r10
 136         movw    r10, ax
 137         movw    ax, bc
 138
 139
 140 .Lmul_hisi_top:
 141         movw    bc, #0
 142
 143 .Lmul_hisi_loop:
 144         shrw    ax, 1
 145         bnc     $.Lmul_hisi_no_add
 146         sel     rb1
 147         addw    ax, bc
 148         sel     rb2
 149         sknc
 150         incw    ax
 151         addw    ax, r_2
 152 .Lmul_hisi_no_add:
 153         sel     rb1
 154         shlw    bc, 1
 155         sel     rb0
 156         rolwc   bc, 1
 157         cmpw    ax, #0
 158         bz      $.Lmul_hisi_done
 159
 160         shrw    ax, 1
 161         bnc     $.Lmul_hisi_no_add2
 162         sel     rb1
 163         addw    ax, bc
 164         sel     rb2
 165         sknc
 166         incw    ax
 167         addw    ax, r_2
 168 .Lmul_hisi_no_add2:
 169         sel     rb1
 170         shlw    bc, 1
 171         sel     rb0
 172         rolwc   bc, 1
 173         cmpw    ax, #0
 174         bnz     $.Lmul_hisi_loop
 175
 176 .Lmul_hisi_done:
 177
 178         movw    ax, r16
 179         movw    r10, ax
 180
 181         sel     rb2
 182         pop     bc
 183         pop     ax
 184         sel     rb0
 185
 186         ret
 187
 188 ;----------------------------------------------------------------------
 189
 190         .global ___mulhi3
 191 ___mulhi3:
 192         movw    r8, #0
 193         movw    ax, [sp+6]
 194         movw    bc, ax
 195         movw    ax, [sp+4]
 196
 197         ;; R8 += AX * BC
 198 .Lmul_hi:
 199         cmpw    ax, bc
 200         skc
 201         xchw    ax, bc
 202         br      $.Lmul_hi_loop
 203
 204 .Lmul_hi_top:
 205         sel     rb1
 206         addw    ax, r_2
 207         sel     rb0
 208 .Lmul_hi_no_add:
 209         shlw    bc, 1
 210 .Lmul_hi_loop:
 211         shrw    ax, 1
 212         bc      $.Lmul_hi_top
 213         cmpw    ax, #0
 214         bz      $.Lmul_hi_done
 215
 216         shlw    bc, 1
 217         shrw    ax, 1
 218         bc      $.Lmul_hi_top
 219         cmpw    ax, #0
 220         bnz     $.Lmul_hi_no_add
 221
 222 .Lmul_hi_done:
 223         ret