1 // Copyright 2019 The Go Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style
3 // license that can be found in the LICENSE file.
7 // mkpreempt generates the asyncPreempt functions for each
20 // Copied from cmd/compile/internal/ssa/gen/*Ops.go
22 var regNames386 = []string{
41 var regNamesAMD64 = []string{
78 var arches = map[string]func(){
83 "mips64x": func() { genMIPS(true) },
84 "mipsx": func() { genMIPS(false) },
86 "riscv64": genRISCV64,
90 var beLe = map[string]bool{"mips64x": true, "mipsx": true, "ppc64x": true}
96 for _, arch := range flag.Args() {
97 gen, ok := arches[arch]
99 log.Fatalf("unknown arch %s", arch)
107 for arch, gen := range arches {
108 f, err := os.Create(fmt.Sprintf("preempt_%s.s", arch))
115 if err := f.Close(); err != nil {
121 func header(arch string) {
122 fmt.Fprintf(out, "// Code generated by mkpreempt.go; DO NOT EDIT.\n\n")
124 base := arch[:len(arch)-1]
125 fmt.Fprintf(out, "// +build %s %sle\n\n", base, base)
127 fmt.Fprintf(out, "#include \"go_asm.h\"\n")
128 fmt.Fprintf(out, "#include \"textflag.h\"\n\n")
129 fmt.Fprintf(out, "TEXT ·asyncPreempt(SB),NOSPLIT|NOFRAME,$0-0\n")
132 func p(f string, args ...interface{}) {
133 fmted := fmt.Sprintf(f, args...)
134 fmt.Fprintf(out, "\t%s\n", strings.Replace(fmted, "\n", "\n\t", -1))
137 func label(l string) {
138 fmt.Fprintf(out, "%s\n", l)
144 sp string // stack pointer register
153 // If this register requires special save and restore, these
154 // give those operations with a %d placeholder for the stack
159 func (l *layout) add(op, reg string, size int) {
160 l.regs = append(l.regs, regPos{op: op, reg: reg, pos: l.stack})
164 func (l *layout) addSpecial(save, restore string, size int) {
165 l.regs = append(l.regs, regPos{save: save, restore: restore, pos: l.stack})
169 func (l *layout) save() {
170 for _, reg := range l.regs {
174 p("%s %s, %d(%s)", reg.op, reg.reg, reg.pos, l.sp)
179 func (l *layout) restore() {
180 for i := len(l.regs) - 1; i >= 0; i-- {
182 if reg.restore != "" {
183 p(reg.restore, reg.pos)
185 p("%s %d(%s), %s", reg.op, reg.pos, l.sp, reg.reg)
193 // Save general purpose registers.
194 var l = layout{sp: "SP"}
195 for _, reg := range regNames386 {
196 if reg == "SP" || strings.HasPrefix(reg, "X") {
199 l.add("MOVL", reg, 4)
202 // Save the 387 state.
204 "FSAVE %d(SP)\nFLDCW runtime·controlWord64(SB)",
208 // Save SSE state only if supported.
209 lSSE := layout{stack: l.stack, sp: "SP"}
210 for i := 0; i < 8; i++ {
211 lSSE.add("MOVUPS", fmt.Sprintf("X%d", i), 16)
214 p("ADJSP $%d", lSSE.stack)
217 p("CMPB internal∕cpu·X86+const_offsetX86HasSSE2(SB), $1\nJNE nosse")
220 p("CALL ·asyncPreempt2(SB)")
221 p("CMPB internal∕cpu·X86+const_offsetX86HasSSE2(SB), $1\nJNE nosse2")
225 p("ADJSP $%d", -lSSE.stack)
232 // Assign stack offsets.
233 var l = layout{sp: "SP"}
234 for _, reg := range regNamesAMD64 {
235 if reg == "SP" || reg == "BP" {
238 if strings.HasPrefix(reg, "X") {
239 l.add("MOVUPS", reg, 16)
241 l.add("MOVQ", reg, 8)
245 // TODO: MXCSR register?
247 // Apparently, the signal handling code path in darwin kernel leaves
248 // the upper bits of Y registers in a dirty state, which causes
249 // many SSE operations (128-bit and narrower) become much slower.
250 // Clear the upper bits to get to a clean state. See issue #37174.
251 // It is safe here as Go code don't use the upper bits of Y registers.
252 p("#ifdef GOOS_darwin")
258 p("// Save flags before clobbering them")
260 p("// obj doesn't understand ADD/SUB on SP, but does understand ADJSP")
261 p("ADJSP $%d", l.stack)
262 p("// But vet doesn't know ADJSP, so suppress vet stack checking")
265 p("CALL ·asyncPreempt2(SB)")
267 p("ADJSP $%d", -l.stack)
274 // Add integer registers R0-R12.
275 // R13 (SP), R14 (LR), R15 (PC) are special and not saved here.
276 var l = layout{sp: "R13", stack: 4} // add LR slot
277 for i := 0; i <= 12; i++ {
278 reg := fmt.Sprintf("R%d", i)
280 continue // R10 is g register, no need to save/restore
282 l.add("MOVW", reg, 4)
284 // Add flag register.
286 "MOVW CPSR, R0\nMOVW R0, %d(R13)",
287 "MOVW %d(R13), R0\nMOVW R0, CPSR",
290 // Add floating point registers F0-F15 and flag register.
291 var lfp = layout{stack: l.stack, sp: "R13"}
293 "MOVW FPCR, R0\nMOVW R0, %d(R13)",
294 "MOVW %d(R13), R0\nMOVW R0, FPCR",
296 for i := 0; i <= 15; i++ {
297 reg := fmt.Sprintf("F%d", i)
298 lfp.add("MOVD", reg, 8)
301 p("MOVW.W R14, -%d(R13)", lfp.stack) // allocate frame, save LR
303 p("MOVB ·goarm(SB), R0\nCMP $6, R0\nBLT nofp") // test goarm, and skip FP registers if goarm=5.
306 p("CALL ·asyncPreempt2(SB)")
307 p("MOVB ·goarm(SB), R0\nCMP $6, R0\nBLT nofp2") // test goarm, and skip FP registers if goarm=5.
312 p("MOVW %d(R13), R14", lfp.stack) // sigctxt.pushCall pushes LR on stack, restore it
313 p("MOVW.P %d(R13), R15", lfp.stack+4) // load PC, pop frame (including the space pushed by sigctxt.pushCall)
314 p("UNDEF") // shouldn't get here
318 // Add integer registers R0-R26
319 // R27 (REGTMP), R28 (g), R29 (FP), R30 (LR), R31 (SP) are special
320 // and not saved here.
321 var l = layout{sp: "RSP", stack: 8} // add slot to save PC of interrupted instruction
322 for i := 0; i <= 26; i++ {
324 continue // R18 is not used, skip
326 reg := fmt.Sprintf("R%d", i)
327 l.add("MOVD", reg, 8)
329 // Add flag registers.
331 "MOVD NZCV, R0\nMOVD R0, %d(RSP)",
332 "MOVD %d(RSP), R0\nMOVD R0, NZCV",
335 "MOVD FPSR, R0\nMOVD R0, %d(RSP)",
336 "MOVD %d(RSP), R0\nMOVD R0, FPSR",
338 // TODO: FPCR? I don't think we'll change it, so no need to save.
339 // Add floating point registers F0-F31.
340 for i := 0; i <= 31; i++ {
341 reg := fmt.Sprintf("F%d", i)
342 l.add("FMOVD", reg, 8)
345 l.stack += 8 // SP needs 16-byte alignment
348 // allocate frame, save PC of interrupted instruction (in LR)
349 p("MOVD R30, %d(RSP)", -l.stack)
350 p("SUB $%d, RSP", l.stack)
351 p("#ifdef GOOS_linux")
352 p("MOVD R29, -8(RSP)") // save frame pointer (only used on Linux)
353 p("SUB $8, RSP, R29") // set up new frame pointer
355 // On darwin, save the LR again after decrementing SP. We run the
356 // signal handler on the G stack (as it doesn't support SA_ONSTACK),
357 // so any writes below SP may be clobbered.
358 p("#ifdef GOOS_darwin")
363 p("CALL ·asyncPreempt2(SB)")
366 p("MOVD %d(RSP), R30", l.stack) // sigctxt.pushCall has pushed LR (at interrupt) on stack, restore it
367 p("#ifdef GOOS_linux")
368 p("MOVD -8(RSP), R29") // restore frame pointer
370 p("MOVD (RSP), R27") // load PC to REGTMP
371 p("ADD $%d, RSP", l.stack+16) // pop frame (including the space pushed by sigctxt.pushCall)
375 func genMIPS(_64bit bool) {
391 // Add integer registers R1-R22, R24-R25, R28
392 // R0 (zero), R23 (REGTMP), R29 (SP), R30 (g), R31 (LR) are special,
393 // and not saved here. R26 and R27 are reserved by kernel and not used.
394 var l = layout{sp: "R29", stack: regsize} // add slot to save PC of interrupted instruction (in LR)
395 for i := 1; i <= 25; i++ {
397 continue // R23 is REGTMP
399 reg := fmt.Sprintf("R%d", i)
400 l.add(mov, reg, regsize)
402 l.add(mov, r28, regsize)
404 mov+" HI, R1\n"+mov+" R1, %d(R29)",
405 mov+" %d(R29), R1\n"+mov+" R1, HI",
408 mov+" LO, R1\n"+mov+" R1, %d(R29)",
409 mov+" %d(R29), R1\n"+mov+" R1, LO",
411 // Add floating point control/status register FCR31 (FCR0-FCR30 are irrelevant)
413 mov+" FCR31, R1\n"+mov+" R1, %d(R29)",
414 mov+" %d(R29), R1\n"+mov+" R1, FCR31",
416 // Add floating point registers F0-F31.
417 for i := 0; i <= 31; i++ {
418 reg := fmt.Sprintf("F%d", i)
419 l.add(movf, reg, regsize)
422 // allocate frame, save PC of interrupted instruction (in LR)
423 p(mov+" R31, -%d(R29)", l.stack)
424 p(sub+" $%d, R29", l.stack)
427 p("CALL ·asyncPreempt2(SB)")
430 p(mov+" %d(R29), R31", l.stack) // sigctxt.pushCall has pushed LR (at interrupt) on stack, restore it
431 p(mov + " (R29), R23") // load PC to REGTMP
432 p(add+" $%d, R29", l.stack+regsize) // pop frame (including the space pushed by sigctxt.pushCall)
437 // Add integer registers R3-R29
438 // R0 (zero), R1 (SP), R30 (g) are special and not saved here.
439 // R2 (TOC pointer in PIC mode), R12 (function entry address in PIC mode) have been saved in sigctxt.pushCall.
440 // R31 (REGTMP) will be saved manually.
441 var l = layout{sp: "R1", stack: 32 + 8} // MinFrameSize on PPC64, plus one word for saving R31
442 for i := 3; i <= 29; i++ {
443 if i == 12 || i == 13 {
444 // R12 has been saved in sigctxt.pushCall.
445 // R13 is TLS pointer, not used by Go code. we must NOT
446 // restore it, otherwise if we parked and resumed on a
447 // different thread we'll mess up TLS addresses.
450 reg := fmt.Sprintf("R%d", i)
451 l.add("MOVD", reg, 8)
454 "MOVW CR, R31\nMOVW R31, %d(R1)",
455 "MOVW %d(R1), R31\nMOVFL R31, $0xff", // this is MOVW R31, CR
456 8) // CR is 4-byte wide, but just keep the alignment
458 "MOVD XER, R31\nMOVD R31, %d(R1)",
459 "MOVD %d(R1), R31\nMOVD R31, XER",
461 // Add floating point registers F0-F31.
462 for i := 0; i <= 31; i++ {
463 reg := fmt.Sprintf("F%d", i)
464 l.add("FMOVD", reg, 8)
466 // Add floating point control/status register FPSCR.
468 "MOVFL FPSCR, F0\nFMOVD F0, %d(R1)",
469 "FMOVD %d(R1), F0\nMOVFL F0, FPSCR",
472 p("MOVD R31, -%d(R1)", l.stack-32) // save R31 first, we'll use R31 for saving LR
474 p("MOVDU R31, -%d(R1)", l.stack) // allocate frame, save PC of interrupted instruction (in LR)
477 p("CALL ·asyncPreempt2(SB)")
480 p("MOVD %d(R1), R31", l.stack) // sigctxt.pushCall has pushed LR, R2, R12 (at interrupt) on stack, restore them
482 p("MOVD %d(R1), R2", l.stack+8)
483 p("MOVD %d(R1), R12", l.stack+16)
484 p("MOVD (R1), R31") // load PC to CTR
486 p("MOVD 32(R1), R31") // restore R31
487 p("ADD $%d, R1", l.stack+32) // pop frame (including the space pushed by sigctxt.pushCall)
492 p("// No async preemption on riscv64 - see issue 36711")
497 // Add integer registers R0-R12
498 // R13 (g), R14 (LR), R15 (SP) are special, and not saved here.
499 // Saving R10 (REGTMP) is not necessary, but it is saved anyway.
500 var l = layout{sp: "R15", stack: 16} // add slot to save PC of interrupted instruction and flags
502 "STMG R0, R12, %d(R15)",
503 "LMG %d(R15), R0, R12",
505 // Add floating point registers F0-F31.
506 for i := 0; i <= 15; i++ {
507 reg := fmt.Sprintf("F%d", i)
508 l.add("FMOVD", reg, 8)
511 // allocate frame, save PC of interrupted instruction (in LR) and flags (condition code)
512 p("IPM R10") // save flags upfront, as ADD will clobber flags
513 p("MOVD R14, -%d(R15)", l.stack)
514 p("ADD $-%d, R15", l.stack)
515 p("MOVW R10, 8(R15)") // save flags
518 p("CALL ·asyncPreempt2(SB)")
521 p("MOVD %d(R15), R14", l.stack) // sigctxt.pushCall has pushed LR (at interrupt) on stack, restore it
522 p("ADD $%d, R15", l.stack+8) // pop frame (including the space pushed by sigctxt.pushCall)
523 p("MOVWZ -%d(R15), R10", l.stack) // load flags to REGTMP
524 p("TMLH R10, $(3<<12)") // restore flags
525 p("MOVD -%d(R15), R10", l.stack+8) // load PC to REGTMP
530 p("// No async preemption on wasm")
534 func notImplemented() {
535 p("// Not implemented yet")