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[thirdparty/pciutils.git] / lspci.c
1 /*
2 * The PCI Utilities -- List All PCI Devices
3 *
4 * Copyright (c) 1997--2008 Martin Mares <mj@ucw.cz>
5 *
6 * Can be freely distributed and used under the terms of the GNU GPL.
7 */
8
9 #include <stdio.h>
10 #include <string.h>
11 #include <stdlib.h>
12 #include <stdarg.h>
13 #include <unistd.h>
14
15 #include "pciutils.h"
16
17 /* Options */
18
19 static int verbose; /* Show detailed information */
20 static int opt_buscentric; /* Show bus addresses/IRQ's instead of CPU-visible ones */
21 static int opt_hex; /* Show contents of config space as hexadecimal numbers */
22 static struct pci_filter filter; /* Device filter */
23 static int opt_tree; /* Show bus tree */
24 static int opt_machine; /* Generate machine-readable output */
25 static int opt_map_mode; /* Bus mapping mode enabled */
26 static int opt_domains; /* Show domain numbers (0=disabled, 1=auto-detected, 2=requested) */
27 static int opt_kernel; /* Show kernel drivers */
28 static char *opt_pcimap; /* Override path to Linux modules.pcimap */
29
30 const char program_name[] = "lspci";
31
32 static char options[] = "nvbxs:d:ti:mgp:kMD" GENERIC_OPTIONS ;
33
34 static char help_msg[] = "\
35 Usage: lspci [<switches>]\n\
36 \n\
37 -v\t\tBe verbose\n\
38 -n\t\tShow numeric ID's\n\
39 -nn\t\tShow both textual and numeric ID's (names & numbers)\n\
40 -b\t\tBus-centric view (PCI addresses and IRQ's instead of those seen by the CPU)\n\
41 -x\t\tShow hex-dump of the standard portion of config space\n\
42 -xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n\
43 -xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n\
44 -s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n\
45 -d [<vendor>]:[<device>]\tShow only selected devices\n\
46 -t\t\tShow bus tree\n\
47 -m\t\tProduce machine-readable output\n\
48 -i <file>\tUse specified ID database instead of %s\n"
49 #ifdef PCI_OS_LINUX
50 "\
51 -k\t\tShow kernel drivers handling each device\n\
52 -p <file>\tLook up kernel modules in a given file instead of default modules.pcimap\n"
53 #endif
54 "\
55 -D\t\tAlways show domain numbers\n\
56 -M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
57 GENERIC_HELP
58 ;
59
60 /*** Communication with libpci ***/
61
62 static struct pci_access *pacc;
63
64 /*
65 * If we aren't being compiled by GCC, use xmalloc() instead of alloca().
66 * This increases our memory footprint, but only slightly since we don't
67 * use alloca() much.
68 */
69 #if defined (__FreeBSD__) || defined (__NetBSD__) || defined (__OpenBSD__) || defined (__DragonFly__)
70 /* alloca() is defined in stdlib.h */
71 #elif defined(__GNUC__) && !defined(PCI_OS_WINDOWS)
72 #include <alloca.h>
73 #else
74 #undef alloca
75 #define alloca xmalloc
76 #endif
77
78 /*** Our view of the PCI bus ***/
79
80 struct device {
81 struct device *next;
82 struct pci_dev *dev;
83 unsigned int config_cached, config_bufsize;
84 byte *config; /* Cached configuration space data */
85 byte *present; /* Maps which configuration bytes are present */
86 };
87
88 static struct device *first_dev;
89 static int seen_errors;
90
91 static int
92 config_fetch(struct device *d, unsigned int pos, unsigned int len)
93 {
94 unsigned int end = pos+len;
95 int result;
96
97 while (pos < d->config_bufsize && len && d->present[pos])
98 pos++, len--;
99 while (pos+len <= d->config_bufsize && len && d->present[pos+len-1])
100 len--;
101 if (!len)
102 return 1;
103
104 if (end > d->config_bufsize)
105 {
106 int orig_size = d->config_bufsize;
107 while (end > d->config_bufsize)
108 d->config_bufsize *= 2;
109 d->config = xrealloc(d->config, d->config_bufsize);
110 d->present = xrealloc(d->present, d->config_bufsize);
111 memset(d->present + orig_size, 0, d->config_bufsize - orig_size);
112 }
113 result = pci_read_block(d->dev, pos, d->config + pos, len);
114 if (result)
115 memset(d->present + pos, 1, len);
116 return result;
117 }
118
119 static struct device *
120 scan_device(struct pci_dev *p)
121 {
122 struct device *d;
123
124 if (p->domain && !opt_domains)
125 opt_domains = 1;
126 if (!pci_filter_match(&filter, p))
127 return NULL;
128 d = xmalloc(sizeof(struct device));
129 memset(d, 0, sizeof(*d));
130 d->dev = p;
131 d->config_cached = d->config_bufsize = 64;
132 d->config = xmalloc(64);
133 d->present = xmalloc(64);
134 memset(d->present, 1, 64);
135 if (!pci_read_block(p, 0, d->config, 64))
136 {
137 fprintf(stderr, "lspci: Unable to read the standard configuration space header of device %04x:%02x:%02x.%d\n",
138 p->domain, p->bus, p->dev, p->func);
139 seen_errors++;
140 return NULL;
141 }
142 if ((d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
143 {
144 /* For cardbus bridges, we need to fetch 64 bytes more to get the
145 * full standard header... */
146 if (config_fetch(d, 64, 64))
147 d->config_cached += 64;
148 }
149 pci_setup_cache(p, d->config, d->config_cached);
150 pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_CLASS | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES);
151 return d;
152 }
153
154 static void
155 scan_devices(void)
156 {
157 struct device *d;
158 struct pci_dev *p;
159
160 pci_scan_bus(pacc);
161 for(p=pacc->devices; p; p=p->next)
162 if (d = scan_device(p))
163 {
164 d->next = first_dev;
165 first_dev = d;
166 }
167 }
168
169 /*** Config space accesses ***/
170
171 static void
172 check_conf_range(struct device *d, unsigned int pos, unsigned int len)
173 {
174 while (len)
175 if (!d->present[pos])
176 die("Internal bug: Accessing non-read configuration byte at position %x", pos);
177 else
178 pos++, len--;
179 }
180
181 static inline byte
182 get_conf_byte(struct device *d, unsigned int pos)
183 {
184 check_conf_range(d, pos, 1);
185 return d->config[pos];
186 }
187
188 static word
189 get_conf_word(struct device *d, unsigned int pos)
190 {
191 check_conf_range(d, pos, 2);
192 return d->config[pos] | (d->config[pos+1] << 8);
193 }
194
195 static u32
196 get_conf_long(struct device *d, unsigned int pos)
197 {
198 check_conf_range(d, pos, 4);
199 return d->config[pos] |
200 (d->config[pos+1] << 8) |
201 (d->config[pos+2] << 16) |
202 (d->config[pos+3] << 24);
203 }
204
205 /*** Sorting ***/
206
207 static int
208 compare_them(const void *A, const void *B)
209 {
210 const struct pci_dev *a = (*(const struct device **)A)->dev;
211 const struct pci_dev *b = (*(const struct device **)B)->dev;
212
213 if (a->domain < b->domain)
214 return -1;
215 if (a->domain > b->domain)
216 return 1;
217 if (a->bus < b->bus)
218 return -1;
219 if (a->bus > b->bus)
220 return 1;
221 if (a->dev < b->dev)
222 return -1;
223 if (a->dev > b->dev)
224 return 1;
225 if (a->func < b->func)
226 return -1;
227 if (a->func > b->func)
228 return 1;
229 return 0;
230 }
231
232 static void
233 sort_them(void)
234 {
235 struct device **index, **h, **last_dev;
236 int cnt;
237 struct device *d;
238
239 cnt = 0;
240 for(d=first_dev; d; d=d->next)
241 cnt++;
242 h = index = alloca(sizeof(struct device *) * cnt);
243 for(d=first_dev; d; d=d->next)
244 *h++ = d;
245 qsort(index, cnt, sizeof(struct device *), compare_them);
246 last_dev = &first_dev;
247 h = index;
248 while (cnt--)
249 {
250 *last_dev = *h;
251 last_dev = &(*h)->next;
252 h++;
253 }
254 *last_dev = NULL;
255 }
256
257 /*** Normal output ***/
258
259 #define FLAG(x,y) ((x & y) ? '+' : '-')
260
261 static void
262 show_slot_name(struct device *d)
263 {
264 struct pci_dev *p = d->dev;
265
266 if (!opt_machine ? opt_domains : (p->domain || opt_domains >= 2))
267 printf("%04x:", p->domain);
268 printf("%02x:%02x.%d", p->bus, p->dev, p->func);
269 }
270
271 static void
272 show_terse(struct device *d)
273 {
274 int c;
275 struct pci_dev *p = d->dev;
276 char classbuf[128], devbuf[128];
277
278 show_slot_name(d);
279 printf(" %s: %s",
280 pci_lookup_name(pacc, classbuf, sizeof(classbuf),
281 PCI_LOOKUP_CLASS,
282 p->device_class),
283 pci_lookup_name(pacc, devbuf, sizeof(devbuf),
284 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
285 p->vendor_id, p->device_id));
286 if (c = get_conf_byte(d, PCI_REVISION_ID))
287 printf(" (rev %02x)", c);
288 if (verbose)
289 {
290 char *x;
291 c = get_conf_byte(d, PCI_CLASS_PROG);
292 x = pci_lookup_name(pacc, devbuf, sizeof(devbuf),
293 PCI_LOOKUP_PROGIF | PCI_LOOKUP_NO_NUMBERS,
294 p->device_class, c);
295 if (c || x)
296 {
297 printf(" (prog-if %02x", c);
298 if (x)
299 printf(" [%s]", x);
300 putchar(')');
301 }
302 }
303 putchar('\n');
304 }
305
306 static void
307 get_subid(struct device *d, word *subvp, word *subdp)
308 {
309 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
310
311 if (htype == PCI_HEADER_TYPE_NORMAL)
312 {
313 *subvp = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
314 *subdp = get_conf_word(d, PCI_SUBSYSTEM_ID);
315 }
316 else if (htype == PCI_HEADER_TYPE_CARDBUS && d->config_cached >= 128)
317 {
318 *subvp = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
319 *subdp = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
320 }
321 else
322 *subvp = *subdp = 0xffff;
323 }
324
325 /*** Capabilities ***/
326
327 static void
328 cap_pm(struct device *d, int where, int cap)
329 {
330 int t, b;
331 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
332
333 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
334 if (verbose < 2)
335 return;
336 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
337 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
338 FLAG(cap, PCI_PM_CAP_DSI),
339 FLAG(cap, PCI_PM_CAP_D1),
340 FLAG(cap, PCI_PM_CAP_D2),
341 pm_aux_current[(cap >> 6) & 7],
342 FLAG(cap, PCI_PM_CAP_PME_D0),
343 FLAG(cap, PCI_PM_CAP_PME_D1),
344 FLAG(cap, PCI_PM_CAP_PME_D2),
345 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
346 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
347 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
348 return;
349 t = get_conf_word(d, where + PCI_PM_CTRL);
350 printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
351 t & PCI_PM_CTRL_STATE_MASK,
352 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
353 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
354 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
355 FLAG(t, PCI_PM_CTRL_PME_STATUS));
356 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
357 if (b)
358 printf("\t\tBridge: PM%c B3%c\n",
359 FLAG(t, PCI_PM_BPCC_ENABLE),
360 FLAG(~t, PCI_PM_PPB_B2_B3));
361 }
362
363 static void
364 format_agp_rate(int rate, char *buf, int agp3)
365 {
366 char *c = buf;
367 int i;
368
369 for(i=0; i<=2; i++)
370 if (rate & (1 << i))
371 {
372 if (c != buf)
373 *c++ = ',';
374 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
375 }
376 if (c != buf)
377 *c = 0;
378 else
379 strcpy(buf, "<none>");
380 }
381
382 static void
383 cap_agp(struct device *d, int where, int cap)
384 {
385 u32 t;
386 char rate[16];
387 int ver, rev;
388 int agp3 = 0;
389
390 ver = (cap >> 4) & 0x0f;
391 rev = cap & 0x0f;
392 printf("AGP version %x.%x\n", ver, rev);
393 if (verbose < 2)
394 return;
395 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
396 return;
397 t = get_conf_long(d, where + PCI_AGP_STATUS);
398 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
399 agp3 = 1;
400 format_agp_rate(t & 7, rate, agp3);
401 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
402 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
403 FLAG(t, PCI_AGP_STATUS_ISOCH),
404 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
405 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
406 FLAG(t, PCI_AGP_STATUS_SBA),
407 FLAG(t, PCI_AGP_STATUS_ITA_COH),
408 FLAG(t, PCI_AGP_STATUS_GART64),
409 FLAG(t, PCI_AGP_STATUS_HTRANS),
410 FLAG(t, PCI_AGP_STATUS_64BIT),
411 FLAG(t, PCI_AGP_STATUS_FW),
412 FLAG(t, PCI_AGP_STATUS_AGP3),
413 rate);
414 t = get_conf_long(d, where + PCI_AGP_COMMAND);
415 format_agp_rate(t & 7, rate, agp3);
416 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
417 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
418 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
419 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
420 FLAG(t, PCI_AGP_COMMAND_SBA),
421 FLAG(t, PCI_AGP_COMMAND_AGP),
422 FLAG(t, PCI_AGP_COMMAND_GART64),
423 FLAG(t, PCI_AGP_COMMAND_64BIT),
424 FLAG(t, PCI_AGP_COMMAND_FW),
425 rate);
426 }
427
428 static void
429 cap_pcix_nobridge(struct device *d, int where)
430 {
431 u16 command;
432 u32 status;
433 static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
434
435 printf("PCI-X non-bridge device\n");
436
437 if (verbose < 2)
438 return;
439
440 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
441 return;
442
443 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
444 status = get_conf_long(d, where + PCI_PCIX_STATUS);
445 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
446 FLAG(command, PCI_PCIX_COMMAND_DPERE),
447 FLAG(command, PCI_PCIX_COMMAND_ERO),
448 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
449 max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
450 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
451 ((status >> 8) & 0xff),
452 ((status >> 3) & 0x1f),
453 (status & PCI_PCIX_STATUS_FUNCTION),
454 FLAG(status, PCI_PCIX_STATUS_64BIT),
455 FLAG(status, PCI_PCIX_STATUS_133MHZ),
456 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
457 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
458 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
459 1 << (9 + ((status >> 21) & 3U)),
460 max_outstanding[(status >> 23) & 7U],
461 1 << (3 + ((status >> 26) & 7U)),
462 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
463 FLAG(status, PCI_PCIX_STATUS_266MHZ),
464 FLAG(status, PCI_PCIX_STATUS_533MHZ));
465 }
466
467 static void
468 cap_pcix_bridge(struct device *d, int where)
469 {
470 static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
471 u16 secstatus;
472 u32 status, upstcr, downstcr;
473
474 printf("PCI-X bridge device\n");
475
476 if (verbose < 2)
477 return;
478
479 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
480 return;
481
482 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
483 printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
484 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
485 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
486 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
487 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
488 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
489 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
490 sec_clock_freq[(secstatus >> 6) & 7]);
491 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
492 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
493 ((status >> 8) & 0xff),
494 ((status >> 3) & 0x1f),
495 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
496 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
497 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
498 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
499 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
500 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
501 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
502 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
503 printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
504 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
505 (upstcr >> 16) & 0xffff);
506 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
507 printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
508 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
509 (downstcr >> 16) & 0xffff);
510 }
511
512 static void
513 cap_pcix(struct device *d, int where)
514 {
515 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
516 {
517 case PCI_HEADER_TYPE_NORMAL:
518 cap_pcix_nobridge(d, where);
519 break;
520 case PCI_HEADER_TYPE_BRIDGE:
521 cap_pcix_bridge(d, where);
522 break;
523 }
524 }
525
526 static inline char *
527 ht_link_width(unsigned width)
528 {
529 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
530 return widths[width];
531 }
532
533 static inline char *
534 ht_link_freq(unsigned freq)
535 {
536 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
537 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
538 return freqs[freq];
539 }
540
541 static void
542 cap_ht_pri(struct device *d, int where, int cmd)
543 {
544 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
545 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
546 char *fmt;
547
548 printf("HyperTransport: Slave or Primary Interface\n");
549 if (verbose < 2)
550 return;
551
552 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
553 return;
554 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
555 if (rid < 0x23 && rid > 0x11)
556 printf("\t\t!!! Possibly incomplete decoding\n");
557
558 if (rid >= 0x23)
559 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
560 else
561 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
562 printf(fmt,
563 (cmd & PCI_HT_PRI_CMD_BUID),
564 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
565 FLAG(cmd, PCI_HT_PRI_CMD_MH),
566 FLAG(cmd, PCI_HT_PRI_CMD_DD),
567 FLAG(cmd, PCI_HT_PRI_CMD_DUL));
568 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
569 if (rid >= 0x23)
570 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
571 else
572 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
573 printf(fmt,
574 FLAG(lctr0, PCI_HT_LCTR_CFLE),
575 FLAG(lctr0, PCI_HT_LCTR_CST),
576 FLAG(lctr0, PCI_HT_LCTR_CFE),
577 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
578 FLAG(lctr0, PCI_HT_LCTR_INIT),
579 FLAG(lctr0, PCI_HT_LCTR_EOC),
580 FLAG(lctr0, PCI_HT_LCTR_TXO),
581 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
582 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
583 FLAG(lctr0, PCI_HT_LCTR_LSEN),
584 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
585 FLAG(lctr0, PCI_HT_LCTR_64B));
586 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
587 if (rid >= 0x23)
588 fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
589 else
590 fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
591 printf(fmt,
592 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
593 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
594 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
595 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
596 FLAG(lcnf0, PCI_HT_LCNF_DFI),
597 FLAG(lcnf0, PCI_HT_LCNF_DFO),
598 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
599 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
600 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
601 if (rid >= 0x23)
602 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
603 else
604 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
605 printf(fmt,
606 FLAG(lctr1, PCI_HT_LCTR_CFLE),
607 FLAG(lctr1, PCI_HT_LCTR_CST),
608 FLAG(lctr1, PCI_HT_LCTR_CFE),
609 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
610 FLAG(lctr1, PCI_HT_LCTR_INIT),
611 FLAG(lctr1, PCI_HT_LCTR_EOC),
612 FLAG(lctr1, PCI_HT_LCTR_TXO),
613 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
614 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
615 FLAG(lctr1, PCI_HT_LCTR_LSEN),
616 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
617 FLAG(lctr1, PCI_HT_LCTR_64B));
618 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
619 if (rid >= 0x23)
620 fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
621 else
622 fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
623 printf(fmt,
624 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
625 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
626 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
627 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
628 FLAG(lcnf1, PCI_HT_LCNF_DFI),
629 FLAG(lcnf1, PCI_HT_LCNF_DFO),
630 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
631 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
632 printf("\t\tRevision ID: %u.%02u\n",
633 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
634 if (rid < 0x23)
635 return;
636 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
637 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
638 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
639 FLAG(lfrer0, PCI_HT_LFRER_PROT),
640 FLAG(lfrer0, PCI_HT_LFRER_OV),
641 FLAG(lfrer0, PCI_HT_LFRER_EOC),
642 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
643 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
644 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
645 FLAG(lfcap0, PCI_HT_LFCAP_200),
646 FLAG(lfcap0, PCI_HT_LFCAP_300),
647 FLAG(lfcap0, PCI_HT_LFCAP_400),
648 FLAG(lfcap0, PCI_HT_LFCAP_500),
649 FLAG(lfcap0, PCI_HT_LFCAP_600),
650 FLAG(lfcap0, PCI_HT_LFCAP_800),
651 FLAG(lfcap0, PCI_HT_LFCAP_1000),
652 FLAG(lfcap0, PCI_HT_LFCAP_1200),
653 FLAG(lfcap0, PCI_HT_LFCAP_1400),
654 FLAG(lfcap0, PCI_HT_LFCAP_1600),
655 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
656 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
657 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
658 FLAG(ftr, PCI_HT_FTR_ISOCFC),
659 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
660 FLAG(ftr, PCI_HT_FTR_CRCTM),
661 FLAG(ftr, PCI_HT_FTR_ECTLT),
662 FLAG(ftr, PCI_HT_FTR_64BA),
663 FLAG(ftr, PCI_HT_FTR_UIDRD));
664 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
665 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
666 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
667 FLAG(lfrer1, PCI_HT_LFRER_PROT),
668 FLAG(lfrer1, PCI_HT_LFRER_OV),
669 FLAG(lfrer1, PCI_HT_LFRER_EOC),
670 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
671 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
672 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
673 FLAG(lfcap1, PCI_HT_LFCAP_200),
674 FLAG(lfcap1, PCI_HT_LFCAP_300),
675 FLAG(lfcap1, PCI_HT_LFCAP_400),
676 FLAG(lfcap1, PCI_HT_LFCAP_500),
677 FLAG(lfcap1, PCI_HT_LFCAP_600),
678 FLAG(lfcap1, PCI_HT_LFCAP_800),
679 FLAG(lfcap1, PCI_HT_LFCAP_1000),
680 FLAG(lfcap1, PCI_HT_LFCAP_1200),
681 FLAG(lfcap1, PCI_HT_LFCAP_1400),
682 FLAG(lfcap1, PCI_HT_LFCAP_1600),
683 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
684 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
685 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
686 FLAG(eh, PCI_HT_EH_PFLE),
687 FLAG(eh, PCI_HT_EH_OFLE),
688 FLAG(eh, PCI_HT_EH_PFE),
689 FLAG(eh, PCI_HT_EH_OFE),
690 FLAG(eh, PCI_HT_EH_EOCFE),
691 FLAG(eh, PCI_HT_EH_RFE),
692 FLAG(eh, PCI_HT_EH_CRCFE),
693 FLAG(eh, PCI_HT_EH_SERRFE),
694 FLAG(eh, PCI_HT_EH_CF),
695 FLAG(eh, PCI_HT_EH_RE),
696 FLAG(eh, PCI_HT_EH_PNFE),
697 FLAG(eh, PCI_HT_EH_ONFE),
698 FLAG(eh, PCI_HT_EH_EOCNFE),
699 FLAG(eh, PCI_HT_EH_RNFE),
700 FLAG(eh, PCI_HT_EH_CRCNFE),
701 FLAG(eh, PCI_HT_EH_SERRNFE));
702 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
703 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
704 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
705 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
706 printf("\t\tBus Number: %02x\n", bn);
707 }
708
709 static void
710 cap_ht_sec(struct device *d, int where, int cmd)
711 {
712 u16 lctr, lcnf, ftr, eh;
713 u8 rid, lfrer, lfcap, mbu, mlu;
714 char *fmt;
715
716 printf("HyperTransport: Host or Secondary Interface\n");
717 if (verbose < 2)
718 return;
719
720 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
721 return;
722 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
723 if (rid < 0x23 && rid > 0x11)
724 printf("\t\t!!! Possibly incomplete decoding\n");
725
726 if (rid >= 0x23)
727 fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
728 else
729 fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
730 printf(fmt,
731 FLAG(cmd, PCI_HT_SEC_CMD_WR),
732 FLAG(cmd, PCI_HT_SEC_CMD_DE),
733 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
734 FLAG(cmd, PCI_HT_SEC_CMD_CS),
735 FLAG(cmd, PCI_HT_SEC_CMD_HH),
736 FLAG(cmd, PCI_HT_SEC_CMD_AS),
737 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
738 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
739 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
740 if (rid >= 0x23)
741 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
742 else
743 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
744 printf(fmt,
745 FLAG(lctr, PCI_HT_LCTR_CFLE),
746 FLAG(lctr, PCI_HT_LCTR_CST),
747 FLAG(lctr, PCI_HT_LCTR_CFE),
748 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
749 FLAG(lctr, PCI_HT_LCTR_INIT),
750 FLAG(lctr, PCI_HT_LCTR_EOC),
751 FLAG(lctr, PCI_HT_LCTR_TXO),
752 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
753 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
754 FLAG(lctr, PCI_HT_LCTR_LSEN),
755 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
756 FLAG(lctr, PCI_HT_LCTR_64B));
757 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
758 if (rid >= 0x23)
759 fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
760 else
761 fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
762 printf(fmt,
763 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
764 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
765 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
766 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
767 FLAG(lcnf, PCI_HT_LCNF_DFI),
768 FLAG(lcnf, PCI_HT_LCNF_DFO),
769 FLAG(lcnf, PCI_HT_LCNF_DFIE),
770 FLAG(lcnf, PCI_HT_LCNF_DFOE));
771 printf("\t\tRevision ID: %u.%02u\n",
772 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
773 if (rid < 0x23)
774 return;
775 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
776 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
777 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
778 FLAG(lfrer, PCI_HT_LFRER_PROT),
779 FLAG(lfrer, PCI_HT_LFRER_OV),
780 FLAG(lfrer, PCI_HT_LFRER_EOC),
781 FLAG(lfrer, PCI_HT_LFRER_CTLT));
782 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
783 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
784 FLAG(lfcap, PCI_HT_LFCAP_200),
785 FLAG(lfcap, PCI_HT_LFCAP_300),
786 FLAG(lfcap, PCI_HT_LFCAP_400),
787 FLAG(lfcap, PCI_HT_LFCAP_500),
788 FLAG(lfcap, PCI_HT_LFCAP_600),
789 FLAG(lfcap, PCI_HT_LFCAP_800),
790 FLAG(lfcap, PCI_HT_LFCAP_1000),
791 FLAG(lfcap, PCI_HT_LFCAP_1200),
792 FLAG(lfcap, PCI_HT_LFCAP_1400),
793 FLAG(lfcap, PCI_HT_LFCAP_1600),
794 FLAG(lfcap, PCI_HT_LFCAP_VEND));
795 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
796 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
797 FLAG(ftr, PCI_HT_FTR_ISOCFC),
798 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
799 FLAG(ftr, PCI_HT_FTR_CRCTM),
800 FLAG(ftr, PCI_HT_FTR_ECTLT),
801 FLAG(ftr, PCI_HT_FTR_64BA),
802 FLAG(ftr, PCI_HT_FTR_UIDRD),
803 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
804 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
805 if (ftr & PCI_HT_SEC_FTR_EXTRS)
806 {
807 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
808 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
809 FLAG(eh, PCI_HT_EH_PFLE),
810 FLAG(eh, PCI_HT_EH_OFLE),
811 FLAG(eh, PCI_HT_EH_PFE),
812 FLAG(eh, PCI_HT_EH_OFE),
813 FLAG(eh, PCI_HT_EH_EOCFE),
814 FLAG(eh, PCI_HT_EH_RFE),
815 FLAG(eh, PCI_HT_EH_CRCFE),
816 FLAG(eh, PCI_HT_EH_SERRFE),
817 FLAG(eh, PCI_HT_EH_CF),
818 FLAG(eh, PCI_HT_EH_RE),
819 FLAG(eh, PCI_HT_EH_PNFE),
820 FLAG(eh, PCI_HT_EH_ONFE),
821 FLAG(eh, PCI_HT_EH_EOCNFE),
822 FLAG(eh, PCI_HT_EH_RNFE),
823 FLAG(eh, PCI_HT_EH_CRCNFE),
824 FLAG(eh, PCI_HT_EH_SERRNFE));
825 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
826 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
827 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
828 }
829 }
830
831 static void
832 cap_ht(struct device *d, int where, int cmd)
833 {
834 int type;
835
836 switch (cmd & PCI_HT_CMD_TYP_HI)
837 {
838 case PCI_HT_CMD_TYP_HI_PRI:
839 cap_ht_pri(d, where, cmd);
840 return;
841 case PCI_HT_CMD_TYP_HI_SEC:
842 cap_ht_sec(d, where, cmd);
843 return;
844 }
845
846 type = cmd & PCI_HT_CMD_TYP;
847 switch (type)
848 {
849 case PCI_HT_CMD_TYP_SW:
850 printf("HyperTransport: Switch\n");
851 break;
852 case PCI_HT_CMD_TYP_IDC:
853 printf("HyperTransport: Interrupt Discovery and Configuration\n");
854 break;
855 case PCI_HT_CMD_TYP_RID:
856 printf("HyperTransport: Revision ID: %u.%02u\n",
857 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
858 break;
859 case PCI_HT_CMD_TYP_UIDC:
860 printf("HyperTransport: UnitID Clumping\n");
861 break;
862 case PCI_HT_CMD_TYP_ECSA:
863 printf("HyperTransport: Extended Configuration Space Access\n");
864 break;
865 case PCI_HT_CMD_TYP_AM:
866 printf("HyperTransport: Address Mapping\n");
867 break;
868 case PCI_HT_CMD_TYP_MSIM:
869 printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
870 FLAG(cmd, PCI_HT_MSIM_CMD_EN),
871 FLAG(cmd, PCI_HT_MSIM_CMD_FIXD));
872 if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD))
873 {
874 u32 offl, offh;
875 if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8))
876 break;
877 offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO);
878 offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI);
879 printf("\t\tMapping Address Base: %016llx\n", ((unsigned long long)offh << 32) | (offl & ~0xfffff));
880 }
881 break;
882 case PCI_HT_CMD_TYP_DR:
883 printf("HyperTransport: DirectRoute\n");
884 break;
885 case PCI_HT_CMD_TYP_VCS:
886 printf("HyperTransport: VCSet\n");
887 break;
888 case PCI_HT_CMD_TYP_RM:
889 printf("HyperTransport: Retry Mode\n");
890 break;
891 case PCI_HT_CMD_TYP_X86:
892 printf("HyperTransport: X86 (reserved)\n");
893 break;
894 default:
895 printf("HyperTransport: #%02x\n", type >> 11);
896 }
897 }
898
899 static void
900 cap_msi(struct device *d, int where, int cap)
901 {
902 int is64;
903 u32 t;
904 u16 w;
905
906 printf("Message Signalled Interrupts: Mask%c 64bit%c Queue=%d/%d Enable%c\n",
907 FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
908 FLAG(cap, PCI_MSI_FLAGS_64BIT),
909 (cap & PCI_MSI_FLAGS_QSIZE) >> 4,
910 (cap & PCI_MSI_FLAGS_QMASK) >> 1,
911 FLAG(cap, PCI_MSI_FLAGS_ENABLE));
912 if (verbose < 2)
913 return;
914 is64 = cap & PCI_MSI_FLAGS_64BIT;
915 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
916 return;
917 printf("\t\tAddress: ");
918 if (is64)
919 {
920 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
921 w = get_conf_word(d, where + PCI_MSI_DATA_64);
922 printf("%08x", t);
923 }
924 else
925 w = get_conf_word(d, where + PCI_MSI_DATA_32);
926 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
927 printf("%08x Data: %04x\n", t, w);
928 if (cap & PCI_MSI_FLAGS_MASK_BIT)
929 {
930 u32 mask, pending;
931
932 if (is64)
933 {
934 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8))
935 return;
936 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64);
937 pending = get_conf_long(d, where + PCI_MSI_PENDING_64);
938 }
939 else
940 {
941 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8))
942 return;
943 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32);
944 pending = get_conf_long(d, where + PCI_MSI_PENDING_32);
945 }
946 printf("\t\tMasking: %08x Pending: %08x\n", mask, pending);
947 }
948 }
949
950 static float power_limit(int value, int scale)
951 {
952 static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
953 return value * scales[scale];
954 }
955
956 static const char *latency_l0s(int value)
957 {
958 static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
959 return latencies[value];
960 }
961
962 static const char *latency_l1(int value)
963 {
964 static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
965 return latencies[value];
966 }
967
968 static void cap_express_dev(struct device *d, int where, int type)
969 {
970 u32 t;
971 u16 w;
972
973 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
974 printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d, Latency L0s %s, L1 %s\n",
975 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
976 (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
977 latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
978 latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
979 printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
980 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
981 (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
982 printf(" AttnBtn%c AttnInd%c PwrInd%c",
983 FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
984 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
985 printf(" RBE%c FLReset%c",
986 FLAG(t, PCI_EXP_DEVCAP_RBE),
987 FLAG(t, PCI_EXP_DEVCAP_FLRESET));
988 if (type == PCI_EXP_TYPE_UPSTREAM)
989 printf("SlotPowerLimit %fW",
990 power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
991 (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
992 printf("\n");
993
994 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
995 printf("\t\tDevCtl:\tReport errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
996 FLAG(w, PCI_EXP_DEVCTL_CERE),
997 FLAG(w, PCI_EXP_DEVCTL_NFERE),
998 FLAG(w, PCI_EXP_DEVCTL_FERE),
999 FLAG(w, PCI_EXP_DEVCTL_URRE));
1000 printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
1001 FLAG(w, PCI_EXP_DEVCTL_RELAXED),
1002 FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
1003 FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
1004 FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
1005 FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
1006 if (type == PCI_EXP_TYPE_PCI_BRIDGE || type == PCI_EXP_TYPE_PCIE_BRIDGE)
1007 printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
1008 if (type == PCI_EXP_TYPE_ENDPOINT && (t & PCI_EXP_DEVCAP_FLRESET))
1009 printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
1010 printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
1011 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
1012 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
1013
1014 w = get_conf_word(d, where + PCI_EXP_DEVSTA);
1015 printf("\t\tDevSta:\tCorrErr%c UncorrErr%c FatalErr%c UnsuppReq%c AuxPwr%c TransPend%c\n",
1016 FLAG(w, PCI_EXP_DEVSTA_CED),
1017 FLAG(w, PCI_EXP_DEVSTA_NFED),
1018 FLAG(w, PCI_EXP_DEVSTA_FED),
1019 FLAG(w, PCI_EXP_DEVSTA_URD),
1020 FLAG(w, PCI_EXP_DEVSTA_AUXPD),
1021 FLAG(w, PCI_EXP_DEVSTA_TRPND));
1022
1023 /* FIXME: Second set of control/status registers is not supported yet. */
1024 }
1025
1026 static char *link_speed(int speed)
1027 {
1028 switch (speed)
1029 {
1030 case 1:
1031 return "2.5GT/s";
1032 case 2:
1033 return "5GT/s";
1034 default:
1035 return "unknown";
1036 }
1037 }
1038
1039 static char *aspm_support(int code)
1040 {
1041 switch (code)
1042 {
1043 case 1:
1044 return "L0s";
1045 case 3:
1046 return "L0s L1";
1047 default:
1048 return "unknown";
1049 }
1050 }
1051
1052 static const char *aspm_enabled(int code)
1053 {
1054 static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
1055 return desc[code];
1056 }
1057
1058 static void cap_express_link(struct device *d, int where, int type)
1059 {
1060 u32 t;
1061 u16 w;
1062
1063 t = get_conf_long(d, where + PCI_EXP_LNKCAP);
1064 printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s, Latency L0 %s, L1 %s\n",
1065 t >> 24,
1066 link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
1067 aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
1068 latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
1069 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
1070 printf("\t\t\tClockPM%c Suprise%c LLActRep%c BwNot%c\n",
1071 FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
1072 FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
1073 FLAG(t, PCI_EXP_LNKCAP_DLLA),
1074 FLAG(t, PCI_EXP_LNKCAP_LBNC));
1075
1076 w = get_conf_word(d, where + PCI_EXP_LNKCTL);
1077 printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
1078 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
1079 (type == PCI_EXP_TYPE_LEG_END))
1080 printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
1081 printf(" Disabled%c Retrain%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
1082 FLAG(w, PCI_EXP_LNKCTL_DISABLE),
1083 FLAG(w, PCI_EXP_LNKCTL_RETRAIN),
1084 FLAG(w, PCI_EXP_LNKCTL_CLOCK),
1085 FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
1086 FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
1087 FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
1088 FLAG(w, PCI_EXP_LNKCTL_BWMIE),
1089 FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
1090
1091 w = get_conf_word(d, where + PCI_EXP_LNKSTA);
1092 printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
1093 link_speed(w & PCI_EXP_LNKSTA_SPEED),
1094 (w & PCI_EXP_LNKSTA_WIDTH) >> 4,
1095 FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
1096 FLAG(w, PCI_EXP_LNKSTA_TRAIN),
1097 FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
1098 FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
1099 FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
1100 FLAG(w, PCI_EXP_LNKSTA_AUTBW));
1101 }
1102
1103 static const char *indicator(int code)
1104 {
1105 static const char *names[] = { "Unknown", "On", "Blink", "Off" };
1106 return names[code];
1107 }
1108
1109 static void cap_express_slot(struct device *d, int where)
1110 {
1111 u32 t;
1112 u16 w;
1113
1114 t = get_conf_long(d, where + PCI_EXP_SLTCAP);
1115 printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surpise%c\n",
1116 FLAG(t, PCI_EXP_SLTCAP_ATNB),
1117 FLAG(t, PCI_EXP_SLTCAP_PWRC),
1118 FLAG(t, PCI_EXP_SLTCAP_MRL),
1119 FLAG(t, PCI_EXP_SLTCAP_ATNI),
1120 FLAG(t, PCI_EXP_SLTCAP_PWRI),
1121 FLAG(t, PCI_EXP_SLTCAP_HPC),
1122 FLAG(t, PCI_EXP_SLTCAP_HPS));
1123 printf("\t\t\tSlot #%3x, PowerLimit %f; Interlock%c NoCompl%c\n",
1124 t >> 19,
1125 power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15),
1126 FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
1127 FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
1128
1129 w = get_conf_word(d, where + PCI_EXP_SLTCTL);
1130 printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
1131 FLAG(w, PCI_EXP_SLTCTL_ATNB),
1132 FLAG(w, PCI_EXP_SLTCTL_PWRF),
1133 FLAG(w, PCI_EXP_SLTCTL_MRLS),
1134 FLAG(w, PCI_EXP_SLTCTL_PRSD),
1135 FLAG(w, PCI_EXP_SLTCTL_CMDC),
1136 FLAG(w, PCI_EXP_SLTCTL_HPIE),
1137 FLAG(w, PCI_EXP_SLTCTL_LLCHG));
1138 printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
1139 indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
1140 indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
1141 FLAG(w, PCI_EXP_SLTCTL_PWRC),
1142 FLAG(w, PCI_EXP_SLTCTL_INTERLOCK));
1143
1144 w = get_conf_word(d, where + PCI_EXP_SLTSTA);
1145 printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
1146 FLAG(w, PCI_EXP_SLTSTA_ATNB),
1147 FLAG(w, PCI_EXP_SLTSTA_PWRF),
1148 FLAG(w, PCI_EXP_SLTSTA_MRL_ST),
1149 FLAG(w, PCI_EXP_SLTSTA_CMDC),
1150 FLAG(w, PCI_EXP_SLTSTA_PRES),
1151 FLAG(w, PCI_EXP_SLTSTA_INTERLOCK));
1152 printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
1153 FLAG(w, PCI_EXP_SLTSTA_MRLS),
1154 FLAG(w, PCI_EXP_SLTSTA_PRSD),
1155 FLAG(w, PCI_EXP_SLTSTA_LLCHG));
1156 }
1157
1158 static void cap_express_root(struct device *d, int where)
1159 {
1160 u32 w = get_conf_word(d, where + PCI_EXP_RTCTL);
1161 printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
1162 FLAG(w, PCI_EXP_RTCTL_SECEE),
1163 FLAG(w, PCI_EXP_RTCTL_SENFEE),
1164 FLAG(w, PCI_EXP_RTCTL_SEFEE),
1165 FLAG(w, PCI_EXP_RTCTL_PMEIE),
1166 FLAG(w, PCI_EXP_RTCTL_CRSVIS));
1167
1168 w = get_conf_word(d, where + PCI_EXP_RTCAP);
1169 printf("\t\tRootCap: CRSVisible%c\n",
1170 FLAG(w, PCI_EXP_RTCAP_CRSVIS));
1171
1172 w = get_conf_word(d, where + PCI_EXP_RTSTA);
1173 printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
1174 w & PCI_EXP_RTSTA_PME_REQID,
1175 FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
1176 FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
1177 }
1178
1179 static void
1180 cap_express(struct device *d, int where, int cap)
1181 {
1182 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1183 int size;
1184 int slot = 0;
1185
1186 printf("Express ");
1187 if (verbose >= 2)
1188 printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS);
1189 switch (type)
1190 {
1191 case PCI_EXP_TYPE_ENDPOINT:
1192 printf("Endpoint");
1193 break;
1194 case PCI_EXP_TYPE_LEG_END:
1195 printf("Legacy Endpoint");
1196 break;
1197 case PCI_EXP_TYPE_ROOT_PORT:
1198 slot = cap & PCI_EXP_FLAGS_SLOT;
1199 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1200 break;
1201 case PCI_EXP_TYPE_UPSTREAM:
1202 printf("Upstream Port");
1203 break;
1204 case PCI_EXP_TYPE_DOWNSTREAM:
1205 slot = cap & PCI_EXP_FLAGS_SLOT;
1206 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1207 break;
1208 case PCI_EXP_TYPE_PCI_BRIDGE:
1209 printf("PCI/PCI-X Bridge");
1210 break;
1211 case PCI_EXP_TYPE_PCIE_BRIDGE:
1212 printf("PCI/PCI-X to PCI-Express Bridge");
1213 break;
1214 case PCI_EXP_TYPE_ROOT_INT_EP:
1215 printf("Root Complex Integrated Endpoint");
1216 break;
1217 case PCI_EXP_TYPE_ROOT_EC:
1218 printf("Root Complex Event Collector");
1219 break;
1220 default:
1221 printf("Unknown type %d", type);
1222 }
1223 printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1224 if (verbose < 2)
1225 return;
1226
1227 size = 16;
1228 if (slot)
1229 size = 24;
1230 if (type == PCI_EXP_TYPE_ROOT_PORT)
1231 size = 32;
1232 if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1233 return;
1234
1235 cap_express_dev(d, where, type);
1236 cap_express_link(d, where, type);
1237 if (slot)
1238 cap_express_slot(d, where);
1239 if (type == PCI_EXP_TYPE_ROOT_PORT)
1240 cap_express_root(d, where);
1241 }
1242
1243 static void
1244 cap_msix(struct device *d, int where, int cap)
1245 {
1246 u32 off;
1247
1248 printf("MSI-X: Enable%c Mask%c TabSize=%d\n",
1249 FLAG(cap, PCI_MSIX_ENABLE),
1250 FLAG(cap, PCI_MSIX_MASK),
1251 (cap & PCI_MSIX_TABSIZE) + 1);
1252 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1253 return;
1254
1255 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1256 printf("\t\tVector table: BAR=%d offset=%08x\n",
1257 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1258 off = get_conf_long(d, where + PCI_MSIX_PBA);
1259 printf("\t\tPBA: BAR=%d offset=%08x\n",
1260 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1261 }
1262
1263 static void
1264 cap_slotid(int cap)
1265 {
1266 int esr = cap & 0xff;
1267 int chs = cap >> 8;
1268
1269 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1270 esr & PCI_SID_ESR_NSLOTS,
1271 FLAG(esr, PCI_SID_ESR_FIC),
1272 chs);
1273 }
1274
1275 static void
1276 cap_ssvid(struct device *d, int where)
1277 {
1278 u16 subsys_v, subsys_d;
1279 char ssnamebuf[256];
1280
1281 if (!config_fetch(d, where, 8))
1282 return;
1283 subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR);
1284 subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE);
1285 printf("Subsystem: %s\n",
1286 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1287 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1288 d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d));
1289 }
1290
1291 static void
1292 cap_dsn(struct device *d, int where)
1293 {
1294 u32 t1, t2;
1295 if (!config_fetch(d, where + 4, 8))
1296 return;
1297 t1 = get_conf_long(d, where + 4);
1298 t2 = get_conf_long(d, where + 8);
1299 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
1300 t1 & 0xff, (t1 >> 8) & 0xff, (t1 >> 16) & 0xff, t1 >> 24,
1301 t2 & 0xff, (t2 >> 8) & 0xff, (t2 >> 16) & 0xff, t2 >> 24);
1302 }
1303
1304 static void
1305 cap_debug_port(int cap)
1306 {
1307 int bar = cap >> 13;
1308 int pos = cap & 0x1fff;
1309 printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
1310 }
1311
1312 static void
1313 show_ext_caps(struct device *d)
1314 {
1315 int where = 0x100;
1316 char been_there[0x1000];
1317 memset(been_there, 0, 0x1000);
1318 do
1319 {
1320 u32 header;
1321 int id;
1322
1323 if (!config_fetch(d, where, 4))
1324 break;
1325 header = get_conf_long(d, where);
1326 if (!header)
1327 break;
1328 id = header & 0xffff;
1329 printf("\tCapabilities: [%03x] ", where);
1330 if (been_there[where]++)
1331 {
1332 printf("<chain looped>\n");
1333 break;
1334 }
1335 switch (id)
1336 {
1337 case PCI_EXT_CAP_ID_AER:
1338 printf("Advanced Error Reporting <?>\n");
1339 break;
1340 case PCI_EXT_CAP_ID_VC:
1341 printf("Virtual Channel <?>\n");
1342 break;
1343 case PCI_EXT_CAP_ID_DSN:
1344 cap_dsn(d, where);
1345 break;
1346 case PCI_EXT_CAP_ID_PB:
1347 printf("Power Budgeting <?>\n");
1348 break;
1349 case PCI_EXT_CAP_ID_RCLINK:
1350 printf("Root Complex Link <?>\n");
1351 break;
1352 case PCI_EXT_CAP_ID_RCILINK:
1353 printf("Root Complex Internal Link <?>\n");
1354 break;
1355 case PCI_EXT_CAP_ID_RCECOLL:
1356 printf("Root Complex Event Collector <?>\n");
1357 break;
1358 case PCI_EXT_CAP_ID_MFVC:
1359 printf("Multi-Function Virtual Channel <?>\n");
1360 break;
1361 case PCI_EXT_CAP_ID_RBCB:
1362 printf("Root Bridge Control Block <?>\n");
1363 break;
1364 case PCI_EXT_CAP_ID_VNDR:
1365 printf("Vendor Specific Information <?>\n");
1366 break;
1367 case PCI_EXT_CAP_ID_ACS:
1368 printf("Access Controls <?>\n");
1369 break;
1370 default:
1371 printf("#%02x\n", id);
1372 break;
1373 }
1374 where = header >> 20;
1375 } while (where);
1376 }
1377
1378 static void
1379 show_caps(struct device *d)
1380 {
1381 int can_have_ext_caps = 0;
1382
1383 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1384 {
1385 int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
1386 byte been_there[256];
1387 memset(been_there, 0, 256);
1388 while (where)
1389 {
1390 int id, next, cap;
1391 printf("\tCapabilities: ");
1392 if (!config_fetch(d, where, 4))
1393 {
1394 puts("<access denied>");
1395 break;
1396 }
1397 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1398 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1399 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1400 printf("[%02x] ", where);
1401 if (been_there[where]++)
1402 {
1403 printf("<chain looped>\n");
1404 break;
1405 }
1406 if (id == 0xff)
1407 {
1408 printf("<chain broken>\n");
1409 break;
1410 }
1411 switch (id)
1412 {
1413 case PCI_CAP_ID_PM:
1414 cap_pm(d, where, cap);
1415 break;
1416 case PCI_CAP_ID_AGP:
1417 cap_agp(d, where, cap);
1418 break;
1419 case PCI_CAP_ID_VPD:
1420 printf("Vital Product Data <?>\n");
1421 break;
1422 case PCI_CAP_ID_SLOTID:
1423 cap_slotid(cap);
1424 break;
1425 case PCI_CAP_ID_MSI:
1426 cap_msi(d, where, cap);
1427 break;
1428 case PCI_CAP_ID_CHSWP:
1429 printf("CompactPCI hot-swap <?>\n");
1430 break;
1431 case PCI_CAP_ID_PCIX:
1432 cap_pcix(d, where);
1433 can_have_ext_caps = 1;
1434 break;
1435 case PCI_CAP_ID_HT:
1436 cap_ht(d, where, cap);
1437 break;
1438 case PCI_CAP_ID_VNDR:
1439 printf("Vendor Specific Information <?>\n");
1440 break;
1441 case PCI_CAP_ID_DBG:
1442 cap_debug_port(cap);
1443 break;
1444 case PCI_CAP_ID_CCRC:
1445 printf("CompactPCI central resource control <?>\n");
1446 break;
1447 case PCI_CAP_ID_HOTPLUG:
1448 printf("Hot-plug capable\n");
1449 break;
1450 case PCI_CAP_ID_SSVID:
1451 cap_ssvid(d, where);
1452 break;
1453 case PCI_CAP_ID_AGP3:
1454 printf("AGP3 <?>\n");
1455 break;
1456 case PCI_CAP_ID_SECURE:
1457 printf("Secure device <?>\n");
1458 break;
1459 case PCI_CAP_ID_EXP:
1460 cap_express(d, where, cap);
1461 can_have_ext_caps = 1;
1462 break;
1463 case PCI_CAP_ID_MSIX:
1464 cap_msix(d, where, cap);
1465 break;
1466 case PCI_CAP_ID_SATA:
1467 printf("SATA HBA <?>\n");
1468 break;
1469 case PCI_CAP_ID_AF:
1470 printf("PCIe advanced features <?>\n");
1471 break;
1472 default:
1473 printf("#%02x [%04x]\n", id, cap);
1474 }
1475 where = next;
1476 }
1477 }
1478 if (can_have_ext_caps)
1479 show_ext_caps(d);
1480 }
1481
1482 /*** Kernel drivers ***/
1483
1484 #ifdef PCI_OS_LINUX
1485
1486 #include <sys/utsname.h>
1487
1488 struct pcimap_entry {
1489 struct pcimap_entry *next;
1490 unsigned int vendor, device;
1491 unsigned int subvendor, subdevice;
1492 unsigned int class, class_mask;
1493 char module[1];
1494 };
1495
1496 static struct pcimap_entry *pcimap_head;
1497
1498 static void
1499 load_pcimap(void)
1500 {
1501 static int tried_pcimap;
1502 struct utsname uts;
1503 char *name, line[1024];
1504 FILE *f;
1505
1506 if (tried_pcimap)
1507 return;
1508 tried_pcimap = 1;
1509
1510 if (name = opt_pcimap)
1511 {
1512 f = fopen(name, "r");
1513 if (!f)
1514 die("Cannot open pcimap file %s: %m", name);
1515 }
1516 else
1517 {
1518 if (uname(&uts) < 0)
1519 die("uname() failed: %m");
1520 name = alloca(64 + strlen(uts.release));
1521 sprintf(name, "/lib/modules/%s/modules.pcimap", uts.release);
1522 f = fopen(name, "r");
1523 if (!f)
1524 return;
1525 }
1526
1527 while (fgets(line, sizeof(line), f))
1528 {
1529 char *c = strchr(line, '\n');
1530 struct pcimap_entry *e;
1531
1532 if (!c)
1533 die("Unterminated or too long line in %s", name);
1534 *c = 0;
1535 if (!line[0] || line[0] == '#')
1536 continue;
1537
1538 c = line;
1539 while (*c && *c != ' ' && *c != '\t')
1540 c++;
1541 if (!*c)
1542 continue; /* FIXME: Emit warnings! */
1543 *c++ = 0;
1544
1545 e = xmalloc(sizeof(*e) + strlen(line));
1546 if (sscanf(c, "%i%i%i%i%i%i",
1547 &e->vendor, &e->device,
1548 &e->subvendor, &e->subdevice,
1549 &e->class, &e->class_mask) != 6)
1550 continue;
1551 e->next = pcimap_head;
1552 pcimap_head = e;
1553 strcpy(e->module, line);
1554 }
1555 fclose(f);
1556 }
1557
1558 static int
1559 match_pcimap(struct device *d, struct pcimap_entry *e)
1560 {
1561 struct pci_dev *dev = d->dev;
1562 unsigned int class = get_conf_long(d, PCI_REVISION_ID) >> 8;
1563 word subv, subd;
1564
1565 #define MATCH(x, y) ((y) > 0xffff || (x) == (y))
1566 get_subid(d, &subv, &subd);
1567 return
1568 MATCH(dev->vendor_id, e->vendor) &&
1569 MATCH(dev->device_id, e->device) &&
1570 MATCH(subv, e->subvendor) &&
1571 MATCH(subd, e->subdevice) &&
1572 (class & e->class_mask) == e->class;
1573 #undef MATCH
1574 }
1575
1576 #define DRIVER_BUF_SIZE 1024
1577
1578 static char *
1579 find_driver(struct device *d, char *buf)
1580 {
1581 struct pci_dev *dev = d->dev;
1582 char *base = dev->access->method_params[PCI_ACCESS_SYS_BUS_PCI];
1583 char name[1024], *drv;
1584 int n;
1585
1586 if (dev->access->method != PCI_ACCESS_SYS_BUS_PCI)
1587 return NULL;
1588
1589 n = snprintf(name, sizeof(name), "%s/devices/%04x:%02x:%02x.%d/driver",
1590 base, dev->domain, dev->bus, dev->dev, dev->func);
1591 if (n < 0 || n >= (int)sizeof(name))
1592 die("show_driver: sysfs device name too long, why?");
1593
1594 n = readlink(name, buf, DRIVER_BUF_SIZE);
1595 if (n < 0)
1596 return NULL;
1597 if (n >= DRIVER_BUF_SIZE)
1598 return "<name-too-long>";
1599 buf[n] = 0;
1600
1601 if (drv = strrchr(buf, '/'))
1602 return drv+1;
1603 else
1604 return buf;
1605 }
1606
1607 static void
1608 show_kernel(struct device *d)
1609 {
1610 char buf[DRIVER_BUF_SIZE];
1611 char *driver;
1612 struct pcimap_entry *e, *last = NULL;
1613
1614 if (driver = find_driver(d, buf))
1615 printf("\tKernel driver in use: %s\n", driver);
1616
1617 load_pcimap();
1618 for (e=pcimap_head; e; e=e->next)
1619 if (match_pcimap(d, e) && (!last || strcmp(last->module, e->module)))
1620 {
1621 printf("%s %s", (last ? "," : "\tKernel modules:"), e->module);
1622 last = e;
1623 }
1624 if (last)
1625 putchar('\n');
1626 }
1627
1628 static void
1629 show_kernel_machine(struct device *d)
1630 {
1631 char buf[DRIVER_BUF_SIZE];
1632 char *driver;
1633 struct pcimap_entry *e, *last = NULL;
1634
1635 if (driver = find_driver(d, buf))
1636 printf("Driver:\t%s\n", driver);
1637
1638 load_pcimap();
1639 for (e=pcimap_head; e; e=e->next)
1640 if (match_pcimap(d, e) && (!last || strcmp(last->module, e->module)))
1641 {
1642 printf("Module:\t%s\n", e->module);
1643 last = e;
1644 }
1645 }
1646
1647 #else
1648
1649 static void
1650 show_kernel(struct device *d UNUSED)
1651 {
1652 }
1653
1654 static void
1655 show_kernel_machine(struct device *d UNUSED)
1656 {
1657 }
1658
1659 #endif
1660
1661 /*** Verbose output ***/
1662
1663 static void
1664 show_size(pciaddr_t x)
1665 {
1666 if (!x)
1667 return;
1668 printf(" [size=");
1669 if (x < 1024)
1670 printf("%d", (int) x);
1671 else if (x < 1048576)
1672 printf("%dK", (int)(x / 1024));
1673 else if (x < 0x80000000)
1674 printf("%dM", (int)(x / 1048576));
1675 else
1676 printf(PCIADDR_T_FMT, x);
1677 putchar(']');
1678 }
1679
1680 static void
1681 show_bases(struct device *d, int cnt)
1682 {
1683 struct pci_dev *p = d->dev;
1684 word cmd = get_conf_word(d, PCI_COMMAND);
1685 int i;
1686
1687 for(i=0; i<cnt; i++)
1688 {
1689 pciaddr_t pos = p->base_addr[i];
1690 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
1691 u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
1692 if (flg == 0xffffffff)
1693 flg = 0;
1694 if (!pos && !flg && !len)
1695 continue;
1696 if (verbose > 1)
1697 printf("\tRegion %d: ", i);
1698 else
1699 putchar('\t');
1700 if (pos && !flg) /* Reported by the OS, but not by the device */
1701 {
1702 printf("[virtual] ");
1703 flg = pos;
1704 }
1705 if (flg & PCI_BASE_ADDRESS_SPACE_IO)
1706 {
1707 pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
1708 printf("I/O ports at ");
1709 if (a)
1710 printf(PCIADDR_PORT_FMT, a);
1711 else if (flg & PCI_BASE_ADDRESS_IO_MASK)
1712 printf("<ignored>");
1713 else
1714 printf("<unassigned>");
1715 if (!(cmd & PCI_COMMAND_IO))
1716 printf(" [disabled]");
1717 }
1718 else
1719 {
1720 int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
1721 pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
1722 int done = 0;
1723 u32 z = 0;
1724
1725 printf("Memory at ");
1726 if (t == PCI_BASE_ADDRESS_MEM_TYPE_64)
1727 {
1728 if (i >= cnt - 1)
1729 {
1730 printf("<invalid-64bit-slot>");
1731 done = 1;
1732 }
1733 else
1734 {
1735 i++;
1736 z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
1737 if (opt_buscentric)
1738 {
1739 u32 y = a & 0xffffffff;
1740 if (a || z)
1741 printf("%08x%08x", z, y);
1742 else
1743 printf("<unassigned>");
1744 done = 1;
1745 }
1746 }
1747 }
1748 if (!done)
1749 {
1750 if (a)
1751 printf(PCIADDR_T_FMT, a);
1752 else
1753 printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "<ignored>" : "<unassigned>");
1754 }
1755 printf(" (%s, %sprefetchable)",
1756 (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
1757 (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
1758 (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
1759 (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
1760 if (!(cmd & PCI_COMMAND_MEMORY))
1761 printf(" [disabled]");
1762 }
1763 show_size(len);
1764 putchar('\n');
1765 }
1766 }
1767
1768 static void
1769 show_rom(struct device *d, int reg)
1770 {
1771 struct pci_dev *p = d->dev;
1772 pciaddr_t rom = p->rom_base_addr;
1773 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
1774 u32 flg = get_conf_long(d, reg);
1775 word cmd = get_conf_word(d, PCI_COMMAND);
1776
1777 if (!rom && !flg && !len)
1778 return;
1779 putchar('\t');
1780 if ((rom & PCI_ROM_ADDRESS_MASK) && !(flg & PCI_ROM_ADDRESS_MASK))
1781 {
1782 printf("[virtual] ");
1783 flg = rom;
1784 }
1785 printf("Expansion ROM at ");
1786 if (rom & PCI_ROM_ADDRESS_MASK)
1787 printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
1788 else if (flg & PCI_ROM_ADDRESS_MASK)
1789 printf("<ignored>");
1790 else
1791 printf("<unassigned>");
1792 if (!(flg & PCI_ROM_ADDRESS_ENABLE))
1793 printf(" [disabled]");
1794 else if (!(cmd & PCI_COMMAND_MEMORY))
1795 printf(" [disabled by cmd]");
1796 show_size(len);
1797 putchar('\n');
1798 }
1799
1800 static void
1801 show_htype0(struct device *d)
1802 {
1803 show_bases(d, 6);
1804 show_rom(d, PCI_ROM_ADDRESS);
1805 show_caps(d);
1806 }
1807
1808 static void
1809 show_htype1(struct device *d)
1810 {
1811 u32 io_base = get_conf_byte(d, PCI_IO_BASE);
1812 u32 io_limit = get_conf_byte(d, PCI_IO_LIMIT);
1813 u32 io_type = io_base & PCI_IO_RANGE_TYPE_MASK;
1814 u32 mem_base = get_conf_word(d, PCI_MEMORY_BASE);
1815 u32 mem_limit = get_conf_word(d, PCI_MEMORY_LIMIT);
1816 u32 mem_type = mem_base & PCI_MEMORY_RANGE_TYPE_MASK;
1817 u32 pref_base = get_conf_word(d, PCI_PREF_MEMORY_BASE);
1818 u32 pref_limit = get_conf_word(d, PCI_PREF_MEMORY_LIMIT);
1819 u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK;
1820 word sec_stat = get_conf_word(d, PCI_SEC_STATUS);
1821 word brc = get_conf_word(d, PCI_BRIDGE_CONTROL);
1822 int verb = verbose > 2;
1823
1824 show_bases(d, 2);
1825 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1826 get_conf_byte(d, PCI_PRIMARY_BUS),
1827 get_conf_byte(d, PCI_SECONDARY_BUS),
1828 get_conf_byte(d, PCI_SUBORDINATE_BUS),
1829 get_conf_byte(d, PCI_SEC_LATENCY_TIMER));
1830
1831 if (io_type != (io_limit & PCI_IO_RANGE_TYPE_MASK) ||
1832 (io_type != PCI_IO_RANGE_TYPE_16 && io_type != PCI_IO_RANGE_TYPE_32))
1833 printf("\t!!! Unknown I/O range types %x/%x\n", io_base, io_limit);
1834 else
1835 {
1836 io_base = (io_base & PCI_IO_RANGE_MASK) << 8;
1837 io_limit = (io_limit & PCI_IO_RANGE_MASK) << 8;
1838 if (io_type == PCI_IO_RANGE_TYPE_32)
1839 {
1840 io_base |= (get_conf_word(d, PCI_IO_BASE_UPPER16) << 16);
1841 io_limit |= (get_conf_word(d, PCI_IO_LIMIT_UPPER16) << 16);
1842 }
1843 if (io_base <= io_limit || verb)
1844 printf("\tI/O behind bridge: %08x-%08x\n", io_base, io_limit+0xfff);
1845 }
1846
1847 if (mem_type != (mem_limit & PCI_MEMORY_RANGE_TYPE_MASK) ||
1848 mem_type)
1849 printf("\t!!! Unknown memory range types %x/%x\n", mem_base, mem_limit);
1850 else
1851 {
1852 mem_base = (mem_base & PCI_MEMORY_RANGE_MASK) << 16;
1853 mem_limit = (mem_limit & PCI_MEMORY_RANGE_MASK) << 16;
1854 if (mem_base <= mem_limit || verb)
1855 printf("\tMemory behind bridge: %08x-%08x\n", mem_base, mem_limit + 0xfffff);
1856 }
1857
1858 if (pref_type != (pref_limit & PCI_PREF_RANGE_TYPE_MASK) ||
1859 (pref_type != PCI_PREF_RANGE_TYPE_32 && pref_type != PCI_PREF_RANGE_TYPE_64))
1860 printf("\t!!! Unknown prefetchable memory range types %x/%x\n", pref_base, pref_limit);
1861 else
1862 {
1863 pref_base = (pref_base & PCI_PREF_RANGE_MASK) << 16;
1864 pref_limit = (pref_limit & PCI_PREF_RANGE_MASK) << 16;
1865 if (pref_base <= pref_limit || verb)
1866 {
1867 if (pref_type == PCI_PREF_RANGE_TYPE_32)
1868 printf("\tPrefetchable memory behind bridge: %08x-%08x\n", pref_base, pref_limit + 0xfffff);
1869 else
1870 printf("\tPrefetchable memory behind bridge: %08x%08x-%08x%08x\n",
1871 get_conf_long(d, PCI_PREF_BASE_UPPER32),
1872 pref_base,
1873 get_conf_long(d, PCI_PREF_LIMIT_UPPER32),
1874 pref_limit + 0xfffff);
1875 }
1876 }
1877
1878 if (verbose > 1)
1879 printf("\tSecondary status: 66MHz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c\n",
1880 FLAG(sec_stat, PCI_STATUS_66MHZ),
1881 FLAG(sec_stat, PCI_STATUS_FAST_BACK),
1882 FLAG(sec_stat, PCI_STATUS_PARITY),
1883 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1884 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1885 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1886 FLAG(sec_stat, PCI_STATUS_SIG_TARGET_ABORT),
1887 FLAG(sec_stat, PCI_STATUS_REC_TARGET_ABORT),
1888 FLAG(sec_stat, PCI_STATUS_REC_MASTER_ABORT),
1889 FLAG(sec_stat, PCI_STATUS_SIG_SYSTEM_ERROR),
1890 FLAG(sec_stat, PCI_STATUS_DETECTED_PARITY));
1891
1892 show_rom(d, PCI_ROM_ADDRESS1);
1893
1894 if (verbose > 1)
1895 {
1896 printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
1897 FLAG(brc, PCI_BRIDGE_CTL_PARITY),
1898 FLAG(brc, PCI_BRIDGE_CTL_SERR),
1899 FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
1900 FLAG(brc, PCI_BRIDGE_CTL_VGA),
1901 FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
1902 FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
1903 FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
1904 printf("\t\tPriDiscTmr%c SecDiscTmr%c DiscTmrStat%c DiscTmrSERREn%c\n",
1905 FLAG(brc, PCI_BRIDGE_CTL_PRI_DISCARD_TIMER),
1906 FLAG(brc, PCI_BRIDGE_CTL_SEC_DISCARD_TIMER),
1907 FLAG(brc, PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS),
1908 FLAG(brc, PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN));
1909 }
1910
1911 show_caps(d);
1912 }
1913
1914 static void
1915 show_htype2(struct device *d)
1916 {
1917 int i;
1918 word cmd = get_conf_word(d, PCI_COMMAND);
1919 word brc = get_conf_word(d, PCI_CB_BRIDGE_CONTROL);
1920 word exca;
1921 int verb = verbose > 2;
1922
1923 show_bases(d, 1);
1924 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1925 get_conf_byte(d, PCI_CB_PRIMARY_BUS),
1926 get_conf_byte(d, PCI_CB_CARD_BUS),
1927 get_conf_byte(d, PCI_CB_SUBORDINATE_BUS),
1928 get_conf_byte(d, PCI_CB_LATENCY_TIMER));
1929 for(i=0; i<2; i++)
1930 {
1931 int p = 8*i;
1932 u32 base = get_conf_long(d, PCI_CB_MEMORY_BASE_0 + p);
1933 u32 limit = get_conf_long(d, PCI_CB_MEMORY_LIMIT_0 + p);
1934 if (limit > base || verb)
1935 printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit,
1936 (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]",
1937 (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : "");
1938 }
1939 for(i=0; i<2; i++)
1940 {
1941 int p = 8*i;
1942 u32 base = get_conf_long(d, PCI_CB_IO_BASE_0 + p);
1943 u32 limit = get_conf_long(d, PCI_CB_IO_LIMIT_0 + p);
1944 if (!(base & PCI_IO_RANGE_TYPE_32))
1945 {
1946 base &= 0xffff;
1947 limit &= 0xffff;
1948 }
1949 base &= PCI_CB_IO_RANGE_MASK;
1950 limit = (limit & PCI_CB_IO_RANGE_MASK) + 3;
1951 if (base <= limit || verb)
1952 printf("\tI/O window %d: %08x-%08x%s\n", i, base, limit,
1953 (cmd & PCI_COMMAND_IO) ? "" : " [disabled]");
1954 }
1955
1956 if (get_conf_word(d, PCI_CB_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR)
1957 printf("\tSecondary status: SERR\n");
1958 if (verbose > 1)
1959 printf("\tBridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c\n",
1960 FLAG(brc, PCI_CB_BRIDGE_CTL_PARITY),
1961 FLAG(brc, PCI_CB_BRIDGE_CTL_SERR),
1962 FLAG(brc, PCI_CB_BRIDGE_CTL_ISA),
1963 FLAG(brc, PCI_CB_BRIDGE_CTL_VGA),
1964 FLAG(brc, PCI_CB_BRIDGE_CTL_MASTER_ABORT),
1965 FLAG(brc, PCI_CB_BRIDGE_CTL_CB_RESET),
1966 FLAG(brc, PCI_CB_BRIDGE_CTL_16BIT_INT),
1967 FLAG(brc, PCI_CB_BRIDGE_CTL_POST_WRITES));
1968
1969 if (d->config_cached < 128)
1970 {
1971 printf("\t<access denied to the rest>\n");
1972 return;
1973 }
1974
1975 exca = get_conf_word(d, PCI_CB_LEGACY_MODE_BASE);
1976 if (exca)
1977 printf("\t16-bit legacy interface ports at %04x\n", exca);
1978 }
1979
1980 static void
1981 show_verbose(struct device *d)
1982 {
1983 struct pci_dev *p = d->dev;
1984 word status = get_conf_word(d, PCI_STATUS);
1985 word cmd = get_conf_word(d, PCI_COMMAND);
1986 word class = p->device_class;
1987 byte bist = get_conf_byte(d, PCI_BIST);
1988 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1989 byte latency = get_conf_byte(d, PCI_LATENCY_TIMER);
1990 byte cache_line = get_conf_byte(d, PCI_CACHE_LINE_SIZE);
1991 byte max_lat, min_gnt;
1992 byte int_pin = get_conf_byte(d, PCI_INTERRUPT_PIN);
1993 unsigned int irq = p->irq;
1994 word subsys_v, subsys_d;
1995 char ssnamebuf[256];
1996
1997 show_terse(d);
1998
1999 switch (htype)
2000 {
2001 case PCI_HEADER_TYPE_NORMAL:
2002 if (class == PCI_CLASS_BRIDGE_PCI)
2003 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
2004 max_lat = get_conf_byte(d, PCI_MAX_LAT);
2005 min_gnt = get_conf_byte(d, PCI_MIN_GNT);
2006 break;
2007 case PCI_HEADER_TYPE_BRIDGE:
2008 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
2009 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
2010 irq = int_pin = min_gnt = max_lat = 0;
2011 break;
2012 case PCI_HEADER_TYPE_CARDBUS:
2013 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
2014 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
2015 min_gnt = max_lat = 0;
2016 break;
2017 default:
2018 printf("\t!!! Unknown header type %02x\n", htype);
2019 return;
2020 }
2021
2022 get_subid(d, &subsys_v, &subsys_d);
2023 if (subsys_v && subsys_v != 0xffff)
2024 printf("\tSubsystem: %s\n",
2025 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
2026 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
2027 p->vendor_id, p->device_id, subsys_v, subsys_d));
2028
2029 if (verbose > 1)
2030 {
2031 printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c DisINTx%c\n",
2032 FLAG(cmd, PCI_COMMAND_IO),
2033 FLAG(cmd, PCI_COMMAND_MEMORY),
2034 FLAG(cmd, PCI_COMMAND_MASTER),
2035 FLAG(cmd, PCI_COMMAND_SPECIAL),
2036 FLAG(cmd, PCI_COMMAND_INVALIDATE),
2037 FLAG(cmd, PCI_COMMAND_VGA_PALETTE),
2038 FLAG(cmd, PCI_COMMAND_PARITY),
2039 FLAG(cmd, PCI_COMMAND_WAIT),
2040 FLAG(cmd, PCI_COMMAND_SERR),
2041 FLAG(cmd, PCI_COMMAND_FAST_BACK),
2042 FLAG(cmd, PCI_COMMAND_DISABLE_INTx));
2043 printf("\tStatus: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c INTx%c\n",
2044 FLAG(status, PCI_STATUS_CAP_LIST),
2045 FLAG(status, PCI_STATUS_66MHZ),
2046 FLAG(status, PCI_STATUS_UDF),
2047 FLAG(status, PCI_STATUS_FAST_BACK),
2048 FLAG(status, PCI_STATUS_PARITY),
2049 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
2050 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
2051 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
2052 FLAG(status, PCI_STATUS_SIG_TARGET_ABORT),
2053 FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
2054 FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
2055 FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
2056 FLAG(status, PCI_STATUS_DETECTED_PARITY),
2057 FLAG(status, PCI_STATUS_INTx));
2058 if (cmd & PCI_COMMAND_MASTER)
2059 {
2060 printf("\tLatency: %d", latency);
2061 if (min_gnt || max_lat)
2062 {
2063 printf(" (");
2064 if (min_gnt)
2065 printf("%dns min", min_gnt*250);
2066 if (min_gnt && max_lat)
2067 printf(", ");
2068 if (max_lat)
2069 printf("%dns max", max_lat*250);
2070 putchar(')');
2071 }
2072 if (cache_line)
2073 printf(", Cache Line Size: %d bytes", cache_line * 4);
2074 putchar('\n');
2075 }
2076 if (int_pin || irq)
2077 printf("\tInterrupt: pin %c routed to IRQ " PCIIRQ_FMT "\n",
2078 (int_pin ? 'A' + int_pin - 1 : '?'), irq);
2079 }
2080 else
2081 {
2082 printf("\tFlags: ");
2083 if (cmd & PCI_COMMAND_MASTER)
2084 printf("bus master, ");
2085 if (cmd & PCI_COMMAND_VGA_PALETTE)
2086 printf("VGA palette snoop, ");
2087 if (cmd & PCI_COMMAND_WAIT)
2088 printf("stepping, ");
2089 if (cmd & PCI_COMMAND_FAST_BACK)
2090 printf("fast Back2Back, ");
2091 if (status & PCI_STATUS_66MHZ)
2092 printf("66MHz, ");
2093 if (status & PCI_STATUS_UDF)
2094 printf("user-definable features, ");
2095 printf("%s devsel",
2096 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
2097 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
2098 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??");
2099 if (cmd & PCI_COMMAND_MASTER)
2100 printf(", latency %d", latency);
2101 if (irq)
2102 printf(", IRQ " PCIIRQ_FMT, irq);
2103 putchar('\n');
2104 }
2105
2106 if (bist & PCI_BIST_CAPABLE)
2107 {
2108 if (bist & PCI_BIST_START)
2109 printf("\tBIST is running\n");
2110 else
2111 printf("\tBIST result: %02x\n", bist & PCI_BIST_CODE_MASK);
2112 }
2113
2114 switch (htype)
2115 {
2116 case PCI_HEADER_TYPE_NORMAL:
2117 show_htype0(d);
2118 break;
2119 case PCI_HEADER_TYPE_BRIDGE:
2120 show_htype1(d);
2121 break;
2122 case PCI_HEADER_TYPE_CARDBUS:
2123 show_htype2(d);
2124 break;
2125 }
2126 }
2127
2128 /*** Machine-readable dumps ***/
2129
2130 static void
2131 show_hex_dump(struct device *d)
2132 {
2133 unsigned int i, cnt;
2134
2135 cnt = d->config_cached;
2136 if (opt_hex >= 3 && config_fetch(d, cnt, 256-cnt))
2137 {
2138 cnt = 256;
2139 if (opt_hex >= 4 && config_fetch(d, 256, 4096-256))
2140 cnt = 4096;
2141 }
2142
2143 for(i=0; i<cnt; i++)
2144 {
2145 if (! (i & 15))
2146 printf("%02x:", i);
2147 printf(" %02x", get_conf_byte(d, i));
2148 if ((i & 15) == 15)
2149 putchar('\n');
2150 }
2151 }
2152
2153 static void
2154 print_shell_escaped(char *c)
2155 {
2156 printf(" \"");
2157 while (*c)
2158 {
2159 if (*c == '"' || *c == '\\')
2160 putchar('\\');
2161 putchar(*c++);
2162 }
2163 putchar('"');
2164 }
2165
2166 static void
2167 show_machine(struct device *d)
2168 {
2169 struct pci_dev *p = d->dev;
2170 int c;
2171 word sv_id, sd_id;
2172 char classbuf[128], vendbuf[128], devbuf[128], svbuf[128], sdbuf[128];
2173
2174 get_subid(d, &sv_id, &sd_id);
2175
2176 if (verbose)
2177 {
2178 printf((opt_machine >= 2) ? "Slot:\t" : "Device:\t");
2179 show_slot_name(d);
2180 putchar('\n');
2181 printf("Class:\t%s\n",
2182 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
2183 printf("Vendor:\t%s\n",
2184 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
2185 printf("Device:\t%s\n",
2186 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
2187 if (sv_id && sv_id != 0xffff)
2188 {
2189 printf("SVendor:\t%s\n",
2190 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
2191 printf("SDevice:\t%s\n",
2192 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
2193 }
2194 if (c = get_conf_byte(d, PCI_REVISION_ID))
2195 printf("Rev:\t%02x\n", c);
2196 if (c = get_conf_byte(d, PCI_CLASS_PROG))
2197 printf("ProgIf:\t%02x\n", c);
2198 if (opt_kernel)
2199 show_kernel_machine(d);
2200 }
2201 else
2202 {
2203 show_slot_name(d);
2204 print_shell_escaped(pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
2205 print_shell_escaped(pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
2206 print_shell_escaped(pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
2207 if (c = get_conf_byte(d, PCI_REVISION_ID))
2208 printf(" -r%02x", c);
2209 if (c = get_conf_byte(d, PCI_CLASS_PROG))
2210 printf(" -p%02x", c);
2211 if (sv_id && sv_id != 0xffff)
2212 {
2213 print_shell_escaped(pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
2214 print_shell_escaped(pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
2215 }
2216 else
2217 printf(" \"\" \"\"");
2218 putchar('\n');
2219 }
2220 }
2221
2222 /*** Main show function ***/
2223
2224 static void
2225 show_device(struct device *d)
2226 {
2227 if (opt_machine)
2228 show_machine(d);
2229 else
2230 {
2231 if (verbose)
2232 show_verbose(d);
2233 else
2234 show_terse(d);
2235 if (opt_kernel || verbose)
2236 show_kernel(d);
2237 }
2238 if (opt_hex)
2239 show_hex_dump(d);
2240 if (verbose || opt_hex)
2241 putchar('\n');
2242 }
2243
2244 static void
2245 show(void)
2246 {
2247 struct device *d;
2248
2249 for(d=first_dev; d; d=d->next)
2250 show_device(d);
2251 }
2252
2253 /*** Tree output ***/
2254
2255 struct bridge {
2256 struct bridge *chain; /* Single-linked list of bridges */
2257 struct bridge *next, *child; /* Tree of bridges */
2258 struct bus *first_bus; /* List of buses connected to this bridge */
2259 unsigned int domain;
2260 unsigned int primary, secondary, subordinate; /* Bus numbers */
2261 struct device *br_dev;
2262 };
2263
2264 struct bus {
2265 unsigned int domain;
2266 unsigned int number;
2267 struct bus *sibling;
2268 struct device *first_dev, **last_dev;
2269 };
2270
2271 static struct bridge host_bridge = { NULL, NULL, NULL, NULL, 0, ~0, 0, ~0, NULL };
2272
2273 static struct bus *
2274 find_bus(struct bridge *b, unsigned int domain, unsigned int n)
2275 {
2276 struct bus *bus;
2277
2278 for(bus=b->first_bus; bus; bus=bus->sibling)
2279 if (bus->domain == domain && bus->number == n)
2280 break;
2281 return bus;
2282 }
2283
2284 static struct bus *
2285 new_bus(struct bridge *b, unsigned int domain, unsigned int n)
2286 {
2287 struct bus *bus = xmalloc(sizeof(struct bus));
2288 bus->domain = domain;
2289 bus->number = n;
2290 bus->sibling = b->first_bus;
2291 bus->first_dev = NULL;
2292 bus->last_dev = &bus->first_dev;
2293 b->first_bus = bus;
2294 return bus;
2295 }
2296
2297 static void
2298 insert_dev(struct device *d, struct bridge *b)
2299 {
2300 struct pci_dev *p = d->dev;
2301 struct bus *bus;
2302
2303 if (! (bus = find_bus(b, p->domain, p->bus)))
2304 {
2305 struct bridge *c;
2306 for(c=b->child; c; c=c->next)
2307 if (c->domain == p->domain && c->secondary <= p->bus && p->bus <= c->subordinate)
2308 {
2309 insert_dev(d, c);
2310 return;
2311 }
2312 bus = new_bus(b, p->domain, p->bus);
2313 }
2314 /* Simple insertion at the end _does_ guarantee the correct order as the
2315 * original device list was sorted by (domain, bus, devfn) lexicographically
2316 * and all devices on the new list have the same bus number.
2317 */
2318 *bus->last_dev = d;
2319 bus->last_dev = &d->next;
2320 d->next = NULL;
2321 }
2322
2323 static void
2324 grow_tree(void)
2325 {
2326 struct device *d, *d2;
2327 struct bridge **last_br, *b;
2328
2329 /* Build list of bridges */
2330
2331 last_br = &host_bridge.chain;
2332 for(d=first_dev; d; d=d->next)
2333 {
2334 word class = d->dev->device_class;
2335 byte ht = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
2336 if (class == PCI_CLASS_BRIDGE_PCI &&
2337 (ht == PCI_HEADER_TYPE_BRIDGE || ht == PCI_HEADER_TYPE_CARDBUS))
2338 {
2339 b = xmalloc(sizeof(struct bridge));
2340 b->domain = d->dev->domain;
2341 if (ht == PCI_HEADER_TYPE_BRIDGE)
2342 {
2343 b->primary = get_conf_byte(d, PCI_PRIMARY_BUS);
2344 b->secondary = get_conf_byte(d, PCI_SECONDARY_BUS);
2345 b->subordinate = get_conf_byte(d, PCI_SUBORDINATE_BUS);
2346 }
2347 else
2348 {
2349 b->primary = get_conf_byte(d, PCI_CB_PRIMARY_BUS);
2350 b->secondary = get_conf_byte(d, PCI_CB_CARD_BUS);
2351 b->subordinate = get_conf_byte(d, PCI_CB_SUBORDINATE_BUS);
2352 }
2353 *last_br = b;
2354 last_br = &b->chain;
2355 b->next = b->child = NULL;
2356 b->first_bus = NULL;
2357 b->br_dev = d;
2358 }
2359 }
2360 *last_br = NULL;
2361
2362 /* Create a bridge tree */
2363
2364 for(b=&host_bridge; b; b=b->chain)
2365 {
2366 struct bridge *c, *best;
2367 best = NULL;
2368 for(c=&host_bridge; c; c=c->chain)
2369 if (c != b && (c == &host_bridge || b->domain == c->domain) &&
2370 b->primary >= c->secondary && b->primary <= c->subordinate &&
2371 (!best || best->subordinate - best->primary > c->subordinate - c->primary))
2372 best = c;
2373 if (best)
2374 {
2375 b->next = best->child;
2376 best->child = b;
2377 }
2378 }
2379
2380 /* Insert secondary bus for each bridge */
2381
2382 for(b=&host_bridge; b; b=b->chain)
2383 if (!find_bus(b, b->domain, b->secondary))
2384 new_bus(b, b->domain, b->secondary);
2385
2386 /* Create bus structs and link devices */
2387
2388 for(d=first_dev; d;)
2389 {
2390 d2 = d->next;
2391 insert_dev(d, &host_bridge);
2392 d = d2;
2393 }
2394 }
2395
2396 static void
2397 print_it(char *line, char *p)
2398 {
2399 *p++ = '\n';
2400 *p = 0;
2401 fputs(line, stdout);
2402 for(p=line; *p; p++)
2403 if (*p == '+' || *p == '|')
2404 *p = '|';
2405 else
2406 *p = ' ';
2407 }
2408
2409 static void show_tree_bridge(struct bridge *, char *, char *);
2410
2411 static void
2412 show_tree_dev(struct device *d, char *line, char *p)
2413 {
2414 struct pci_dev *q = d->dev;
2415 struct bridge *b;
2416 char namebuf[256];
2417
2418 p += sprintf(p, "%02x.%x", q->dev, q->func);
2419 for(b=&host_bridge; b; b=b->chain)
2420 if (b->br_dev == d)
2421 {
2422 if (b->secondary == b->subordinate)
2423 p += sprintf(p, "-[%04x:%02x]-", b->domain, b->secondary);
2424 else
2425 p += sprintf(p, "-[%04x:%02x-%02x]-", b->domain, b->secondary, b->subordinate);
2426 show_tree_bridge(b, line, p);
2427 return;
2428 }
2429 if (verbose)
2430 p += sprintf(p, " %s",
2431 pci_lookup_name(pacc, namebuf, sizeof(namebuf),
2432 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
2433 q->vendor_id, q->device_id));
2434 print_it(line, p);
2435 }
2436
2437 static void
2438 show_tree_bus(struct bus *b, char *line, char *p)
2439 {
2440 if (!b->first_dev)
2441 print_it(line, p);
2442 else if (!b->first_dev->next)
2443 {
2444 *p++ = '-';
2445 *p++ = '-';
2446 show_tree_dev(b->first_dev, line, p);
2447 }
2448 else
2449 {
2450 struct device *d = b->first_dev;
2451 while (d->next)
2452 {
2453 p[0] = '+';
2454 p[1] = '-';
2455 show_tree_dev(d, line, p+2);
2456 d = d->next;
2457 }
2458 p[0] = '\\';
2459 p[1] = '-';
2460 show_tree_dev(d, line, p+2);
2461 }
2462 }
2463
2464 static void
2465 show_tree_bridge(struct bridge *b, char *line, char *p)
2466 {
2467 *p++ = '-';
2468 if (!b->first_bus->sibling)
2469 {
2470 if (b == &host_bridge)
2471 p += sprintf(p, "[%04x:%02x]-", b->domain, b->first_bus->number);
2472 show_tree_bus(b->first_bus, line, p);
2473 }
2474 else
2475 {
2476 struct bus *u = b->first_bus;
2477 char *k;
2478
2479 while (u->sibling)
2480 {
2481 k = p + sprintf(p, "+-[%04x:%02x]-", u->domain, u->number);
2482 show_tree_bus(u, line, k);
2483 u = u->sibling;
2484 }
2485 k = p + sprintf(p, "\\-[%04x:%02x]-", u->domain, u->number);
2486 show_tree_bus(u, line, k);
2487 }
2488 }
2489
2490 static void
2491 show_forest(void)
2492 {
2493 char line[256];
2494
2495 grow_tree();
2496 show_tree_bridge(&host_bridge, line, line);
2497 }
2498
2499 /*** Bus mapping mode ***/
2500
2501 struct bus_bridge {
2502 struct bus_bridge *next;
2503 byte this, dev, func, first, last, bug;
2504 };
2505
2506 struct bus_info {
2507 byte exists;
2508 byte guestbook;
2509 struct bus_bridge *bridges, *via;
2510 };
2511
2512 static struct bus_info *bus_info;
2513
2514 static void
2515 map_bridge(struct bus_info *bi, struct device *d, int np, int ns, int nl)
2516 {
2517 struct bus_bridge *b = xmalloc(sizeof(struct bus_bridge));
2518 struct pci_dev *p = d->dev;
2519
2520 b->next = bi->bridges;
2521 bi->bridges = b;
2522 b->this = get_conf_byte(d, np);
2523 b->dev = p->dev;
2524 b->func = p->func;
2525 b->first = get_conf_byte(d, ns);
2526 b->last = get_conf_byte(d, nl);
2527 printf("## %02x.%02x:%d is a bridge from %02x to %02x-%02x\n",
2528 p->bus, p->dev, p->func, b->this, b->first, b->last);
2529 if (b->this != p->bus)
2530 printf("!!! Bridge points to invalid primary bus.\n");
2531 if (b->first > b->last)
2532 {
2533 printf("!!! Bridge points to invalid bus range.\n");
2534 b->last = b->first;
2535 }
2536 }
2537
2538 static void
2539 do_map_bus(int bus)
2540 {
2541 int dev, func;
2542 int verbose = pacc->debugging;
2543 struct bus_info *bi = bus_info + bus;
2544 struct device *d;
2545
2546 if (verbose)
2547 printf("Mapping bus %02x\n", bus);
2548 for(dev = 0; dev < 32; dev++)
2549 if (filter.slot < 0 || filter.slot == dev)
2550 {
2551 int func_limit = 1;
2552 for(func = 0; func < func_limit; func++)
2553 if (filter.func < 0 || filter.func == func)
2554 {
2555 /* XXX: Bus mapping supports only domain 0 */
2556 struct pci_dev *p = pci_get_dev(pacc, 0, bus, dev, func);
2557 u16 vendor = pci_read_word(p, PCI_VENDOR_ID);
2558 if (vendor && vendor != 0xffff)
2559 {
2560 if (!func && (pci_read_byte(p, PCI_HEADER_TYPE) & 0x80))
2561 func_limit = 8;
2562 if (verbose)
2563 printf("Discovered device %02x:%02x.%d\n", bus, dev, func);
2564 bi->exists = 1;
2565 if (d = scan_device(p))
2566 {
2567 show_device(d);
2568 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
2569 {
2570 case PCI_HEADER_TYPE_BRIDGE:
2571 map_bridge(bi, d, PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS);
2572 break;
2573 case PCI_HEADER_TYPE_CARDBUS:
2574 map_bridge(bi, d, PCI_CB_PRIMARY_BUS, PCI_CB_CARD_BUS, PCI_CB_SUBORDINATE_BUS);
2575 break;
2576 }
2577 free(d);
2578 }
2579 else if (verbose)
2580 printf("But it was filtered out.\n");
2581 }
2582 pci_free_dev(p);
2583 }
2584 }
2585 }
2586
2587 static void
2588 do_map_bridges(int bus, int min, int max)
2589 {
2590 struct bus_info *bi = bus_info + bus;
2591 struct bus_bridge *b;
2592
2593 bi->guestbook = 1;
2594 for(b=bi->bridges; b; b=b->next)
2595 {
2596 if (bus_info[b->first].guestbook)
2597 b->bug = 1;
2598 else if (b->first < min || b->last > max)
2599 b->bug = 2;
2600 else
2601 {
2602 bus_info[b->first].via = b;
2603 do_map_bridges(b->first, b->first, b->last);
2604 }
2605 }
2606 }
2607
2608 static void
2609 map_bridges(void)
2610 {
2611 int i;
2612
2613 printf("\nSummary of buses:\n\n");
2614 for(i=0; i<256; i++)
2615 if (bus_info[i].exists && !bus_info[i].guestbook)
2616 do_map_bridges(i, 0, 255);
2617 for(i=0; i<256; i++)
2618 {
2619 struct bus_info *bi = bus_info + i;
2620 struct bus_bridge *b = bi->via;
2621
2622 if (bi->exists)
2623 {
2624 printf("%02x: ", i);
2625 if (b)
2626 printf("Entered via %02x:%02x.%d\n", b->this, b->dev, b->func);
2627 else if (!i)
2628 printf("Primary host bus\n");
2629 else
2630 printf("Secondary host bus (?)\n");
2631 }
2632 for(b=bi->bridges; b; b=b->next)
2633 {
2634 printf("\t%02x.%d Bridge to %02x-%02x", b->dev, b->func, b->first, b->last);
2635 switch (b->bug)
2636 {
2637 case 1:
2638 printf(" <overlap bug>");
2639 break;
2640 case 2:
2641 printf(" <crossing bug>");
2642 break;
2643 }
2644 putchar('\n');
2645 }
2646 }
2647 }
2648
2649 static void
2650 map_the_bus(void)
2651 {
2652 if (pacc->method == PCI_ACCESS_PROC_BUS_PCI ||
2653 pacc->method == PCI_ACCESS_DUMP)
2654 printf("WARNING: Bus mapping can be reliable only with direct hardware access enabled.\n\n");
2655 bus_info = xmalloc(sizeof(struct bus_info) * 256);
2656 memset(bus_info, 0, sizeof(struct bus_info) * 256);
2657 if (filter.bus >= 0)
2658 do_map_bus(filter.bus);
2659 else
2660 {
2661 int bus;
2662 for(bus=0; bus<256; bus++)
2663 do_map_bus(bus);
2664 }
2665 map_bridges();
2666 }
2667
2668 /* Main */
2669
2670 int
2671 main(int argc, char **argv)
2672 {
2673 int i;
2674 char *msg;
2675
2676 if (argc == 2 && !strcmp(argv[1], "--version"))
2677 {
2678 puts("lspci version " PCIUTILS_VERSION);
2679 return 0;
2680 }
2681
2682 pacc = pci_alloc();
2683 pacc->error = die;
2684 pci_filter_init(pacc, &filter);
2685
2686 while ((i = getopt(argc, argv, options)) != -1)
2687 switch (i)
2688 {
2689 case 'n':
2690 pacc->numeric_ids++;
2691 break;
2692 case 'v':
2693 verbose++;
2694 break;
2695 case 'b':
2696 pacc->buscentric = 1;
2697 opt_buscentric = 1;
2698 break;
2699 case 's':
2700 if (msg = pci_filter_parse_slot(&filter, optarg))
2701 die("-s: %s", msg);
2702 break;
2703 case 'd':
2704 if (msg = pci_filter_parse_id(&filter, optarg))
2705 die("-d: %s", msg);
2706 break;
2707 case 'x':
2708 opt_hex++;
2709 break;
2710 case 't':
2711 opt_tree++;
2712 break;
2713 case 'i':
2714 pci_set_name_list_path(pacc, optarg, 0);
2715 break;
2716 case 'm':
2717 opt_machine++;
2718 break;
2719 case 'p':
2720 opt_pcimap = optarg;
2721 break;
2722 case 'k':
2723 opt_kernel++;
2724 break;
2725 case 'M':
2726 opt_map_mode++;
2727 break;
2728 case 'D':
2729 opt_domains = 2;
2730 break;
2731 default:
2732 if (parse_generic_option(i, pacc, optarg))
2733 break;
2734 bad:
2735 fprintf(stderr, help_msg, pacc->id_file_name);
2736 return 1;
2737 }
2738 if (optind < argc)
2739 goto bad;
2740
2741 /* FIXME */
2742 pacc->id_lookup_mode |= PCI_LOOKUP_NETWORK;
2743 pci_init(pacc);
2744 if (opt_map_mode)
2745 map_the_bus();
2746 else
2747 {
2748 scan_devices();
2749 sort_them();
2750 if (opt_tree)
2751 show_forest();
2752 else
2753 show();
2754 }
2755 pci_cleanup(pacc);
2756
2757 return (seen_errors ? 2 : 0);
2758 }
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