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setpci: Decorate trace() with PCI_PRINTF.
[thirdparty/pciutils.git] / lspci.c
1 /*
2 * The PCI Utilities -- List All PCI Devices
3 *
4 * Copyright (c) 1997--2008 Martin Mares <mj@ucw.cz>
5 *
6 * Can be freely distributed and used under the terms of the GNU GPL.
7 */
8
9 #include <stdio.h>
10 #include <string.h>
11 #include <stdlib.h>
12 #include <stdarg.h>
13 #include <unistd.h>
14
15 #define PCIUTILS_LSPCI
16 #include "pciutils.h"
17
18 /* Options */
19
20 static int verbose; /* Show detailed information */
21 static int opt_buscentric; /* Show bus addresses/IRQ's instead of CPU-visible ones */
22 static int opt_hex; /* Show contents of config space as hexadecimal numbers */
23 static struct pci_filter filter; /* Device filter */
24 static int opt_tree; /* Show bus tree */
25 static int opt_machine; /* Generate machine-readable output */
26 static int opt_map_mode; /* Bus mapping mode enabled */
27 static int opt_domains; /* Show domain numbers (0=disabled, 1=auto-detected, 2=requested) */
28 static int opt_kernel; /* Show kernel drivers */
29 static int opt_query_dns; /* Query the DNS (0=disabled, 1=enabled, 2=refresh cache) */
30 static int opt_query_all; /* Query the DNS for all entries */
31 static char *opt_pcimap; /* Override path to Linux modules.pcimap */
32
33 const char program_name[] = "lspci";
34
35 static char options[] = "nvbxs:d:ti:mgp:qkMDQ" GENERIC_OPTIONS ;
36
37 static char help_msg[] =
38 "Usage: lspci [<switches>]\n"
39 "\n"
40 "Basic display modes:\n"
41 "-mm\t\tProduce machine-readable output (single -m for an obsolete format)\n"
42 "-t\t\tShow bus tree\n"
43 "\n"
44 "Display options:\n"
45 "-v\t\tBe verbose (-vv for very verbose)\n"
46 #ifdef PCI_OS_LINUX
47 "-k\t\tShow kernel drivers handling each device\n"
48 #endif
49 "-x\t\tShow hex-dump of the standard part of the config space\n"
50 "-xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n"
51 "-xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n"
52 "-b\t\tBus-centric view (addresses and IRQ's as seen by the bus)\n"
53 "-D\t\tAlways show domain numbers\n"
54 "\n"
55 "Resolving of device ID's to names:\n"
56 "-n\t\tShow numeric ID's\n"
57 "-nn\t\tShow both textual and numeric ID's (names & numbers)\n"
58 #ifdef PCI_USE_DNS
59 "-q\t\tQuery the PCI ID database for unknown ID's via DNS\n"
60 "-qq\t\tAs above, but re-query locally cached entries\n"
61 "-Q\t\tQuery the PCI ID database for all ID's via DNS\n"
62 #endif
63 "\n"
64 "Selection of devices:\n"
65 "-s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n"
66 "-d [<vendor>]:[<device>]\t\t\tShow only devices with specified ID's\n"
67 "\n"
68 "Other options:\n"
69 "-i <file>\tUse specified ID database instead of %s\n"
70 #ifdef PCI_OS_LINUX
71 "-p <file>\tLook up kernel modules in a given file instead of default modules.pcimap\n"
72 #endif
73 "-M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
74 "\n"
75 "PCI access options:\n"
76 GENERIC_HELP
77 ;
78
79 /*** Communication with libpci ***/
80
81 static struct pci_access *pacc;
82
83 /*
84 * If we aren't being compiled by GCC, use xmalloc() instead of alloca().
85 * This increases our memory footprint, but only slightly since we don't
86 * use alloca() much.
87 */
88 #if defined (__FreeBSD__) || defined (__NetBSD__) || defined (__OpenBSD__) || defined (__DragonFly__)
89 /* alloca() is defined in stdlib.h */
90 #elif defined(__GNUC__) && !defined(PCI_OS_WINDOWS)
91 #include <alloca.h>
92 #else
93 #undef alloca
94 #define alloca xmalloc
95 #endif
96
97 /*** Our view of the PCI bus ***/
98
99 struct device {
100 struct device *next;
101 struct pci_dev *dev;
102 unsigned int config_cached, config_bufsize;
103 byte *config; /* Cached configuration space data */
104 byte *present; /* Maps which configuration bytes are present */
105 };
106
107 static struct device *first_dev;
108 static int seen_errors;
109
110 static int
111 config_fetch(struct device *d, unsigned int pos, unsigned int len)
112 {
113 unsigned int end = pos+len;
114 int result;
115
116 while (pos < d->config_bufsize && len && d->present[pos])
117 pos++, len--;
118 while (pos+len <= d->config_bufsize && len && d->present[pos+len-1])
119 len--;
120 if (!len)
121 return 1;
122
123 if (end > d->config_bufsize)
124 {
125 int orig_size = d->config_bufsize;
126 while (end > d->config_bufsize)
127 d->config_bufsize *= 2;
128 d->config = xrealloc(d->config, d->config_bufsize);
129 d->present = xrealloc(d->present, d->config_bufsize);
130 memset(d->present + orig_size, 0, d->config_bufsize - orig_size);
131 }
132 result = pci_read_block(d->dev, pos, d->config + pos, len);
133 if (result)
134 memset(d->present + pos, 1, len);
135 return result;
136 }
137
138 static struct device *
139 scan_device(struct pci_dev *p)
140 {
141 struct device *d;
142
143 if (p->domain && !opt_domains)
144 opt_domains = 1;
145 if (!pci_filter_match(&filter, p))
146 return NULL;
147 d = xmalloc(sizeof(struct device));
148 memset(d, 0, sizeof(*d));
149 d->dev = p;
150 d->config_cached = d->config_bufsize = 64;
151 d->config = xmalloc(64);
152 d->present = xmalloc(64);
153 memset(d->present, 1, 64);
154 if (!pci_read_block(p, 0, d->config, 64))
155 {
156 fprintf(stderr, "lspci: Unable to read the standard configuration space header of device %04x:%02x:%02x.%d\n",
157 p->domain, p->bus, p->dev, p->func);
158 seen_errors++;
159 return NULL;
160 }
161 if ((d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
162 {
163 /* For cardbus bridges, we need to fetch 64 bytes more to get the
164 * full standard header... */
165 if (config_fetch(d, 64, 64))
166 d->config_cached += 64;
167 }
168 pci_setup_cache(p, d->config, d->config_cached);
169 pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_CLASS | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES);
170 return d;
171 }
172
173 static void
174 scan_devices(void)
175 {
176 struct device *d;
177 struct pci_dev *p;
178
179 pci_scan_bus(pacc);
180 for (p=pacc->devices; p; p=p->next)
181 if (d = scan_device(p))
182 {
183 d->next = first_dev;
184 first_dev = d;
185 }
186 }
187
188 /*** Config space accesses ***/
189
190 static void
191 check_conf_range(struct device *d, unsigned int pos, unsigned int len)
192 {
193 while (len)
194 if (!d->present[pos])
195 die("Internal bug: Accessing non-read configuration byte at position %x", pos);
196 else
197 pos++, len--;
198 }
199
200 static inline byte
201 get_conf_byte(struct device *d, unsigned int pos)
202 {
203 check_conf_range(d, pos, 1);
204 return d->config[pos];
205 }
206
207 static word
208 get_conf_word(struct device *d, unsigned int pos)
209 {
210 check_conf_range(d, pos, 2);
211 return d->config[pos] | (d->config[pos+1] << 8);
212 }
213
214 static u32
215 get_conf_long(struct device *d, unsigned int pos)
216 {
217 check_conf_range(d, pos, 4);
218 return d->config[pos] |
219 (d->config[pos+1] << 8) |
220 (d->config[pos+2] << 16) |
221 (d->config[pos+3] << 24);
222 }
223
224 /*** Sorting ***/
225
226 static int
227 compare_them(const void *A, const void *B)
228 {
229 const struct pci_dev *a = (*(const struct device **)A)->dev;
230 const struct pci_dev *b = (*(const struct device **)B)->dev;
231
232 if (a->domain < b->domain)
233 return -1;
234 if (a->domain > b->domain)
235 return 1;
236 if (a->bus < b->bus)
237 return -1;
238 if (a->bus > b->bus)
239 return 1;
240 if (a->dev < b->dev)
241 return -1;
242 if (a->dev > b->dev)
243 return 1;
244 if (a->func < b->func)
245 return -1;
246 if (a->func > b->func)
247 return 1;
248 return 0;
249 }
250
251 static void
252 sort_them(void)
253 {
254 struct device **index, **h, **last_dev;
255 int cnt;
256 struct device *d;
257
258 cnt = 0;
259 for (d=first_dev; d; d=d->next)
260 cnt++;
261 h = index = alloca(sizeof(struct device *) * cnt);
262 for (d=first_dev; d; d=d->next)
263 *h++ = d;
264 qsort(index, cnt, sizeof(struct device *), compare_them);
265 last_dev = &first_dev;
266 h = index;
267 while (cnt--)
268 {
269 *last_dev = *h;
270 last_dev = &(*h)->next;
271 h++;
272 }
273 *last_dev = NULL;
274 }
275
276 /*** Normal output ***/
277
278 #define FLAG(x,y) ((x & y) ? '+' : '-')
279
280 static void
281 show_slot_name(struct device *d)
282 {
283 struct pci_dev *p = d->dev;
284
285 if (!opt_machine ? opt_domains : (p->domain || opt_domains >= 2))
286 printf("%04x:", p->domain);
287 printf("%02x:%02x.%d", p->bus, p->dev, p->func);
288 }
289
290 static void
291 get_subid(struct device *d, word *subvp, word *subdp)
292 {
293 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
294
295 if (htype == PCI_HEADER_TYPE_NORMAL)
296 {
297 *subvp = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
298 *subdp = get_conf_word(d, PCI_SUBSYSTEM_ID);
299 }
300 else if (htype == PCI_HEADER_TYPE_CARDBUS && d->config_cached >= 128)
301 {
302 *subvp = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
303 *subdp = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
304 }
305 else
306 *subvp = *subdp = 0xffff;
307 }
308
309 static void
310 show_terse(struct device *d)
311 {
312 int c;
313 struct pci_dev *p = d->dev;
314 char classbuf[128], devbuf[128];
315
316 show_slot_name(d);
317 printf(" %s: %s",
318 pci_lookup_name(pacc, classbuf, sizeof(classbuf),
319 PCI_LOOKUP_CLASS,
320 p->device_class),
321 pci_lookup_name(pacc, devbuf, sizeof(devbuf),
322 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
323 p->vendor_id, p->device_id));
324 if (c = get_conf_byte(d, PCI_REVISION_ID))
325 printf(" (rev %02x)", c);
326 if (verbose)
327 {
328 char *x;
329 c = get_conf_byte(d, PCI_CLASS_PROG);
330 x = pci_lookup_name(pacc, devbuf, sizeof(devbuf),
331 PCI_LOOKUP_PROGIF | PCI_LOOKUP_NO_NUMBERS,
332 p->device_class, c);
333 if (c || x)
334 {
335 printf(" (prog-if %02x", c);
336 if (x)
337 printf(" [%s]", x);
338 putchar(')');
339 }
340 }
341 putchar('\n');
342
343 if (verbose || opt_kernel)
344 {
345 word subsys_v, subsys_d;
346 char ssnamebuf[256];
347
348 get_subid(d, &subsys_v, &subsys_d);
349 if (subsys_v && subsys_v != 0xffff)
350 printf("\tSubsystem: %s\n",
351 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
352 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
353 p->vendor_id, p->device_id, subsys_v, subsys_d));
354 }
355 }
356
357 /*** Capabilities ***/
358
359 static void
360 cap_pm(struct device *d, int where, int cap)
361 {
362 int t, b;
363 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
364
365 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
366 if (verbose < 2)
367 return;
368 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
369 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
370 FLAG(cap, PCI_PM_CAP_DSI),
371 FLAG(cap, PCI_PM_CAP_D1),
372 FLAG(cap, PCI_PM_CAP_D2),
373 pm_aux_current[(cap >> 6) & 7],
374 FLAG(cap, PCI_PM_CAP_PME_D0),
375 FLAG(cap, PCI_PM_CAP_PME_D1),
376 FLAG(cap, PCI_PM_CAP_PME_D2),
377 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
378 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
379 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
380 return;
381 t = get_conf_word(d, where + PCI_PM_CTRL);
382 printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
383 t & PCI_PM_CTRL_STATE_MASK,
384 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
385 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
386 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
387 FLAG(t, PCI_PM_CTRL_PME_STATUS));
388 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
389 if (b)
390 printf("\t\tBridge: PM%c B3%c\n",
391 FLAG(t, PCI_PM_BPCC_ENABLE),
392 FLAG(~t, PCI_PM_PPB_B2_B3));
393 }
394
395 static void
396 format_agp_rate(int rate, char *buf, int agp3)
397 {
398 char *c = buf;
399 int i;
400
401 for (i=0; i<=2; i++)
402 if (rate & (1 << i))
403 {
404 if (c != buf)
405 *c++ = ',';
406 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
407 }
408 if (c != buf)
409 *c = 0;
410 else
411 strcpy(buf, "<none>");
412 }
413
414 static void
415 cap_agp(struct device *d, int where, int cap)
416 {
417 u32 t;
418 char rate[16];
419 int ver, rev;
420 int agp3 = 0;
421
422 ver = (cap >> 4) & 0x0f;
423 rev = cap & 0x0f;
424 printf("AGP version %x.%x\n", ver, rev);
425 if (verbose < 2)
426 return;
427 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
428 return;
429 t = get_conf_long(d, where + PCI_AGP_STATUS);
430 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
431 agp3 = 1;
432 format_agp_rate(t & 7, rate, agp3);
433 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
434 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
435 FLAG(t, PCI_AGP_STATUS_ISOCH),
436 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
437 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
438 FLAG(t, PCI_AGP_STATUS_SBA),
439 FLAG(t, PCI_AGP_STATUS_ITA_COH),
440 FLAG(t, PCI_AGP_STATUS_GART64),
441 FLAG(t, PCI_AGP_STATUS_HTRANS),
442 FLAG(t, PCI_AGP_STATUS_64BIT),
443 FLAG(t, PCI_AGP_STATUS_FW),
444 FLAG(t, PCI_AGP_STATUS_AGP3),
445 rate);
446 t = get_conf_long(d, where + PCI_AGP_COMMAND);
447 format_agp_rate(t & 7, rate, agp3);
448 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
449 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
450 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
451 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
452 FLAG(t, PCI_AGP_COMMAND_SBA),
453 FLAG(t, PCI_AGP_COMMAND_AGP),
454 FLAG(t, PCI_AGP_COMMAND_GART64),
455 FLAG(t, PCI_AGP_COMMAND_64BIT),
456 FLAG(t, PCI_AGP_COMMAND_FW),
457 rate);
458 }
459
460 static void
461 cap_pcix_nobridge(struct device *d, int where)
462 {
463 u16 command;
464 u32 status;
465 static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
466
467 printf("PCI-X non-bridge device\n");
468
469 if (verbose < 2)
470 return;
471
472 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
473 return;
474
475 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
476 status = get_conf_long(d, where + PCI_PCIX_STATUS);
477 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
478 FLAG(command, PCI_PCIX_COMMAND_DPERE),
479 FLAG(command, PCI_PCIX_COMMAND_ERO),
480 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
481 max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
482 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
483 ((status >> 8) & 0xff),
484 ((status >> 3) & 0x1f),
485 (status & PCI_PCIX_STATUS_FUNCTION),
486 FLAG(status, PCI_PCIX_STATUS_64BIT),
487 FLAG(status, PCI_PCIX_STATUS_133MHZ),
488 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
489 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
490 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
491 1 << (9 + ((status >> 21) & 3U)),
492 max_outstanding[(status >> 23) & 7U],
493 1 << (3 + ((status >> 26) & 7U)),
494 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
495 FLAG(status, PCI_PCIX_STATUS_266MHZ),
496 FLAG(status, PCI_PCIX_STATUS_533MHZ));
497 }
498
499 static void
500 cap_pcix_bridge(struct device *d, int where)
501 {
502 static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
503 u16 secstatus;
504 u32 status, upstcr, downstcr;
505
506 printf("PCI-X bridge device\n");
507
508 if (verbose < 2)
509 return;
510
511 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
512 return;
513
514 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
515 printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
516 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
517 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
518 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
519 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
520 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
521 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
522 sec_clock_freq[(secstatus >> 6) & 7]);
523 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
524 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
525 ((status >> 8) & 0xff),
526 ((status >> 3) & 0x1f),
527 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
528 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
529 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
530 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
531 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
532 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
533 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
534 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
535 printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
536 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
537 (upstcr >> 16) & 0xffff);
538 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
539 printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
540 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
541 (downstcr >> 16) & 0xffff);
542 }
543
544 static void
545 cap_pcix(struct device *d, int where)
546 {
547 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
548 {
549 case PCI_HEADER_TYPE_NORMAL:
550 cap_pcix_nobridge(d, where);
551 break;
552 case PCI_HEADER_TYPE_BRIDGE:
553 cap_pcix_bridge(d, where);
554 break;
555 }
556 }
557
558 static inline char *
559 ht_link_width(unsigned width)
560 {
561 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
562 return widths[width];
563 }
564
565 static inline char *
566 ht_link_freq(unsigned freq)
567 {
568 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
569 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
570 return freqs[freq];
571 }
572
573 static void
574 cap_ht_pri(struct device *d, int where, int cmd)
575 {
576 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
577 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
578 char *fmt;
579
580 printf("HyperTransport: Slave or Primary Interface\n");
581 if (verbose < 2)
582 return;
583
584 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
585 return;
586 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
587 if (rid < 0x22 && rid > 0x11)
588 printf("\t\t!!! Possibly incomplete decoding\n");
589
590 if (rid >= 0x22)
591 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
592 else
593 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
594 printf(fmt,
595 (cmd & PCI_HT_PRI_CMD_BUID),
596 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
597 FLAG(cmd, PCI_HT_PRI_CMD_MH),
598 FLAG(cmd, PCI_HT_PRI_CMD_DD),
599 FLAG(cmd, PCI_HT_PRI_CMD_DUL));
600 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
601 if (rid >= 0x22)
602 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
603 else
604 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
605 printf(fmt,
606 FLAG(lctr0, PCI_HT_LCTR_CFLE),
607 FLAG(lctr0, PCI_HT_LCTR_CST),
608 FLAG(lctr0, PCI_HT_LCTR_CFE),
609 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
610 FLAG(lctr0, PCI_HT_LCTR_INIT),
611 FLAG(lctr0, PCI_HT_LCTR_EOC),
612 FLAG(lctr0, PCI_HT_LCTR_TXO),
613 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
614 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
615 FLAG(lctr0, PCI_HT_LCTR_LSEN),
616 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
617 FLAG(lctr0, PCI_HT_LCTR_64B));
618 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
619 if (rid >= 0x22)
620 fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
621 else
622 fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
623 printf(fmt,
624 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
625 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
626 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
627 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
628 FLAG(lcnf0, PCI_HT_LCNF_DFI),
629 FLAG(lcnf0, PCI_HT_LCNF_DFO),
630 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
631 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
632 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
633 if (rid >= 0x22)
634 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
635 else
636 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
637 printf(fmt,
638 FLAG(lctr1, PCI_HT_LCTR_CFLE),
639 FLAG(lctr1, PCI_HT_LCTR_CST),
640 FLAG(lctr1, PCI_HT_LCTR_CFE),
641 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
642 FLAG(lctr1, PCI_HT_LCTR_INIT),
643 FLAG(lctr1, PCI_HT_LCTR_EOC),
644 FLAG(lctr1, PCI_HT_LCTR_TXO),
645 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
646 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
647 FLAG(lctr1, PCI_HT_LCTR_LSEN),
648 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
649 FLAG(lctr1, PCI_HT_LCTR_64B));
650 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
651 if (rid >= 0x22)
652 fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
653 else
654 fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
655 printf(fmt,
656 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
657 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
658 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
659 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
660 FLAG(lcnf1, PCI_HT_LCNF_DFI),
661 FLAG(lcnf1, PCI_HT_LCNF_DFO),
662 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
663 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
664 printf("\t\tRevision ID: %u.%02u\n",
665 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
666 if (rid < 0x22)
667 return;
668 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
669 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
670 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
671 FLAG(lfrer0, PCI_HT_LFRER_PROT),
672 FLAG(lfrer0, PCI_HT_LFRER_OV),
673 FLAG(lfrer0, PCI_HT_LFRER_EOC),
674 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
675 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
676 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
677 FLAG(lfcap0, PCI_HT_LFCAP_200),
678 FLAG(lfcap0, PCI_HT_LFCAP_300),
679 FLAG(lfcap0, PCI_HT_LFCAP_400),
680 FLAG(lfcap0, PCI_HT_LFCAP_500),
681 FLAG(lfcap0, PCI_HT_LFCAP_600),
682 FLAG(lfcap0, PCI_HT_LFCAP_800),
683 FLAG(lfcap0, PCI_HT_LFCAP_1000),
684 FLAG(lfcap0, PCI_HT_LFCAP_1200),
685 FLAG(lfcap0, PCI_HT_LFCAP_1400),
686 FLAG(lfcap0, PCI_HT_LFCAP_1600),
687 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
688 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
689 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
690 FLAG(ftr, PCI_HT_FTR_ISOCFC),
691 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
692 FLAG(ftr, PCI_HT_FTR_CRCTM),
693 FLAG(ftr, PCI_HT_FTR_ECTLT),
694 FLAG(ftr, PCI_HT_FTR_64BA),
695 FLAG(ftr, PCI_HT_FTR_UIDRD));
696 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
697 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
698 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
699 FLAG(lfrer1, PCI_HT_LFRER_PROT),
700 FLAG(lfrer1, PCI_HT_LFRER_OV),
701 FLAG(lfrer1, PCI_HT_LFRER_EOC),
702 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
703 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
704 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
705 FLAG(lfcap1, PCI_HT_LFCAP_200),
706 FLAG(lfcap1, PCI_HT_LFCAP_300),
707 FLAG(lfcap1, PCI_HT_LFCAP_400),
708 FLAG(lfcap1, PCI_HT_LFCAP_500),
709 FLAG(lfcap1, PCI_HT_LFCAP_600),
710 FLAG(lfcap1, PCI_HT_LFCAP_800),
711 FLAG(lfcap1, PCI_HT_LFCAP_1000),
712 FLAG(lfcap1, PCI_HT_LFCAP_1200),
713 FLAG(lfcap1, PCI_HT_LFCAP_1400),
714 FLAG(lfcap1, PCI_HT_LFCAP_1600),
715 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
716 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
717 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
718 FLAG(eh, PCI_HT_EH_PFLE),
719 FLAG(eh, PCI_HT_EH_OFLE),
720 FLAG(eh, PCI_HT_EH_PFE),
721 FLAG(eh, PCI_HT_EH_OFE),
722 FLAG(eh, PCI_HT_EH_EOCFE),
723 FLAG(eh, PCI_HT_EH_RFE),
724 FLAG(eh, PCI_HT_EH_CRCFE),
725 FLAG(eh, PCI_HT_EH_SERRFE),
726 FLAG(eh, PCI_HT_EH_CF),
727 FLAG(eh, PCI_HT_EH_RE),
728 FLAG(eh, PCI_HT_EH_PNFE),
729 FLAG(eh, PCI_HT_EH_ONFE),
730 FLAG(eh, PCI_HT_EH_EOCNFE),
731 FLAG(eh, PCI_HT_EH_RNFE),
732 FLAG(eh, PCI_HT_EH_CRCNFE),
733 FLAG(eh, PCI_HT_EH_SERRNFE));
734 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
735 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
736 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
737 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
738 printf("\t\tBus Number: %02x\n", bn);
739 }
740
741 static void
742 cap_ht_sec(struct device *d, int where, int cmd)
743 {
744 u16 lctr, lcnf, ftr, eh;
745 u8 rid, lfrer, lfcap, mbu, mlu;
746 char *fmt;
747
748 printf("HyperTransport: Host or Secondary Interface\n");
749 if (verbose < 2)
750 return;
751
752 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
753 return;
754 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
755 if (rid < 0x22 && rid > 0x11)
756 printf("\t\t!!! Possibly incomplete decoding\n");
757
758 if (rid >= 0x22)
759 fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
760 else
761 fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
762 printf(fmt,
763 FLAG(cmd, PCI_HT_SEC_CMD_WR),
764 FLAG(cmd, PCI_HT_SEC_CMD_DE),
765 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
766 FLAG(cmd, PCI_HT_SEC_CMD_CS),
767 FLAG(cmd, PCI_HT_SEC_CMD_HH),
768 FLAG(cmd, PCI_HT_SEC_CMD_AS),
769 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
770 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
771 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
772 if (rid >= 0x22)
773 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
774 else
775 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
776 printf(fmt,
777 FLAG(lctr, PCI_HT_LCTR_CFLE),
778 FLAG(lctr, PCI_HT_LCTR_CST),
779 FLAG(lctr, PCI_HT_LCTR_CFE),
780 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
781 FLAG(lctr, PCI_HT_LCTR_INIT),
782 FLAG(lctr, PCI_HT_LCTR_EOC),
783 FLAG(lctr, PCI_HT_LCTR_TXO),
784 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
785 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
786 FLAG(lctr, PCI_HT_LCTR_LSEN),
787 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
788 FLAG(lctr, PCI_HT_LCTR_64B));
789 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
790 if (rid >= 0x22)
791 fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
792 else
793 fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
794 printf(fmt,
795 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
796 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
797 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
798 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
799 FLAG(lcnf, PCI_HT_LCNF_DFI),
800 FLAG(lcnf, PCI_HT_LCNF_DFO),
801 FLAG(lcnf, PCI_HT_LCNF_DFIE),
802 FLAG(lcnf, PCI_HT_LCNF_DFOE));
803 printf("\t\tRevision ID: %u.%02u\n",
804 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
805 if (rid < 0x22)
806 return;
807 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
808 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
809 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
810 FLAG(lfrer, PCI_HT_LFRER_PROT),
811 FLAG(lfrer, PCI_HT_LFRER_OV),
812 FLAG(lfrer, PCI_HT_LFRER_EOC),
813 FLAG(lfrer, PCI_HT_LFRER_CTLT));
814 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
815 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
816 FLAG(lfcap, PCI_HT_LFCAP_200),
817 FLAG(lfcap, PCI_HT_LFCAP_300),
818 FLAG(lfcap, PCI_HT_LFCAP_400),
819 FLAG(lfcap, PCI_HT_LFCAP_500),
820 FLAG(lfcap, PCI_HT_LFCAP_600),
821 FLAG(lfcap, PCI_HT_LFCAP_800),
822 FLAG(lfcap, PCI_HT_LFCAP_1000),
823 FLAG(lfcap, PCI_HT_LFCAP_1200),
824 FLAG(lfcap, PCI_HT_LFCAP_1400),
825 FLAG(lfcap, PCI_HT_LFCAP_1600),
826 FLAG(lfcap, PCI_HT_LFCAP_VEND));
827 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
828 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
829 FLAG(ftr, PCI_HT_FTR_ISOCFC),
830 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
831 FLAG(ftr, PCI_HT_FTR_CRCTM),
832 FLAG(ftr, PCI_HT_FTR_ECTLT),
833 FLAG(ftr, PCI_HT_FTR_64BA),
834 FLAG(ftr, PCI_HT_FTR_UIDRD),
835 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
836 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
837 if (ftr & PCI_HT_SEC_FTR_EXTRS)
838 {
839 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
840 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
841 FLAG(eh, PCI_HT_EH_PFLE),
842 FLAG(eh, PCI_HT_EH_OFLE),
843 FLAG(eh, PCI_HT_EH_PFE),
844 FLAG(eh, PCI_HT_EH_OFE),
845 FLAG(eh, PCI_HT_EH_EOCFE),
846 FLAG(eh, PCI_HT_EH_RFE),
847 FLAG(eh, PCI_HT_EH_CRCFE),
848 FLAG(eh, PCI_HT_EH_SERRFE),
849 FLAG(eh, PCI_HT_EH_CF),
850 FLAG(eh, PCI_HT_EH_RE),
851 FLAG(eh, PCI_HT_EH_PNFE),
852 FLAG(eh, PCI_HT_EH_ONFE),
853 FLAG(eh, PCI_HT_EH_EOCNFE),
854 FLAG(eh, PCI_HT_EH_RNFE),
855 FLAG(eh, PCI_HT_EH_CRCNFE),
856 FLAG(eh, PCI_HT_EH_SERRNFE));
857 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
858 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
859 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
860 }
861 }
862
863 static void
864 cap_ht(struct device *d, int where, int cmd)
865 {
866 int type;
867
868 switch (cmd & PCI_HT_CMD_TYP_HI)
869 {
870 case PCI_HT_CMD_TYP_HI_PRI:
871 cap_ht_pri(d, where, cmd);
872 return;
873 case PCI_HT_CMD_TYP_HI_SEC:
874 cap_ht_sec(d, where, cmd);
875 return;
876 }
877
878 type = cmd & PCI_HT_CMD_TYP;
879 switch (type)
880 {
881 case PCI_HT_CMD_TYP_SW:
882 printf("HyperTransport: Switch\n");
883 break;
884 case PCI_HT_CMD_TYP_IDC:
885 printf("HyperTransport: Interrupt Discovery and Configuration\n");
886 break;
887 case PCI_HT_CMD_TYP_RID:
888 printf("HyperTransport: Revision ID: %u.%02u\n",
889 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
890 break;
891 case PCI_HT_CMD_TYP_UIDC:
892 printf("HyperTransport: UnitID Clumping\n");
893 break;
894 case PCI_HT_CMD_TYP_ECSA:
895 printf("HyperTransport: Extended Configuration Space Access\n");
896 break;
897 case PCI_HT_CMD_TYP_AM:
898 printf("HyperTransport: Address Mapping\n");
899 break;
900 case PCI_HT_CMD_TYP_MSIM:
901 printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
902 FLAG(cmd, PCI_HT_MSIM_CMD_EN),
903 FLAG(cmd, PCI_HT_MSIM_CMD_FIXD));
904 if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD))
905 {
906 u32 offl, offh;
907 if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8))
908 break;
909 offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO);
910 offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI);
911 printf("\t\tMapping Address Base: %016llx\n", ((unsigned long long)offh << 32) | (offl & ~0xfffff));
912 }
913 break;
914 case PCI_HT_CMD_TYP_DR:
915 printf("HyperTransport: DirectRoute\n");
916 break;
917 case PCI_HT_CMD_TYP_VCS:
918 printf("HyperTransport: VCSet\n");
919 break;
920 case PCI_HT_CMD_TYP_RM:
921 printf("HyperTransport: Retry Mode\n");
922 break;
923 case PCI_HT_CMD_TYP_X86:
924 printf("HyperTransport: X86 (reserved)\n");
925 break;
926 default:
927 printf("HyperTransport: #%02x\n", type >> 11);
928 }
929 }
930
931 static void
932 cap_msi(struct device *d, int where, int cap)
933 {
934 int is64;
935 u32 t;
936 u16 w;
937
938 printf("MSI: Mask%c 64bit%c Count=%d/%d Enable%c\n",
939 FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
940 FLAG(cap, PCI_MSI_FLAGS_64BIT),
941 1 << ((cap & PCI_MSI_FLAGS_QSIZE) >> 4),
942 1 << ((cap & PCI_MSI_FLAGS_QMASK) >> 1),
943 FLAG(cap, PCI_MSI_FLAGS_ENABLE));
944 if (verbose < 2)
945 return;
946 is64 = cap & PCI_MSI_FLAGS_64BIT;
947 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
948 return;
949 printf("\t\tAddress: ");
950 if (is64)
951 {
952 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
953 w = get_conf_word(d, where + PCI_MSI_DATA_64);
954 printf("%08x", t);
955 }
956 else
957 w = get_conf_word(d, where + PCI_MSI_DATA_32);
958 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
959 printf("%08x Data: %04x\n", t, w);
960 if (cap & PCI_MSI_FLAGS_MASK_BIT)
961 {
962 u32 mask, pending;
963
964 if (is64)
965 {
966 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8))
967 return;
968 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64);
969 pending = get_conf_long(d, where + PCI_MSI_PENDING_64);
970 }
971 else
972 {
973 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8))
974 return;
975 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32);
976 pending = get_conf_long(d, where + PCI_MSI_PENDING_32);
977 }
978 printf("\t\tMasking: %08x Pending: %08x\n", mask, pending);
979 }
980 }
981
982 static float power_limit(int value, int scale)
983 {
984 static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
985 return value * scales[scale];
986 }
987
988 static const char *latency_l0s(int value)
989 {
990 static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
991 return latencies[value];
992 }
993
994 static const char *latency_l1(int value)
995 {
996 static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
997 return latencies[value];
998 }
999
1000 static void cap_express_dev(struct device *d, int where, int type)
1001 {
1002 u32 t;
1003 u16 w;
1004
1005 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
1006 printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d, Latency L0s %s, L1 %s\n",
1007 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
1008 (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
1009 latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
1010 latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
1011 printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
1012 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
1013 (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
1014 printf(" AttnBtn%c AttnInd%c PwrInd%c",
1015 FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
1016 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
1017 printf(" RBE%c FLReset%c",
1018 FLAG(t, PCI_EXP_DEVCAP_RBE),
1019 FLAG(t, PCI_EXP_DEVCAP_FLRESET));
1020 if (type == PCI_EXP_TYPE_UPSTREAM)
1021 printf("SlotPowerLimit %fW",
1022 power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
1023 (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
1024 printf("\n");
1025
1026 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
1027 printf("\t\tDevCtl:\tReport errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
1028 FLAG(w, PCI_EXP_DEVCTL_CERE),
1029 FLAG(w, PCI_EXP_DEVCTL_NFERE),
1030 FLAG(w, PCI_EXP_DEVCTL_FERE),
1031 FLAG(w, PCI_EXP_DEVCTL_URRE));
1032 printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
1033 FLAG(w, PCI_EXP_DEVCTL_RELAXED),
1034 FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
1035 FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
1036 FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
1037 FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
1038 if (type == PCI_EXP_TYPE_PCI_BRIDGE || type == PCI_EXP_TYPE_PCIE_BRIDGE)
1039 printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
1040 if (type == PCI_EXP_TYPE_ENDPOINT && (t & PCI_EXP_DEVCAP_FLRESET))
1041 printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
1042 printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
1043 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
1044 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
1045
1046 w = get_conf_word(d, where + PCI_EXP_DEVSTA);
1047 printf("\t\tDevSta:\tCorrErr%c UncorrErr%c FatalErr%c UnsuppReq%c AuxPwr%c TransPend%c\n",
1048 FLAG(w, PCI_EXP_DEVSTA_CED),
1049 FLAG(w, PCI_EXP_DEVSTA_NFED),
1050 FLAG(w, PCI_EXP_DEVSTA_FED),
1051 FLAG(w, PCI_EXP_DEVSTA_URD),
1052 FLAG(w, PCI_EXP_DEVSTA_AUXPD),
1053 FLAG(w, PCI_EXP_DEVSTA_TRPND));
1054 }
1055
1056 static char *link_speed(int speed)
1057 {
1058 switch (speed)
1059 {
1060 case 1:
1061 return "2.5GT/s";
1062 case 2:
1063 return "5GT/s";
1064 default:
1065 return "unknown";
1066 }
1067 }
1068
1069 static char *aspm_support(int code)
1070 {
1071 switch (code)
1072 {
1073 case 1:
1074 return "L0s";
1075 case 3:
1076 return "L0s L1";
1077 default:
1078 return "unknown";
1079 }
1080 }
1081
1082 static const char *aspm_enabled(int code)
1083 {
1084 static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
1085 return desc[code];
1086 }
1087
1088 static void cap_express_link(struct device *d, int where, int type)
1089 {
1090 u32 t;
1091 u16 w;
1092
1093 t = get_conf_long(d, where + PCI_EXP_LNKCAP);
1094 printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s, Latency L0 %s, L1 %s\n",
1095 t >> 24,
1096 link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
1097 aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
1098 latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
1099 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
1100 printf("\t\t\tClockPM%c Suprise%c LLActRep%c BwNot%c\n",
1101 FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
1102 FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
1103 FLAG(t, PCI_EXP_LNKCAP_DLLA),
1104 FLAG(t, PCI_EXP_LNKCAP_LBNC));
1105
1106 w = get_conf_word(d, where + PCI_EXP_LNKCTL);
1107 printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
1108 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
1109 (type == PCI_EXP_TYPE_LEG_END))
1110 printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
1111 printf(" Disabled%c Retrain%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
1112 FLAG(w, PCI_EXP_LNKCTL_DISABLE),
1113 FLAG(w, PCI_EXP_LNKCTL_RETRAIN),
1114 FLAG(w, PCI_EXP_LNKCTL_CLOCK),
1115 FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
1116 FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
1117 FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
1118 FLAG(w, PCI_EXP_LNKCTL_BWMIE),
1119 FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
1120
1121 w = get_conf_word(d, where + PCI_EXP_LNKSTA);
1122 printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
1123 link_speed(w & PCI_EXP_LNKSTA_SPEED),
1124 (w & PCI_EXP_LNKSTA_WIDTH) >> 4,
1125 FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
1126 FLAG(w, PCI_EXP_LNKSTA_TRAIN),
1127 FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
1128 FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
1129 FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
1130 FLAG(w, PCI_EXP_LNKSTA_AUTBW));
1131 }
1132
1133 static const char *indicator(int code)
1134 {
1135 static const char *names[] = { "Unknown", "On", "Blink", "Off" };
1136 return names[code];
1137 }
1138
1139 static void cap_express_slot(struct device *d, int where)
1140 {
1141 u32 t;
1142 u16 w;
1143
1144 t = get_conf_long(d, where + PCI_EXP_SLTCAP);
1145 printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surpise%c\n",
1146 FLAG(t, PCI_EXP_SLTCAP_ATNB),
1147 FLAG(t, PCI_EXP_SLTCAP_PWRC),
1148 FLAG(t, PCI_EXP_SLTCAP_MRL),
1149 FLAG(t, PCI_EXP_SLTCAP_ATNI),
1150 FLAG(t, PCI_EXP_SLTCAP_PWRI),
1151 FLAG(t, PCI_EXP_SLTCAP_HPC),
1152 FLAG(t, PCI_EXP_SLTCAP_HPS));
1153 printf("\t\t\tSlot #%3x, PowerLimit %f; Interlock%c NoCompl%c\n",
1154 t >> 19,
1155 power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15),
1156 FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
1157 FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
1158
1159 w = get_conf_word(d, where + PCI_EXP_SLTCTL);
1160 printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
1161 FLAG(w, PCI_EXP_SLTCTL_ATNB),
1162 FLAG(w, PCI_EXP_SLTCTL_PWRF),
1163 FLAG(w, PCI_EXP_SLTCTL_MRLS),
1164 FLAG(w, PCI_EXP_SLTCTL_PRSD),
1165 FLAG(w, PCI_EXP_SLTCTL_CMDC),
1166 FLAG(w, PCI_EXP_SLTCTL_HPIE),
1167 FLAG(w, PCI_EXP_SLTCTL_LLCHG));
1168 printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
1169 indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
1170 indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
1171 FLAG(w, PCI_EXP_SLTCTL_PWRC),
1172 FLAG(w, PCI_EXP_SLTCTL_INTERLOCK));
1173
1174 w = get_conf_word(d, where + PCI_EXP_SLTSTA);
1175 printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
1176 FLAG(w, PCI_EXP_SLTSTA_ATNB),
1177 FLAG(w, PCI_EXP_SLTSTA_PWRF),
1178 FLAG(w, PCI_EXP_SLTSTA_MRL_ST),
1179 FLAG(w, PCI_EXP_SLTSTA_CMDC),
1180 FLAG(w, PCI_EXP_SLTSTA_PRES),
1181 FLAG(w, PCI_EXP_SLTSTA_INTERLOCK));
1182 printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
1183 FLAG(w, PCI_EXP_SLTSTA_MRLS),
1184 FLAG(w, PCI_EXP_SLTSTA_PRSD),
1185 FLAG(w, PCI_EXP_SLTSTA_LLCHG));
1186 }
1187
1188 static void cap_express_root(struct device *d, int where)
1189 {
1190 u32 w = get_conf_word(d, where + PCI_EXP_RTCTL);
1191 printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
1192 FLAG(w, PCI_EXP_RTCTL_SECEE),
1193 FLAG(w, PCI_EXP_RTCTL_SENFEE),
1194 FLAG(w, PCI_EXP_RTCTL_SEFEE),
1195 FLAG(w, PCI_EXP_RTCTL_PMEIE),
1196 FLAG(w, PCI_EXP_RTCTL_CRSVIS));
1197
1198 w = get_conf_word(d, where + PCI_EXP_RTCAP);
1199 printf("\t\tRootCap: CRSVisible%c\n",
1200 FLAG(w, PCI_EXP_RTCAP_CRSVIS));
1201
1202 w = get_conf_word(d, where + PCI_EXP_RTSTA);
1203 printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
1204 w & PCI_EXP_RTSTA_PME_REQID,
1205 FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
1206 FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
1207 }
1208
1209 static const char *cap_express_dev2_timeout_range(int type)
1210 {
1211 /* Decode Completion Timeout Ranges. */
1212 switch (type)
1213 {
1214 case 0:
1215 return "Not Supported";
1216 case 1:
1217 return "Range A";
1218 case 2:
1219 return "Range B";
1220 case 3:
1221 return "Range AB";
1222 case 6:
1223 return "Range BC";
1224 case 7:
1225 return "Range ABC";
1226 case 14:
1227 return "Range BCD";
1228 case 15:
1229 return "Range ABCD";
1230 default:
1231 return "Unknown";
1232 }
1233 }
1234
1235 static const char *cap_express_dev2_timeout_value(int type)
1236 {
1237 /* Decode Completion Timeout Value. */
1238 switch (type)
1239 {
1240 case 0:
1241 return "50us to 50ms";
1242 case 1:
1243 return "50us to 100us";
1244 case 2:
1245 return "1ms to 10ms";
1246 case 5:
1247 return "16ms to 55ms";
1248 case 6:
1249 return "65ms to 210ms";
1250 case 9:
1251 return "260ms to 900ms";
1252 case 10:
1253 return "1s to 3.5s";
1254 case 13:
1255 return "4s to 13s";
1256 case 14:
1257 return "17s to 64s";
1258 default:
1259 return "Unknown";
1260 }
1261 }
1262
1263 static void cap_express_dev2(struct device *d, int where, int type)
1264 {
1265 u32 l;
1266 u16 w;
1267
1268 l = get_conf_long(d, where + PCI_EXP_DEVCAP2);
1269 printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c",
1270 cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l)),
1271 FLAG(l, PCI_EXP_DEV2_TIMEOUT_DIS));
1272 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1273 printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEV2_ARI));
1274 else
1275 printf("\n");
1276
1277 w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
1278 printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c",
1279 cap_express_dev2_timeout_value(PCI_EXP_DEV2_TIMEOUT_VALUE(w)),
1280 FLAG(w, PCI_EXP_DEV2_TIMEOUT_DIS));
1281 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1282 printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEV2_ARI));
1283 else
1284 printf("\n");
1285 }
1286
1287 static const char *cap_express_link2_speed(int type)
1288 {
1289 switch (type)
1290 {
1291 case 0: /* hardwire to 0 means only the 2.5GT/s is supported */
1292 case 1:
1293 return "2.5GT/s";
1294 case 2:
1295 return "5GT/s";
1296 default:
1297 return "Unknown";
1298 }
1299 }
1300
1301 static const char *cap_express_link2_deemphasis(int type)
1302 {
1303 switch (type)
1304 {
1305 case 0:
1306 return "-6dB";
1307 case 1:
1308 return "-3.5dB";
1309 default:
1310 return "Unknown";
1311 }
1312 }
1313
1314 static const char *cap_express_link2_transmargin(int type)
1315 {
1316 switch (type)
1317 {
1318 case 0:
1319 return "Normal Operating Range";
1320 case 1:
1321 return "800-1200mV(full-swing)/400-700mV(half-swing)";
1322 case 2:
1323 case 3:
1324 case 4:
1325 case 5:
1326 return "200-400mV(full-swing)/100-200mV(half-swing)";
1327 default:
1328 return "Unknown";
1329 }
1330 }
1331
1332 static void cap_express_link2(struct device *d, int where, int type UNUSED)
1333 {
1334 u16 w;
1335
1336 w = get_conf_word(d, where + PCI_EXP_LNKCTL2);
1337 printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c, Selectable De-emphasis: %s\n"
1338 "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
1339 "\t\t\t Compliance De-emphasis: %s\n",
1340 cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)),
1341 FLAG(w, PCI_EXP_LNKCTL2_CMPLNC),
1342 FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS),
1343 cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w)),
1344 cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w)),
1345 FLAG(w, PCI_EXP_LNKCTL2_MOD_CMPLNC),
1346 FLAG(w, PCI_EXP_LNKCTL2_CMPLNC_SOS),
1347 cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w)));
1348
1349 w = get_conf_word(d, where + PCI_EXP_LNKSTA2);
1350 printf("\t\tLnkSta2: Current De-emphasis Level: %s\n",
1351 cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)));
1352 }
1353
1354 static void cap_express_slot2(struct device *d UNUSED, int where UNUSED)
1355 {
1356 /* No capabilities that require this field in PCIe rev2.0 spec. */
1357 }
1358
1359 static void
1360 cap_express(struct device *d, int where, int cap)
1361 {
1362 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1363 int size;
1364 int slot = 0;
1365
1366 printf("Express ");
1367 if (verbose >= 2)
1368 printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS);
1369 switch (type)
1370 {
1371 case PCI_EXP_TYPE_ENDPOINT:
1372 printf("Endpoint");
1373 break;
1374 case PCI_EXP_TYPE_LEG_END:
1375 printf("Legacy Endpoint");
1376 break;
1377 case PCI_EXP_TYPE_ROOT_PORT:
1378 slot = cap & PCI_EXP_FLAGS_SLOT;
1379 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1380 break;
1381 case PCI_EXP_TYPE_UPSTREAM:
1382 printf("Upstream Port");
1383 break;
1384 case PCI_EXP_TYPE_DOWNSTREAM:
1385 slot = cap & PCI_EXP_FLAGS_SLOT;
1386 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1387 break;
1388 case PCI_EXP_TYPE_PCI_BRIDGE:
1389 printf("PCI/PCI-X Bridge");
1390 break;
1391 case PCI_EXP_TYPE_PCIE_BRIDGE:
1392 printf("PCI/PCI-X to PCI-Express Bridge");
1393 break;
1394 case PCI_EXP_TYPE_ROOT_INT_EP:
1395 printf("Root Complex Integrated Endpoint");
1396 break;
1397 case PCI_EXP_TYPE_ROOT_EC:
1398 printf("Root Complex Event Collector");
1399 break;
1400 default:
1401 printf("Unknown type %d", type);
1402 }
1403 printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1404 if (verbose < 2)
1405 return;
1406
1407 size = 16;
1408 if (slot)
1409 size = 24;
1410 if (type == PCI_EXP_TYPE_ROOT_PORT)
1411 size = 32;
1412 if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1413 return;
1414
1415 cap_express_dev(d, where, type);
1416 cap_express_link(d, where, type);
1417 if (slot)
1418 cap_express_slot(d, where);
1419 if (type == PCI_EXP_TYPE_ROOT_PORT)
1420 cap_express_root(d, where);
1421
1422 if ((cap & PCI_EXP_FLAGS_VERS) < 2)
1423 return;
1424
1425 size = 16;
1426 if (slot)
1427 size = 24;
1428 if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size))
1429 return;
1430
1431 cap_express_dev2(d, where, type);
1432 cap_express_link2(d, where, type);
1433 if (slot)
1434 cap_express_slot2(d, where);
1435 }
1436
1437 static void
1438 cap_msix(struct device *d, int where, int cap)
1439 {
1440 u32 off;
1441
1442 printf("MSI-X: Enable%c Mask%c TabSize=%d\n",
1443 FLAG(cap, PCI_MSIX_ENABLE),
1444 FLAG(cap, PCI_MSIX_MASK),
1445 (cap & PCI_MSIX_TABSIZE) + 1);
1446 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1447 return;
1448
1449 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1450 printf("\t\tVector table: BAR=%d offset=%08x\n",
1451 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1452 off = get_conf_long(d, where + PCI_MSIX_PBA);
1453 printf("\t\tPBA: BAR=%d offset=%08x\n",
1454 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1455 }
1456
1457 static void
1458 cap_slotid(int cap)
1459 {
1460 int esr = cap & 0xff;
1461 int chs = cap >> 8;
1462
1463 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1464 esr & PCI_SID_ESR_NSLOTS,
1465 FLAG(esr, PCI_SID_ESR_FIC),
1466 chs);
1467 }
1468
1469 static void
1470 cap_ssvid(struct device *d, int where)
1471 {
1472 u16 subsys_v, subsys_d;
1473 char ssnamebuf[256];
1474
1475 if (!config_fetch(d, where, 8))
1476 return;
1477 subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR);
1478 subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE);
1479 printf("Subsystem: %s\n",
1480 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1481 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1482 d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d));
1483 }
1484
1485 static void
1486 cap_dsn(struct device *d, int where)
1487 {
1488 u32 t1, t2;
1489 if (!config_fetch(d, where + 4, 8))
1490 return;
1491 t1 = get_conf_long(d, where + 4);
1492 t2 = get_conf_long(d, where + 8);
1493 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
1494 t1 & 0xff, (t1 >> 8) & 0xff, (t1 >> 16) & 0xff, t1 >> 24,
1495 t2 & 0xff, (t2 >> 8) & 0xff, (t2 >> 16) & 0xff, t2 >> 24);
1496 }
1497
1498 static void
1499 cap_debug_port(int cap)
1500 {
1501 int bar = cap >> 13;
1502 int pos = cap & 0x1fff;
1503 printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
1504 }
1505
1506 static void
1507 cap_aer(struct device *d, int where)
1508 {
1509 u32 l;
1510
1511 printf("Advanced Error Reporting\n");
1512 if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 24))
1513 return;
1514
1515 l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS);
1516 printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
1517 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
1518 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
1519 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
1520 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
1521 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
1522 l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK);
1523 printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
1524 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
1525 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
1526 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
1527 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
1528 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
1529 l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER);
1530 printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
1531 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
1532 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
1533 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
1534 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
1535 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
1536 l = get_conf_long(d, where + PCI_ERR_COR_STATUS);
1537 printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n",
1538 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
1539 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
1540 l = get_conf_long(d, where + PCI_ERR_COR_MASK);
1541 printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n",
1542 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
1543 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
1544 l = get_conf_long(d, where + PCI_ERR_CAP);
1545 printf("\t\tAERCap:\tFirst Error Pointer: %02x, GenCap%c CGenEn%c ChkCap%c ChkEn%c\n",
1546 PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE),
1547 FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE));
1548
1549 }
1550
1551 static void
1552 cap_acs(struct device *d, int where)
1553 {
1554 u16 w;
1555
1556 printf("Access Control Services\n");
1557 if (!config_fetch(d, where + PCI_ACS_CAP, 4))
1558 return;
1559
1560 w = get_conf_word(d, where + PCI_ACS_CAP);
1561 printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
1562 "DirectTrans%c\n",
1563 FLAG(w, PCI_ACS_CAP_VALID), FLAG(w, PCI_ACS_CAP_BLOCK), FLAG(w, PCI_ACS_CAP_REQ_RED),
1564 FLAG(w, PCI_ACS_CAP_CMPLT_RED), FLAG(w, PCI_ACS_CAP_FORWARD), FLAG(w, PCI_ACS_CAP_EGRESS),
1565 FLAG(w, PCI_ACS_CAP_TRANS));
1566 w = get_conf_word(d, where + PCI_ACS_CTRL);
1567 printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
1568 "DirectTrans%c\n",
1569 FLAG(w, PCI_ACS_CTRL_VALID), FLAG(w, PCI_ACS_CTRL_BLOCK), FLAG(w, PCI_ACS_CTRL_REQ_RED),
1570 FLAG(w, PCI_ACS_CTRL_CMPLT_RED), FLAG(w, PCI_ACS_CTRL_FORWARD), FLAG(w, PCI_ACS_CTRL_EGRESS),
1571 FLAG(w, PCI_ACS_CTRL_TRANS));
1572 }
1573
1574 static void
1575 cap_ari(struct device *d, int where)
1576 {
1577 u16 w;
1578
1579 printf("Alternative Routing-ID Interpretation (ARI)\n");
1580 if (!config_fetch(d, where + PCI_ARI_CAP, 4))
1581 return;
1582
1583 w = get_conf_word(d, where + PCI_ARI_CAP);
1584 printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n",
1585 FLAG(w, PCI_ARI_CAP_MFVC), FLAG(w, PCI_ARI_CAP_ACS),
1586 PCI_ARI_CAP_NFN(w));
1587 w = get_conf_word(d, where + PCI_ARI_CTRL);
1588 printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n",
1589 FLAG(w, PCI_ARI_CTRL_MFVC), FLAG(w, PCI_ARI_CTRL_ACS),
1590 PCI_ARI_CTRL_FG(w));
1591 }
1592
1593 static void
1594 cap_ats(struct device *d, int where)
1595 {
1596 u16 w;
1597
1598 printf("Address Translation Service (ATS)\n");
1599 if (!config_fetch(d, where + PCI_ATS_CAP, 4))
1600 return;
1601
1602 w = get_conf_word(d, where + PCI_ATS_CAP);
1603 printf("\t\tATSCap:\tInvalidate Queue Depth: %02x\n", PCI_ATS_CAP_IQD(w));
1604 w = get_conf_word(d, where + PCI_ATS_CTRL);
1605 printf("\t\tATSCtl:\tEnable%c, Smallest Translation Unit: %02x\n",
1606 FLAG(w, PCI_ATS_CTRL_ENABLE), PCI_ATS_CTRL_STU(w));
1607 }
1608
1609 static void
1610 cap_sriov(struct device *d, int where)
1611 {
1612 u16 b;
1613 u16 w;
1614 u32 l;
1615
1616 printf("Single Root I/O Virtualization (SR-IOV)\n");
1617 if (!config_fetch(d, where + PCI_IOV_CAP, 0x3c))
1618 return;
1619
1620 l = get_conf_long(d, where + PCI_IOV_CAP);
1621 printf("\t\tIOVCap:\tMigration%c, Interrupt Message Number: %03x\n",
1622 FLAG(l, PCI_IOV_CAP_VFM), PCI_IOV_CAP_IMN(l));
1623 w = get_conf_word(d, where + PCI_IOV_CTRL);
1624 printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c\n",
1625 FLAG(w, PCI_IOV_CTRL_VFE), FLAG(w, PCI_IOV_CTRL_VFME),
1626 FLAG(w, PCI_IOV_CTRL_VFMIE), FLAG(w, PCI_IOV_CTRL_MSE),
1627 FLAG(w, PCI_IOV_CTRL_ARI));
1628 w = get_conf_word(d, where + PCI_IOV_STATUS);
1629 printf("\t\tIOVSta:\tMigration%c\n", FLAG(w, PCI_IOV_STATUS_MS));
1630 w = get_conf_word(d, where + PCI_IOV_INITIALVF);
1631 printf("\t\tInitial VFs: %d, ", w);
1632 w = get_conf_word(d, where + PCI_IOV_TOTALVF);
1633 printf("Total VFs: %d, ", w);
1634 w = get_conf_word(d, where + PCI_IOV_NUMVF);
1635 printf("Number of VFs: %d, ", w);
1636 b = get_conf_byte(d, where + PCI_IOV_FDL);
1637 printf("Function Dependency Link: %02x\n", b);
1638 w = get_conf_word(d, where + PCI_IOV_OFFSET);
1639 printf("\t\tVF offset: %d, ", w);
1640 w = get_conf_word(d, where + PCI_IOV_STRIDE);
1641 printf("stride: %d, ", w);
1642 w = get_conf_word(d, where + PCI_IOV_DID);
1643 printf("Device ID: %04x\n", w);
1644 l = get_conf_long(d, where + PCI_IOV_SUPPS);
1645 printf("\t\tSupported Page Size: %08x, ", l);
1646 l = get_conf_long(d, where + PCI_IOV_SYSPS);
1647 printf("System Page Size: %08x\n", l);
1648 printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l),
1649 PCI_IOV_MSA_BIR(l));
1650 }
1651
1652 static void
1653 show_ext_caps(struct device *d)
1654 {
1655 int where = 0x100;
1656 char been_there[0x1000];
1657 memset(been_there, 0, 0x1000);
1658 do
1659 {
1660 u32 header;
1661 int id;
1662
1663 if (!config_fetch(d, where, 4))
1664 break;
1665 header = get_conf_long(d, where);
1666 if (!header)
1667 break;
1668 id = header & 0xffff;
1669 printf("\tCapabilities: [%03x] ", where);
1670 if (been_there[where]++)
1671 {
1672 printf("<chain looped>\n");
1673 break;
1674 }
1675 switch (id)
1676 {
1677 case PCI_EXT_CAP_ID_AER:
1678 cap_aer(d, where);
1679 break;
1680 case PCI_EXT_CAP_ID_VC:
1681 printf("Virtual Channel <?>\n");
1682 break;
1683 case PCI_EXT_CAP_ID_DSN:
1684 cap_dsn(d, where);
1685 break;
1686 case PCI_EXT_CAP_ID_PB:
1687 printf("Power Budgeting <?>\n");
1688 break;
1689 case PCI_EXT_CAP_ID_RCLINK:
1690 printf("Root Complex Link <?>\n");
1691 break;
1692 case PCI_EXT_CAP_ID_RCILINK:
1693 printf("Root Complex Internal Link <?>\n");
1694 break;
1695 case PCI_EXT_CAP_ID_RCECOLL:
1696 printf("Root Complex Event Collector <?>\n");
1697 break;
1698 case PCI_EXT_CAP_ID_MFVC:
1699 printf("Multi-Function Virtual Channel <?>\n");
1700 break;
1701 case PCI_EXT_CAP_ID_RBCB:
1702 printf("Root Bridge Control Block <?>\n");
1703 break;
1704 case PCI_EXT_CAP_ID_VNDR:
1705 printf("Vendor Specific Information <?>\n");
1706 break;
1707 case PCI_EXT_CAP_ID_ACS:
1708 cap_acs(d, where);
1709 break;
1710 case PCI_EXT_CAP_ID_ARI:
1711 cap_ari(d, where);
1712 break;
1713 case PCI_EXT_CAP_ID_ATS:
1714 cap_ats(d, where);
1715 break;
1716 case PCI_EXT_CAP_ID_SRIOV:
1717 cap_sriov(d, where);
1718 break;
1719 default:
1720 printf("#%02x\n", id);
1721 break;
1722 }
1723 where = header >> 20;
1724 } while (where);
1725 }
1726
1727 static void
1728 show_caps(struct device *d)
1729 {
1730 int can_have_ext_caps = 0;
1731
1732 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1733 {
1734 int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
1735 byte been_there[256];
1736 memset(been_there, 0, 256);
1737 while (where)
1738 {
1739 int id, next, cap;
1740 printf("\tCapabilities: ");
1741 if (!config_fetch(d, where, 4))
1742 {
1743 puts("<access denied>");
1744 break;
1745 }
1746 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1747 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1748 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1749 printf("[%02x] ", where);
1750 if (been_there[where]++)
1751 {
1752 printf("<chain looped>\n");
1753 break;
1754 }
1755 if (id == 0xff)
1756 {
1757 printf("<chain broken>\n");
1758 break;
1759 }
1760 switch (id)
1761 {
1762 case PCI_CAP_ID_PM:
1763 cap_pm(d, where, cap);
1764 break;
1765 case PCI_CAP_ID_AGP:
1766 cap_agp(d, where, cap);
1767 break;
1768 case PCI_CAP_ID_VPD:
1769 printf("Vital Product Data <?>\n");
1770 break;
1771 case PCI_CAP_ID_SLOTID:
1772 cap_slotid(cap);
1773 break;
1774 case PCI_CAP_ID_MSI:
1775 cap_msi(d, where, cap);
1776 break;
1777 case PCI_CAP_ID_CHSWP:
1778 printf("CompactPCI hot-swap <?>\n");
1779 break;
1780 case PCI_CAP_ID_PCIX:
1781 cap_pcix(d, where);
1782 can_have_ext_caps = 1;
1783 break;
1784 case PCI_CAP_ID_HT:
1785 cap_ht(d, where, cap);
1786 break;
1787 case PCI_CAP_ID_VNDR:
1788 printf("Vendor Specific Information <?>\n");
1789 break;
1790 case PCI_CAP_ID_DBG:
1791 cap_debug_port(cap);
1792 break;
1793 case PCI_CAP_ID_CCRC:
1794 printf("CompactPCI central resource control <?>\n");
1795 break;
1796 case PCI_CAP_ID_HOTPLUG:
1797 printf("Hot-plug capable\n");
1798 break;
1799 case PCI_CAP_ID_SSVID:
1800 cap_ssvid(d, where);
1801 break;
1802 case PCI_CAP_ID_AGP3:
1803 printf("AGP3 <?>\n");
1804 break;
1805 case PCI_CAP_ID_SECURE:
1806 printf("Secure device <?>\n");
1807 break;
1808 case PCI_CAP_ID_EXP:
1809 cap_express(d, where, cap);
1810 can_have_ext_caps = 1;
1811 break;
1812 case PCI_CAP_ID_MSIX:
1813 cap_msix(d, where, cap);
1814 break;
1815 case PCI_CAP_ID_SATA:
1816 printf("SATA HBA <?>\n");
1817 break;
1818 case PCI_CAP_ID_AF:
1819 printf("PCIe advanced features <?>\n");
1820 break;
1821 default:
1822 printf("#%02x [%04x]\n", id, cap);
1823 }
1824 where = next;
1825 }
1826 }
1827 if (can_have_ext_caps)
1828 show_ext_caps(d);
1829 }
1830
1831 /*** Kernel drivers ***/
1832
1833 #ifdef PCI_OS_LINUX
1834
1835 #include <sys/utsname.h>
1836
1837 struct pcimap_entry {
1838 struct pcimap_entry *next;
1839 unsigned int vendor, device;
1840 unsigned int subvendor, subdevice;
1841 unsigned int class, class_mask;
1842 char module[1];
1843 };
1844
1845 static struct pcimap_entry *pcimap_head;
1846
1847 static void
1848 load_pcimap(void)
1849 {
1850 static int tried_pcimap;
1851 struct utsname uts;
1852 char *name, line[1024];
1853 FILE *f;
1854
1855 if (tried_pcimap)
1856 return;
1857 tried_pcimap = 1;
1858
1859 if (name = opt_pcimap)
1860 {
1861 f = fopen(name, "r");
1862 if (!f)
1863 die("Cannot open pcimap file %s: %m", name);
1864 }
1865 else
1866 {
1867 if (uname(&uts) < 0)
1868 die("uname() failed: %m");
1869 name = alloca(64 + strlen(uts.release));
1870 sprintf(name, "/lib/modules/%s/modules.pcimap", uts.release);
1871 f = fopen(name, "r");
1872 if (!f)
1873 return;
1874 }
1875
1876 while (fgets(line, sizeof(line), f))
1877 {
1878 char *c = strchr(line, '\n');
1879 struct pcimap_entry *e;
1880
1881 if (!c)
1882 die("Unterminated or too long line in %s", name);
1883 *c = 0;
1884 if (!line[0] || line[0] == '#')
1885 continue;
1886
1887 c = line;
1888 while (*c && *c != ' ' && *c != '\t')
1889 c++;
1890 if (!*c)
1891 continue; /* FIXME: Emit warnings! */
1892 *c++ = 0;
1893
1894 e = xmalloc(sizeof(*e) + strlen(line));
1895 if (sscanf(c, "%i%i%i%i%i%i",
1896 &e->vendor, &e->device,
1897 &e->subvendor, &e->subdevice,
1898 &e->class, &e->class_mask) != 6)
1899 continue;
1900 e->next = pcimap_head;
1901 pcimap_head = e;
1902 strcpy(e->module, line);
1903 }
1904 fclose(f);
1905 }
1906
1907 static int
1908 match_pcimap(struct device *d, struct pcimap_entry *e)
1909 {
1910 struct pci_dev *dev = d->dev;
1911 unsigned int class = get_conf_long(d, PCI_REVISION_ID) >> 8;
1912 word subv, subd;
1913
1914 #define MATCH(x, y) ((y) > 0xffff || (x) == (y))
1915 get_subid(d, &subv, &subd);
1916 return
1917 MATCH(dev->vendor_id, e->vendor) &&
1918 MATCH(dev->device_id, e->device) &&
1919 MATCH(subv, e->subvendor) &&
1920 MATCH(subd, e->subdevice) &&
1921 (class & e->class_mask) == e->class;
1922 #undef MATCH
1923 }
1924
1925 #define DRIVER_BUF_SIZE 1024
1926
1927 static char *
1928 find_driver(struct device *d, char *buf)
1929 {
1930 struct pci_dev *dev = d->dev;
1931 char name[1024], *drv, *base;
1932 int n;
1933
1934 if (dev->access->method != PCI_ACCESS_SYS_BUS_PCI)
1935 return NULL;
1936
1937 base = pci_get_param(dev->access, "sysfs.path");
1938 if (!base || !base[0])
1939 return NULL;
1940
1941 n = snprintf(name, sizeof(name), "%s/devices/%04x:%02x:%02x.%d/driver",
1942 base, dev->domain, dev->bus, dev->dev, dev->func);
1943 if (n < 0 || n >= (int)sizeof(name))
1944 die("show_driver: sysfs device name too long, why?");
1945
1946 n = readlink(name, buf, DRIVER_BUF_SIZE);
1947 if (n < 0)
1948 return NULL;
1949 if (n >= DRIVER_BUF_SIZE)
1950 return "<name-too-long>";
1951 buf[n] = 0;
1952
1953 if (drv = strrchr(buf, '/'))
1954 return drv+1;
1955 else
1956 return buf;
1957 }
1958
1959 static void
1960 show_kernel(struct device *d)
1961 {
1962 char buf[DRIVER_BUF_SIZE];
1963 char *driver;
1964 struct pcimap_entry *e, *last = NULL;
1965
1966 if (driver = find_driver(d, buf))
1967 printf("\tKernel driver in use: %s\n", driver);
1968
1969 load_pcimap();
1970 for (e=pcimap_head; e; e=e->next)
1971 if (match_pcimap(d, e) && (!last || strcmp(last->module, e->module)))
1972 {
1973 printf("%s %s", (last ? "," : "\tKernel modules:"), e->module);
1974 last = e;
1975 }
1976 if (last)
1977 putchar('\n');
1978 }
1979
1980 static void
1981 show_kernel_machine(struct device *d)
1982 {
1983 char buf[DRIVER_BUF_SIZE];
1984 char *driver;
1985 struct pcimap_entry *e, *last = NULL;
1986
1987 if (driver = find_driver(d, buf))
1988 printf("Driver:\t%s\n", driver);
1989
1990 load_pcimap();
1991 for (e=pcimap_head; e; e=e->next)
1992 if (match_pcimap(d, e) && (!last || strcmp(last->module, e->module)))
1993 {
1994 printf("Module:\t%s\n", e->module);
1995 last = e;
1996 }
1997 }
1998
1999 #else
2000
2001 static void
2002 show_kernel(struct device *d UNUSED)
2003 {
2004 }
2005
2006 static void
2007 show_kernel_machine(struct device *d UNUSED)
2008 {
2009 }
2010
2011 #endif
2012
2013 /*** Verbose output ***/
2014
2015 static void
2016 show_size(pciaddr_t x)
2017 {
2018 if (!x)
2019 return;
2020 printf(" [size=");
2021 if (x < 1024)
2022 printf("%d", (int) x);
2023 else if (x < 1048576)
2024 printf("%dK", (int)(x / 1024));
2025 else if (x < 0x80000000)
2026 printf("%dM", (int)(x / 1048576));
2027 else
2028 printf(PCIADDR_T_FMT, x);
2029 putchar(']');
2030 }
2031
2032 static void
2033 show_bases(struct device *d, int cnt)
2034 {
2035 struct pci_dev *p = d->dev;
2036 word cmd = get_conf_word(d, PCI_COMMAND);
2037 int i;
2038
2039 for (i=0; i<cnt; i++)
2040 {
2041 pciaddr_t pos = p->base_addr[i];
2042 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
2043 u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
2044 if (flg == 0xffffffff)
2045 flg = 0;
2046 if (!pos && !flg && !len)
2047 continue;
2048 if (verbose > 1)
2049 printf("\tRegion %d: ", i);
2050 else
2051 putchar('\t');
2052 if (pos && !flg) /* Reported by the OS, but not by the device */
2053 {
2054 printf("[virtual] ");
2055 flg = pos;
2056 }
2057 if (flg & PCI_BASE_ADDRESS_SPACE_IO)
2058 {
2059 pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
2060 printf("I/O ports at ");
2061 if (a)
2062 printf(PCIADDR_PORT_FMT, a);
2063 else if (flg & PCI_BASE_ADDRESS_IO_MASK)
2064 printf("<ignored>");
2065 else
2066 printf("<unassigned>");
2067 if (!(cmd & PCI_COMMAND_IO))
2068 printf(" [disabled]");
2069 }
2070 else
2071 {
2072 int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
2073 pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
2074 int done = 0;
2075 u32 z = 0;
2076
2077 printf("Memory at ");
2078 if (t == PCI_BASE_ADDRESS_MEM_TYPE_64)
2079 {
2080 if (i >= cnt - 1)
2081 {
2082 printf("<invalid-64bit-slot>");
2083 done = 1;
2084 }
2085 else
2086 {
2087 i++;
2088 z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
2089 if (opt_buscentric)
2090 {
2091 u32 y = a & 0xffffffff;
2092 if (a || z)
2093 printf("%08x%08x", z, y);
2094 else
2095 printf("<unassigned>");
2096 done = 1;
2097 }
2098 }
2099 }
2100 if (!done)
2101 {
2102 if (a)
2103 printf(PCIADDR_T_FMT, a);
2104 else
2105 printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "<ignored>" : "<unassigned>");
2106 }
2107 printf(" (%s, %sprefetchable)",
2108 (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
2109 (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
2110 (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
2111 (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
2112 if (!(cmd & PCI_COMMAND_MEMORY))
2113 printf(" [disabled]");
2114 }
2115 show_size(len);
2116 putchar('\n');
2117 }
2118 }
2119
2120 static void
2121 show_rom(struct device *d, int reg)
2122 {
2123 struct pci_dev *p = d->dev;
2124 pciaddr_t rom = p->rom_base_addr;
2125 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
2126 u32 flg = get_conf_long(d, reg);
2127 word cmd = get_conf_word(d, PCI_COMMAND);
2128
2129 if (!rom && !flg && !len)
2130 return;
2131 putchar('\t');
2132 if ((rom & PCI_ROM_ADDRESS_MASK) && !(flg & PCI_ROM_ADDRESS_MASK))
2133 {
2134 printf("[virtual] ");
2135 flg = rom;
2136 }
2137 printf("Expansion ROM at ");
2138 if (rom & PCI_ROM_ADDRESS_MASK)
2139 printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
2140 else if (flg & PCI_ROM_ADDRESS_MASK)
2141 printf("<ignored>");
2142 else
2143 printf("<unassigned>");
2144 if (!(flg & PCI_ROM_ADDRESS_ENABLE))
2145 printf(" [disabled]");
2146 else if (!(cmd & PCI_COMMAND_MEMORY))
2147 printf(" [disabled by cmd]");
2148 show_size(len);
2149 putchar('\n');
2150 }
2151
2152 static void
2153 show_htype0(struct device *d)
2154 {
2155 show_bases(d, 6);
2156 show_rom(d, PCI_ROM_ADDRESS);
2157 show_caps(d);
2158 }
2159
2160 static void
2161 show_htype1(struct device *d)
2162 {
2163 u32 io_base = get_conf_byte(d, PCI_IO_BASE);
2164 u32 io_limit = get_conf_byte(d, PCI_IO_LIMIT);
2165 u32 io_type = io_base & PCI_IO_RANGE_TYPE_MASK;
2166 u32 mem_base = get_conf_word(d, PCI_MEMORY_BASE);
2167 u32 mem_limit = get_conf_word(d, PCI_MEMORY_LIMIT);
2168 u32 mem_type = mem_base & PCI_MEMORY_RANGE_TYPE_MASK;
2169 u32 pref_base = get_conf_word(d, PCI_PREF_MEMORY_BASE);
2170 u32 pref_limit = get_conf_word(d, PCI_PREF_MEMORY_LIMIT);
2171 u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK;
2172 word sec_stat = get_conf_word(d, PCI_SEC_STATUS);
2173 word brc = get_conf_word(d, PCI_BRIDGE_CONTROL);
2174 int verb = verbose > 2;
2175
2176 show_bases(d, 2);
2177 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
2178 get_conf_byte(d, PCI_PRIMARY_BUS),
2179 get_conf_byte(d, PCI_SECONDARY_BUS),
2180 get_conf_byte(d, PCI_SUBORDINATE_BUS),
2181 get_conf_byte(d, PCI_SEC_LATENCY_TIMER));
2182
2183 if (io_type != (io_limit & PCI_IO_RANGE_TYPE_MASK) ||
2184 (io_type != PCI_IO_RANGE_TYPE_16 && io_type != PCI_IO_RANGE_TYPE_32))
2185 printf("\t!!! Unknown I/O range types %x/%x\n", io_base, io_limit);
2186 else
2187 {
2188 io_base = (io_base & PCI_IO_RANGE_MASK) << 8;
2189 io_limit = (io_limit & PCI_IO_RANGE_MASK) << 8;
2190 if (io_type == PCI_IO_RANGE_TYPE_32)
2191 {
2192 io_base |= (get_conf_word(d, PCI_IO_BASE_UPPER16) << 16);
2193 io_limit |= (get_conf_word(d, PCI_IO_LIMIT_UPPER16) << 16);
2194 }
2195 if (io_base <= io_limit || verb)
2196 printf("\tI/O behind bridge: %08x-%08x\n", io_base, io_limit+0xfff);
2197 }
2198
2199 if (mem_type != (mem_limit & PCI_MEMORY_RANGE_TYPE_MASK) ||
2200 mem_type)
2201 printf("\t!!! Unknown memory range types %x/%x\n", mem_base, mem_limit);
2202 else
2203 {
2204 mem_base = (mem_base & PCI_MEMORY_RANGE_MASK) << 16;
2205 mem_limit = (mem_limit & PCI_MEMORY_RANGE_MASK) << 16;
2206 if (mem_base <= mem_limit || verb)
2207 printf("\tMemory behind bridge: %08x-%08x\n", mem_base, mem_limit + 0xfffff);
2208 }
2209
2210 if (pref_type != (pref_limit & PCI_PREF_RANGE_TYPE_MASK) ||
2211 (pref_type != PCI_PREF_RANGE_TYPE_32 && pref_type != PCI_PREF_RANGE_TYPE_64))
2212 printf("\t!!! Unknown prefetchable memory range types %x/%x\n", pref_base, pref_limit);
2213 else
2214 {
2215 pref_base = (pref_base & PCI_PREF_RANGE_MASK) << 16;
2216 pref_limit = (pref_limit & PCI_PREF_RANGE_MASK) << 16;
2217 if (pref_base <= pref_limit || verb)
2218 {
2219 if (pref_type == PCI_PREF_RANGE_TYPE_32)
2220 printf("\tPrefetchable memory behind bridge: %08x-%08x\n", pref_base, pref_limit + 0xfffff);
2221 else
2222 printf("\tPrefetchable memory behind bridge: %08x%08x-%08x%08x\n",
2223 get_conf_long(d, PCI_PREF_BASE_UPPER32),
2224 pref_base,
2225 get_conf_long(d, PCI_PREF_LIMIT_UPPER32),
2226 pref_limit + 0xfffff);
2227 }
2228 }
2229
2230 if (verbose > 1)
2231 printf("\tSecondary status: 66MHz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c\n",
2232 FLAG(sec_stat, PCI_STATUS_66MHZ),
2233 FLAG(sec_stat, PCI_STATUS_FAST_BACK),
2234 FLAG(sec_stat, PCI_STATUS_PARITY),
2235 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
2236 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
2237 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
2238 FLAG(sec_stat, PCI_STATUS_SIG_TARGET_ABORT),
2239 FLAG(sec_stat, PCI_STATUS_REC_TARGET_ABORT),
2240 FLAG(sec_stat, PCI_STATUS_REC_MASTER_ABORT),
2241 FLAG(sec_stat, PCI_STATUS_SIG_SYSTEM_ERROR),
2242 FLAG(sec_stat, PCI_STATUS_DETECTED_PARITY));
2243
2244 show_rom(d, PCI_ROM_ADDRESS1);
2245
2246 if (verbose > 1)
2247 {
2248 printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
2249 FLAG(brc, PCI_BRIDGE_CTL_PARITY),
2250 FLAG(brc, PCI_BRIDGE_CTL_SERR),
2251 FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
2252 FLAG(brc, PCI_BRIDGE_CTL_VGA),
2253 FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
2254 FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
2255 FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
2256 printf("\t\tPriDiscTmr%c SecDiscTmr%c DiscTmrStat%c DiscTmrSERREn%c\n",
2257 FLAG(brc, PCI_BRIDGE_CTL_PRI_DISCARD_TIMER),
2258 FLAG(brc, PCI_BRIDGE_CTL_SEC_DISCARD_TIMER),
2259 FLAG(brc, PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS),
2260 FLAG(brc, PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN));
2261 }
2262
2263 show_caps(d);
2264 }
2265
2266 static void
2267 show_htype2(struct device *d)
2268 {
2269 int i;
2270 word cmd = get_conf_word(d, PCI_COMMAND);
2271 word brc = get_conf_word(d, PCI_CB_BRIDGE_CONTROL);
2272 word exca;
2273 int verb = verbose > 2;
2274
2275 show_bases(d, 1);
2276 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
2277 get_conf_byte(d, PCI_CB_PRIMARY_BUS),
2278 get_conf_byte(d, PCI_CB_CARD_BUS),
2279 get_conf_byte(d, PCI_CB_SUBORDINATE_BUS),
2280 get_conf_byte(d, PCI_CB_LATENCY_TIMER));
2281 for (i=0; i<2; i++)
2282 {
2283 int p = 8*i;
2284 u32 base = get_conf_long(d, PCI_CB_MEMORY_BASE_0 + p);
2285 u32 limit = get_conf_long(d, PCI_CB_MEMORY_LIMIT_0 + p);
2286 if (limit > base || verb)
2287 printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit,
2288 (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]",
2289 (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : "");
2290 }
2291 for (i=0; i<2; i++)
2292 {
2293 int p = 8*i;
2294 u32 base = get_conf_long(d, PCI_CB_IO_BASE_0 + p);
2295 u32 limit = get_conf_long(d, PCI_CB_IO_LIMIT_0 + p);
2296 if (!(base & PCI_IO_RANGE_TYPE_32))
2297 {
2298 base &= 0xffff;
2299 limit &= 0xffff;
2300 }
2301 base &= PCI_CB_IO_RANGE_MASK;
2302 limit = (limit & PCI_CB_IO_RANGE_MASK) + 3;
2303 if (base <= limit || verb)
2304 printf("\tI/O window %d: %08x-%08x%s\n", i, base, limit,
2305 (cmd & PCI_COMMAND_IO) ? "" : " [disabled]");
2306 }
2307
2308 if (get_conf_word(d, PCI_CB_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR)
2309 printf("\tSecondary status: SERR\n");
2310 if (verbose > 1)
2311 printf("\tBridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c\n",
2312 FLAG(brc, PCI_CB_BRIDGE_CTL_PARITY),
2313 FLAG(brc, PCI_CB_BRIDGE_CTL_SERR),
2314 FLAG(brc, PCI_CB_BRIDGE_CTL_ISA),
2315 FLAG(brc, PCI_CB_BRIDGE_CTL_VGA),
2316 FLAG(brc, PCI_CB_BRIDGE_CTL_MASTER_ABORT),
2317 FLAG(brc, PCI_CB_BRIDGE_CTL_CB_RESET),
2318 FLAG(brc, PCI_CB_BRIDGE_CTL_16BIT_INT),
2319 FLAG(brc, PCI_CB_BRIDGE_CTL_POST_WRITES));
2320
2321 if (d->config_cached < 128)
2322 {
2323 printf("\t<access denied to the rest>\n");
2324 return;
2325 }
2326
2327 exca = get_conf_word(d, PCI_CB_LEGACY_MODE_BASE);
2328 if (exca)
2329 printf("\t16-bit legacy interface ports at %04x\n", exca);
2330 }
2331
2332 static void
2333 show_verbose(struct device *d)
2334 {
2335 struct pci_dev *p = d->dev;
2336 word status = get_conf_word(d, PCI_STATUS);
2337 word cmd = get_conf_word(d, PCI_COMMAND);
2338 word class = p->device_class;
2339 byte bist = get_conf_byte(d, PCI_BIST);
2340 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
2341 byte latency = get_conf_byte(d, PCI_LATENCY_TIMER);
2342 byte cache_line = get_conf_byte(d, PCI_CACHE_LINE_SIZE);
2343 byte max_lat, min_gnt;
2344 byte int_pin = get_conf_byte(d, PCI_INTERRUPT_PIN);
2345 unsigned int irq = p->irq;
2346
2347 show_terse(d);
2348
2349 switch (htype)
2350 {
2351 case PCI_HEADER_TYPE_NORMAL:
2352 if (class == PCI_CLASS_BRIDGE_PCI)
2353 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
2354 max_lat = get_conf_byte(d, PCI_MAX_LAT);
2355 min_gnt = get_conf_byte(d, PCI_MIN_GNT);
2356 break;
2357 case PCI_HEADER_TYPE_BRIDGE:
2358 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
2359 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
2360 irq = int_pin = min_gnt = max_lat = 0;
2361 break;
2362 case PCI_HEADER_TYPE_CARDBUS:
2363 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
2364 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
2365 min_gnt = max_lat = 0;
2366 break;
2367 default:
2368 printf("\t!!! Unknown header type %02x\n", htype);
2369 return;
2370 }
2371
2372 if (verbose > 1)
2373 {
2374 printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c DisINTx%c\n",
2375 FLAG(cmd, PCI_COMMAND_IO),
2376 FLAG(cmd, PCI_COMMAND_MEMORY),
2377 FLAG(cmd, PCI_COMMAND_MASTER),
2378 FLAG(cmd, PCI_COMMAND_SPECIAL),
2379 FLAG(cmd, PCI_COMMAND_INVALIDATE),
2380 FLAG(cmd, PCI_COMMAND_VGA_PALETTE),
2381 FLAG(cmd, PCI_COMMAND_PARITY),
2382 FLAG(cmd, PCI_COMMAND_WAIT),
2383 FLAG(cmd, PCI_COMMAND_SERR),
2384 FLAG(cmd, PCI_COMMAND_FAST_BACK),
2385 FLAG(cmd, PCI_COMMAND_DISABLE_INTx));
2386 printf("\tStatus: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c INTx%c\n",
2387 FLAG(status, PCI_STATUS_CAP_LIST),
2388 FLAG(status, PCI_STATUS_66MHZ),
2389 FLAG(status, PCI_STATUS_UDF),
2390 FLAG(status, PCI_STATUS_FAST_BACK),
2391 FLAG(status, PCI_STATUS_PARITY),
2392 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
2393 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
2394 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
2395 FLAG(status, PCI_STATUS_SIG_TARGET_ABORT),
2396 FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
2397 FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
2398 FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
2399 FLAG(status, PCI_STATUS_DETECTED_PARITY),
2400 FLAG(status, PCI_STATUS_INTx));
2401 if (cmd & PCI_COMMAND_MASTER)
2402 {
2403 printf("\tLatency: %d", latency);
2404 if (min_gnt || max_lat)
2405 {
2406 printf(" (");
2407 if (min_gnt)
2408 printf("%dns min", min_gnt*250);
2409 if (min_gnt && max_lat)
2410 printf(", ");
2411 if (max_lat)
2412 printf("%dns max", max_lat*250);
2413 putchar(')');
2414 }
2415 if (cache_line)
2416 printf(", Cache Line Size: %d bytes", cache_line * 4);
2417 putchar('\n');
2418 }
2419 if (int_pin || irq)
2420 printf("\tInterrupt: pin %c routed to IRQ " PCIIRQ_FMT "\n",
2421 (int_pin ? 'A' + int_pin - 1 : '?'), irq);
2422 }
2423 else
2424 {
2425 printf("\tFlags: ");
2426 if (cmd & PCI_COMMAND_MASTER)
2427 printf("bus master, ");
2428 if (cmd & PCI_COMMAND_VGA_PALETTE)
2429 printf("VGA palette snoop, ");
2430 if (cmd & PCI_COMMAND_WAIT)
2431 printf("stepping, ");
2432 if (cmd & PCI_COMMAND_FAST_BACK)
2433 printf("fast Back2Back, ");
2434 if (status & PCI_STATUS_66MHZ)
2435 printf("66MHz, ");
2436 if (status & PCI_STATUS_UDF)
2437 printf("user-definable features, ");
2438 printf("%s devsel",
2439 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
2440 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
2441 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??");
2442 if (cmd & PCI_COMMAND_MASTER)
2443 printf(", latency %d", latency);
2444 if (irq)
2445 printf(", IRQ " PCIIRQ_FMT, irq);
2446 putchar('\n');
2447 }
2448
2449 if (bist & PCI_BIST_CAPABLE)
2450 {
2451 if (bist & PCI_BIST_START)
2452 printf("\tBIST is running\n");
2453 else
2454 printf("\tBIST result: %02x\n", bist & PCI_BIST_CODE_MASK);
2455 }
2456
2457 switch (htype)
2458 {
2459 case PCI_HEADER_TYPE_NORMAL:
2460 show_htype0(d);
2461 break;
2462 case PCI_HEADER_TYPE_BRIDGE:
2463 show_htype1(d);
2464 break;
2465 case PCI_HEADER_TYPE_CARDBUS:
2466 show_htype2(d);
2467 break;
2468 }
2469 }
2470
2471 /*** Machine-readable dumps ***/
2472
2473 static void
2474 show_hex_dump(struct device *d)
2475 {
2476 unsigned int i, cnt;
2477
2478 cnt = d->config_cached;
2479 if (opt_hex >= 3 && config_fetch(d, cnt, 256-cnt))
2480 {
2481 cnt = 256;
2482 if (opt_hex >= 4 && config_fetch(d, 256, 4096-256))
2483 cnt = 4096;
2484 }
2485
2486 for (i=0; i<cnt; i++)
2487 {
2488 if (! (i & 15))
2489 printf("%02x:", i);
2490 printf(" %02x", get_conf_byte(d, i));
2491 if ((i & 15) == 15)
2492 putchar('\n');
2493 }
2494 }
2495
2496 static void
2497 print_shell_escaped(char *c)
2498 {
2499 printf(" \"");
2500 while (*c)
2501 {
2502 if (*c == '"' || *c == '\\')
2503 putchar('\\');
2504 putchar(*c++);
2505 }
2506 putchar('"');
2507 }
2508
2509 static void
2510 show_machine(struct device *d)
2511 {
2512 struct pci_dev *p = d->dev;
2513 int c;
2514 word sv_id, sd_id;
2515 char classbuf[128], vendbuf[128], devbuf[128], svbuf[128], sdbuf[128];
2516
2517 get_subid(d, &sv_id, &sd_id);
2518
2519 if (verbose)
2520 {
2521 printf((opt_machine >= 2) ? "Slot:\t" : "Device:\t");
2522 show_slot_name(d);
2523 putchar('\n');
2524 printf("Class:\t%s\n",
2525 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
2526 printf("Vendor:\t%s\n",
2527 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
2528 printf("Device:\t%s\n",
2529 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
2530 if (sv_id && sv_id != 0xffff)
2531 {
2532 printf("SVendor:\t%s\n",
2533 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
2534 printf("SDevice:\t%s\n",
2535 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
2536 }
2537 if (c = get_conf_byte(d, PCI_REVISION_ID))
2538 printf("Rev:\t%02x\n", c);
2539 if (c = get_conf_byte(d, PCI_CLASS_PROG))
2540 printf("ProgIf:\t%02x\n", c);
2541 if (opt_kernel)
2542 show_kernel_machine(d);
2543 }
2544 else
2545 {
2546 show_slot_name(d);
2547 print_shell_escaped(pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
2548 print_shell_escaped(pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
2549 print_shell_escaped(pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
2550 if (c = get_conf_byte(d, PCI_REVISION_ID))
2551 printf(" -r%02x", c);
2552 if (c = get_conf_byte(d, PCI_CLASS_PROG))
2553 printf(" -p%02x", c);
2554 if (sv_id && sv_id != 0xffff)
2555 {
2556 print_shell_escaped(pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
2557 print_shell_escaped(pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
2558 }
2559 else
2560 printf(" \"\" \"\"");
2561 putchar('\n');
2562 }
2563 }
2564
2565 /*** Main show function ***/
2566
2567 static void
2568 show_device(struct device *d)
2569 {
2570 if (opt_machine)
2571 show_machine(d);
2572 else
2573 {
2574 if (verbose)
2575 show_verbose(d);
2576 else
2577 show_terse(d);
2578 if (opt_kernel || verbose)
2579 show_kernel(d);
2580 }
2581 if (opt_hex)
2582 show_hex_dump(d);
2583 if (verbose || opt_hex)
2584 putchar('\n');
2585 }
2586
2587 static void
2588 show(void)
2589 {
2590 struct device *d;
2591
2592 for (d=first_dev; d; d=d->next)
2593 show_device(d);
2594 }
2595
2596 /*** Tree output ***/
2597
2598 struct bridge {
2599 struct bridge *chain; /* Single-linked list of bridges */
2600 struct bridge *next, *child; /* Tree of bridges */
2601 struct bus *first_bus; /* List of buses connected to this bridge */
2602 unsigned int domain;
2603 unsigned int primary, secondary, subordinate; /* Bus numbers */
2604 struct device *br_dev;
2605 };
2606
2607 struct bus {
2608 unsigned int domain;
2609 unsigned int number;
2610 struct bus *sibling;
2611 struct device *first_dev, **last_dev;
2612 };
2613
2614 static struct bridge host_bridge = { NULL, NULL, NULL, NULL, 0, ~0, 0, ~0, NULL };
2615
2616 static struct bus *
2617 find_bus(struct bridge *b, unsigned int domain, unsigned int n)
2618 {
2619 struct bus *bus;
2620
2621 for (bus=b->first_bus; bus; bus=bus->sibling)
2622 if (bus->domain == domain && bus->number == n)
2623 break;
2624 return bus;
2625 }
2626
2627 static struct bus *
2628 new_bus(struct bridge *b, unsigned int domain, unsigned int n)
2629 {
2630 struct bus *bus = xmalloc(sizeof(struct bus));
2631 bus->domain = domain;
2632 bus->number = n;
2633 bus->sibling = b->first_bus;
2634 bus->first_dev = NULL;
2635 bus->last_dev = &bus->first_dev;
2636 b->first_bus = bus;
2637 return bus;
2638 }
2639
2640 static void
2641 insert_dev(struct device *d, struct bridge *b)
2642 {
2643 struct pci_dev *p = d->dev;
2644 struct bus *bus;
2645
2646 if (! (bus = find_bus(b, p->domain, p->bus)))
2647 {
2648 struct bridge *c;
2649 for (c=b->child; c; c=c->next)
2650 if (c->domain == p->domain && c->secondary <= p->bus && p->bus <= c->subordinate)
2651 {
2652 insert_dev(d, c);
2653 return;
2654 }
2655 bus = new_bus(b, p->domain, p->bus);
2656 }
2657 /* Simple insertion at the end _does_ guarantee the correct order as the
2658 * original device list was sorted by (domain, bus, devfn) lexicographically
2659 * and all devices on the new list have the same bus number.
2660 */
2661 *bus->last_dev = d;
2662 bus->last_dev = &d->next;
2663 d->next = NULL;
2664 }
2665
2666 static void
2667 grow_tree(void)
2668 {
2669 struct device *d, *d2;
2670 struct bridge **last_br, *b;
2671
2672 /* Build list of bridges */
2673
2674 last_br = &host_bridge.chain;
2675 for (d=first_dev; d; d=d->next)
2676 {
2677 word class = d->dev->device_class;
2678 byte ht = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
2679 if (class == PCI_CLASS_BRIDGE_PCI &&
2680 (ht == PCI_HEADER_TYPE_BRIDGE || ht == PCI_HEADER_TYPE_CARDBUS))
2681 {
2682 b = xmalloc(sizeof(struct bridge));
2683 b->domain = d->dev->domain;
2684 if (ht == PCI_HEADER_TYPE_BRIDGE)
2685 {
2686 b->primary = get_conf_byte(d, PCI_PRIMARY_BUS);
2687 b->secondary = get_conf_byte(d, PCI_SECONDARY_BUS);
2688 b->subordinate = get_conf_byte(d, PCI_SUBORDINATE_BUS);
2689 }
2690 else
2691 {
2692 b->primary = get_conf_byte(d, PCI_CB_PRIMARY_BUS);
2693 b->secondary = get_conf_byte(d, PCI_CB_CARD_BUS);
2694 b->subordinate = get_conf_byte(d, PCI_CB_SUBORDINATE_BUS);
2695 }
2696 *last_br = b;
2697 last_br = &b->chain;
2698 b->next = b->child = NULL;
2699 b->first_bus = NULL;
2700 b->br_dev = d;
2701 }
2702 }
2703 *last_br = NULL;
2704
2705 /* Create a bridge tree */
2706
2707 for (b=&host_bridge; b; b=b->chain)
2708 {
2709 struct bridge *c, *best;
2710 best = NULL;
2711 for (c=&host_bridge; c; c=c->chain)
2712 if (c != b && (c == &host_bridge || b->domain == c->domain) &&
2713 b->primary >= c->secondary && b->primary <= c->subordinate &&
2714 (!best || best->subordinate - best->primary > c->subordinate - c->primary))
2715 best = c;
2716 if (best)
2717 {
2718 b->next = best->child;
2719 best->child = b;
2720 }
2721 }
2722
2723 /* Insert secondary bus for each bridge */
2724
2725 for (b=&host_bridge; b; b=b->chain)
2726 if (!find_bus(b, b->domain, b->secondary))
2727 new_bus(b, b->domain, b->secondary);
2728
2729 /* Create bus structs and link devices */
2730
2731 for (d=first_dev; d;)
2732 {
2733 d2 = d->next;
2734 insert_dev(d, &host_bridge);
2735 d = d2;
2736 }
2737 }
2738
2739 static void
2740 print_it(char *line, char *p)
2741 {
2742 *p++ = '\n';
2743 *p = 0;
2744 fputs(line, stdout);
2745 for (p=line; *p; p++)
2746 if (*p == '+' || *p == '|')
2747 *p = '|';
2748 else
2749 *p = ' ';
2750 }
2751
2752 static void show_tree_bridge(struct bridge *, char *, char *);
2753
2754 static void
2755 show_tree_dev(struct device *d, char *line, char *p)
2756 {
2757 struct pci_dev *q = d->dev;
2758 struct bridge *b;
2759 char namebuf[256];
2760
2761 p += sprintf(p, "%02x.%x", q->dev, q->func);
2762 for (b=&host_bridge; b; b=b->chain)
2763 if (b->br_dev == d)
2764 {
2765 if (b->secondary == b->subordinate)
2766 p += sprintf(p, "-[%04x:%02x]-", b->domain, b->secondary);
2767 else
2768 p += sprintf(p, "-[%04x:%02x-%02x]-", b->domain, b->secondary, b->subordinate);
2769 show_tree_bridge(b, line, p);
2770 return;
2771 }
2772 if (verbose)
2773 p += sprintf(p, " %s",
2774 pci_lookup_name(pacc, namebuf, sizeof(namebuf),
2775 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
2776 q->vendor_id, q->device_id));
2777 print_it(line, p);
2778 }
2779
2780 static void
2781 show_tree_bus(struct bus *b, char *line, char *p)
2782 {
2783 if (!b->first_dev)
2784 print_it(line, p);
2785 else if (!b->first_dev->next)
2786 {
2787 *p++ = '-';
2788 *p++ = '-';
2789 show_tree_dev(b->first_dev, line, p);
2790 }
2791 else
2792 {
2793 struct device *d = b->first_dev;
2794 while (d->next)
2795 {
2796 p[0] = '+';
2797 p[1] = '-';
2798 show_tree_dev(d, line, p+2);
2799 d = d->next;
2800 }
2801 p[0] = '\\';
2802 p[1] = '-';
2803 show_tree_dev(d, line, p+2);
2804 }
2805 }
2806
2807 static void
2808 show_tree_bridge(struct bridge *b, char *line, char *p)
2809 {
2810 *p++ = '-';
2811 if (!b->first_bus->sibling)
2812 {
2813 if (b == &host_bridge)
2814 p += sprintf(p, "[%04x:%02x]-", b->domain, b->first_bus->number);
2815 show_tree_bus(b->first_bus, line, p);
2816 }
2817 else
2818 {
2819 struct bus *u = b->first_bus;
2820 char *k;
2821
2822 while (u->sibling)
2823 {
2824 k = p + sprintf(p, "+-[%04x:%02x]-", u->domain, u->number);
2825 show_tree_bus(u, line, k);
2826 u = u->sibling;
2827 }
2828 k = p + sprintf(p, "\\-[%04x:%02x]-", u->domain, u->number);
2829 show_tree_bus(u, line, k);
2830 }
2831 }
2832
2833 static void
2834 show_forest(void)
2835 {
2836 char line[256];
2837
2838 grow_tree();
2839 show_tree_bridge(&host_bridge, line, line);
2840 }
2841
2842 /*** Bus mapping mode ***/
2843
2844 struct bus_bridge {
2845 struct bus_bridge *next;
2846 byte this, dev, func, first, last, bug;
2847 };
2848
2849 struct bus_info {
2850 byte exists;
2851 byte guestbook;
2852 struct bus_bridge *bridges, *via;
2853 };
2854
2855 static struct bus_info *bus_info;
2856
2857 static void
2858 map_bridge(struct bus_info *bi, struct device *d, int np, int ns, int nl)
2859 {
2860 struct bus_bridge *b = xmalloc(sizeof(struct bus_bridge));
2861 struct pci_dev *p = d->dev;
2862
2863 b->next = bi->bridges;
2864 bi->bridges = b;
2865 b->this = get_conf_byte(d, np);
2866 b->dev = p->dev;
2867 b->func = p->func;
2868 b->first = get_conf_byte(d, ns);
2869 b->last = get_conf_byte(d, nl);
2870 printf("## %02x.%02x:%d is a bridge from %02x to %02x-%02x\n",
2871 p->bus, p->dev, p->func, b->this, b->first, b->last);
2872 if (b->this != p->bus)
2873 printf("!!! Bridge points to invalid primary bus.\n");
2874 if (b->first > b->last)
2875 {
2876 printf("!!! Bridge points to invalid bus range.\n");
2877 b->last = b->first;
2878 }
2879 }
2880
2881 static void
2882 do_map_bus(int bus)
2883 {
2884 int dev, func;
2885 int verbose = pacc->debugging;
2886 struct bus_info *bi = bus_info + bus;
2887 struct device *d;
2888
2889 if (verbose)
2890 printf("Mapping bus %02x\n", bus);
2891 for (dev = 0; dev < 32; dev++)
2892 if (filter.slot < 0 || filter.slot == dev)
2893 {
2894 int func_limit = 1;
2895 for (func = 0; func < func_limit; func++)
2896 if (filter.func < 0 || filter.func == func)
2897 {
2898 /* XXX: Bus mapping supports only domain 0 */
2899 struct pci_dev *p = pci_get_dev(pacc, 0, bus, dev, func);
2900 u16 vendor = pci_read_word(p, PCI_VENDOR_ID);
2901 if (vendor && vendor != 0xffff)
2902 {
2903 if (!func && (pci_read_byte(p, PCI_HEADER_TYPE) & 0x80))
2904 func_limit = 8;
2905 if (verbose)
2906 printf("Discovered device %02x:%02x.%d\n", bus, dev, func);
2907 bi->exists = 1;
2908 if (d = scan_device(p))
2909 {
2910 show_device(d);
2911 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
2912 {
2913 case PCI_HEADER_TYPE_BRIDGE:
2914 map_bridge(bi, d, PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS);
2915 break;
2916 case PCI_HEADER_TYPE_CARDBUS:
2917 map_bridge(bi, d, PCI_CB_PRIMARY_BUS, PCI_CB_CARD_BUS, PCI_CB_SUBORDINATE_BUS);
2918 break;
2919 }
2920 free(d);
2921 }
2922 else if (verbose)
2923 printf("But it was filtered out.\n");
2924 }
2925 pci_free_dev(p);
2926 }
2927 }
2928 }
2929
2930 static void
2931 do_map_bridges(int bus, int min, int max)
2932 {
2933 struct bus_info *bi = bus_info + bus;
2934 struct bus_bridge *b;
2935
2936 bi->guestbook = 1;
2937 for (b=bi->bridges; b; b=b->next)
2938 {
2939 if (bus_info[b->first].guestbook)
2940 b->bug = 1;
2941 else if (b->first < min || b->last > max)
2942 b->bug = 2;
2943 else
2944 {
2945 bus_info[b->first].via = b;
2946 do_map_bridges(b->first, b->first, b->last);
2947 }
2948 }
2949 }
2950
2951 static void
2952 map_bridges(void)
2953 {
2954 int i;
2955
2956 printf("\nSummary of buses:\n\n");
2957 for (i=0; i<256; i++)
2958 if (bus_info[i].exists && !bus_info[i].guestbook)
2959 do_map_bridges(i, 0, 255);
2960 for (i=0; i<256; i++)
2961 {
2962 struct bus_info *bi = bus_info + i;
2963 struct bus_bridge *b = bi->via;
2964
2965 if (bi->exists)
2966 {
2967 printf("%02x: ", i);
2968 if (b)
2969 printf("Entered via %02x:%02x.%d\n", b->this, b->dev, b->func);
2970 else if (!i)
2971 printf("Primary host bus\n");
2972 else
2973 printf("Secondary host bus (?)\n");
2974 }
2975 for (b=bi->bridges; b; b=b->next)
2976 {
2977 printf("\t%02x.%d Bridge to %02x-%02x", b->dev, b->func, b->first, b->last);
2978 switch (b->bug)
2979 {
2980 case 1:
2981 printf(" <overlap bug>");
2982 break;
2983 case 2:
2984 printf(" <crossing bug>");
2985 break;
2986 }
2987 putchar('\n');
2988 }
2989 }
2990 }
2991
2992 static void
2993 map_the_bus(void)
2994 {
2995 if (pacc->method == PCI_ACCESS_PROC_BUS_PCI ||
2996 pacc->method == PCI_ACCESS_DUMP)
2997 printf("WARNING: Bus mapping can be reliable only with direct hardware access enabled.\n\n");
2998 bus_info = xmalloc(sizeof(struct bus_info) * 256);
2999 memset(bus_info, 0, sizeof(struct bus_info) * 256);
3000 if (filter.bus >= 0)
3001 do_map_bus(filter.bus);
3002 else
3003 {
3004 int bus;
3005 for (bus=0; bus<256; bus++)
3006 do_map_bus(bus);
3007 }
3008 map_bridges();
3009 }
3010
3011 /* Main */
3012
3013 int
3014 main(int argc, char **argv)
3015 {
3016 int i;
3017 char *msg;
3018
3019 if (argc == 2 && !strcmp(argv[1], "--version"))
3020 {
3021 puts("lspci version " PCIUTILS_VERSION);
3022 return 0;
3023 }
3024
3025 pacc = pci_alloc();
3026 pacc->error = die;
3027 pci_filter_init(pacc, &filter);
3028
3029 while ((i = getopt(argc, argv, options)) != -1)
3030 switch (i)
3031 {
3032 case 'n':
3033 pacc->numeric_ids++;
3034 break;
3035 case 'v':
3036 verbose++;
3037 break;
3038 case 'b':
3039 pacc->buscentric = 1;
3040 opt_buscentric = 1;
3041 break;
3042 case 's':
3043 if (msg = pci_filter_parse_slot(&filter, optarg))
3044 die("-s: %s", msg);
3045 break;
3046 case 'd':
3047 if (msg = pci_filter_parse_id(&filter, optarg))
3048 die("-d: %s", msg);
3049 break;
3050 case 'x':
3051 opt_hex++;
3052 break;
3053 case 't':
3054 opt_tree++;
3055 break;
3056 case 'i':
3057 pci_set_name_list_path(pacc, optarg, 0);
3058 break;
3059 case 'm':
3060 opt_machine++;
3061 break;
3062 case 'p':
3063 opt_pcimap = optarg;
3064 break;
3065 #ifdef PCI_OS_LINUX
3066 case 'k':
3067 opt_kernel++;
3068 break;
3069 #endif
3070 case 'M':
3071 opt_map_mode++;
3072 break;
3073 case 'D':
3074 opt_domains = 2;
3075 break;
3076 #ifdef PCI_USE_DNS
3077 case 'q':
3078 opt_query_dns++;
3079 break;
3080 case 'Q':
3081 opt_query_all = 1;
3082 break;
3083 #else
3084 case 'q':
3085 case 'Q':
3086 die("DNS queries are not available in this version");
3087 #endif
3088 default:
3089 if (parse_generic_option(i, pacc, optarg))
3090 break;
3091 bad:
3092 fprintf(stderr, help_msg, pacc->id_file_name);
3093 return 1;
3094 }
3095 if (optind < argc)
3096 goto bad;
3097
3098 if (opt_query_dns)
3099 {
3100 pacc->id_lookup_mode |= PCI_LOOKUP_NETWORK;
3101 if (opt_query_dns > 1)
3102 pacc->id_lookup_mode |= PCI_LOOKUP_REFRESH_CACHE;
3103 }
3104 if (opt_query_all)
3105 pacc->id_lookup_mode |= PCI_LOOKUP_NETWORK | PCI_LOOKUP_SKIP_LOCAL;
3106
3107 pci_init(pacc);
3108 if (opt_map_mode)
3109 map_the_bus();
3110 else
3111 {
3112 scan_devices();
3113 sort_them();
3114 if (opt_tree)
3115 show_forest();
3116 else
3117 show();
3118 }
3119 pci_cleanup(pacc);
3120
3121 return (seen_errors ? 2 : 0);
3122 }
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