manual/platform.texi

   1 @node Platform, Contributors, Maintenance, Top
   2 @c %MENU% Describe all platform-specific facilities provided
   3 @appendix Platform-specific facilities
   4
   5 @Theglibc{} can provide machine-specific functionality.
   6
   7 @menu
   8 * PowerPC::           Facilities Specific to the PowerPC Architecture
   9 * RISC-V::            Facilities Specific to the RISC-V Architecture
  10 * X86::               Facilities Specific to the X86 Architecture
  11 @end menu
  12
  13 @node PowerPC
  14 @appendixsec PowerPC-specific Facilities
  15
  16 Facilities specific to PowerPC that are not specific to a particular
  17 operating system are declared in @file{sys/platform/ppc.h}.
  18
  19 @deftypefun {uint64_t} __ppc_get_timebase (void)
  20 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
  21 Read the current value of the Time Base Register.
  22
  23 The @dfn{Time Base Register} is a 64-bit register that stores a monotonically
  24 incremented value updated at a system-dependent frequency that may be
  25 different from the processor frequency.  More information is available in
  26 @cite{Power ISA 2.06b - Book II - Section 5.2}.
  27
  28 @code{__ppc_get_timebase} uses the processor's time base facility directly
  29 without requiring assistance from the operating system, so it is very
  30 efficient.
  31 @end deftypefun
  32
  33 @deftypefun {uint64_t} __ppc_get_timebase_freq (void)
  34 @safety{@prelim{}@mtunsafe{@mtuinit{}}@asunsafe{@asucorrupt{:init}}@acunsafe{@acucorrupt{:init}}}
  35 @c __ppc_get_timebase_freq=__get_timebase_freq @mtuinit @acsfd
  36 @c  __get_clockfreq @mtuinit @asucorrupt:init @acucorrupt:init @acsfd
  37 @c    the initialization of the static timebase_freq is not exactly
  38 @c    safe, because hp_timing_t cannot be atomically set up.
  39 @c   syscall:get_tbfreq ok
  40 @c   open dup @acsfd
  41 @c   read dup ok
  42 @c   memcpy dup ok
  43 @c   memmem dup ok
  44 @c   close dup @acsfd
  45 Read the current frequency at which the Time Base Register is updated.
  46
  47 This frequency is not related to the processor clock or the bus clock.
  48 It is also possible that this frequency is not constant.  More information is
  49 available in @cite{Power ISA 2.06b - Book II - Section 5.2}.
  50 @end deftypefun
  51
  52 The following functions provide hints about the usage of resources that are
  53 shared with other processors.  They can be used, for example, if a program
  54 waiting on a lock intends to divert the shared resources to be used by other
  55 processors.  More information is available in @cite{Power ISA 2.06b - Book II -
  56 Section 3.2}.
  57
  58 @deftypefun {void} __ppc_yield (void)
  59 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
  60 Provide a hint that performance will probably be improved if shared resources
  61 dedicated to the executing processor are released for use by other processors.
  62 @end deftypefun
  63
  64 @deftypefun {void} __ppc_mdoio (void)
  65 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
  66 Provide a hint that performance will probably be improved if shared resources
  67 dedicated to the executing processor are released until all outstanding storage
  68 accesses to caching-inhibited storage have been completed.
  69 @end deftypefun
  70
  71 @deftypefun {void} __ppc_mdoom (void)
  72 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
  73 Provide a hint that performance will probably be improved if shared resources
  74 dedicated to the executing processor are released until all outstanding storage
  75 accesses to cacheable storage for which the data is not in the cache have been
  76 completed.
  77 @end deftypefun
  78
  79 @deftypefun {void} __ppc_set_ppr_med (void)
  80 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
  81 Set the Program Priority Register to medium value (default).
  82
  83 The @dfn{Program Priority Register} (PPR) is a 64-bit register that controls
  84 the program's priority.  By adjusting the PPR value the programmer may
  85 improve system throughput by causing the system resources to be used
  86 more efficiently, especially in contention situations.
  87 The three unprivileged states available are covered by the functions
  88 @code{__ppc_set_ppr_med} (medium -- default), @code{__ppc_set_ppc_low} (low)
  89 and @code{__ppc_set_ppc_med_low} (medium low).  More information
  90 available in @cite{Power ISA 2.06b - Book II - Section 3.1}.
  91 @end deftypefun
  92
  93 @deftypefun {void} __ppc_set_ppr_low (void)
  94 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
  95 Set the Program Priority Register to low value.
  96 @end deftypefun
  97
  98 @deftypefun {void} __ppc_set_ppr_med_low (void)
  99 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
 100 Set the Program Priority Register to medium low value.
 101 @end deftypefun
 102
 103 Power ISA 2.07 extends the priorities that can be set to the Program Priority
 104 Register (PPR).  The following functions implement the new priority levels:
 105 very low and medium high.
 106
 107 @deftypefun {void} __ppc_set_ppr_very_low (void)
 108 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
 109 Set the Program Priority Register to very low value.
 110 @end deftypefun
 111
 112 @deftypefun {void} __ppc_set_ppr_med_high (void)
 113 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
 114 Set the Program Priority Register to medium high value.  The medium high
 115 priority is privileged and may only be set during certain time intervals by
 116 problem-state programs.  If the program priority is medium high when the time
 117 interval expires or if an attempt is made to set the priority to medium high
 118 when it is not allowed, the priority is set to medium.
 119 @end deftypefun
 120
 121 @node RISC-V
 122 @appendixsec RISC-V-specific Facilities
 123
 124 Cache management facilities specific to RISC-V systems that implement the Linux
 125 ABI are declared in @file{sys/cachectl.h}.
 126
 127 @deftypefun {void} __riscv_flush_icache (void *@var{start}, void *@var{end}, unsigned long int @var{flags})
 128 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
 129 Enforce ordering between stores and instruction cache fetches.  The range of
 130 addresses over which ordering is enforced is specified by @var{start} and
 131 @var{end}.  The @var{flags} argument controls the extent of this ordering, with
 132 the default behavior (a @var{flags} value of 0) being to enforce the fence on
 133 all threads in the current process.  Setting the
 134 @code{SYS_RISCV_FLUSH_ICACHE_LOCAL} bit allows users to indicate that enforcing
 135 ordering on only the current thread is necessary.  All other flag bits are
 136 reserved.
 137 @end deftypefun
 138
 139 @node X86
 140 @appendixsec X86-specific Facilities
 141
 142 Facilities specific to X86 that are not specific to a particular
 143 operating system are declared in @file{sys/platform/x86.h}.
 144
 145 @deftypefun {const struct cpuid_feature *} __x86_get_cpuid_feature_leaf (unsigned int @var{leaf})
 146 @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
 147 Return a pointer to x86 CPU feature structure used by query macros for x86
 148 CPU feature @var{leaf}.
 149 @end deftypefun
 150
 151 @deftypefn Macro int CPU_FEATURE_PRESENT (@var{name})
 152 This macro returns a nonzero value (true) if the processor has the feature
 153 @var{name}.
 154 @end deftypefn
 155
 156 @deftypefn Macro int CPU_FEATURE_ACTIVE (@var{name})
 157 This macro returns a nonzero value (true) if the processor has the feature
 158 @var{name} and the feature is active.  There may be other preconditions,
 159 like sufficient stack space or further setup for AMX, which must be
 160 satisfied before the feature can be used.
 161 @end deftypefn
 162
 163 The supported processor features are:
 164
 165 @itemize @bullet
 166
 167 @item
 168 @code{ACPI} -- Thermal Monitor and Software Controlled Clock Facilities.
 169
 170 @item
 171 @code{ADX} -- ADX instruction extensions.
 172
 173 @item
 174 @code{APIC} -- APIC On-Chip.
 175
 176 @item
 177 @code{AES} -- The AES instruction extensions.
 178
 179 @item
 180 @code{AESKLE} -- AES Key Locker instructions are enabled by OS.
 181
 182 @item
 183 @code{AMD_IBPB} -- Indirect branch predictor barrier (IBPB) for AMD cpus.
 184
 185 @item
 186 @code{AMD_IBRS} -- Indirect branch restricted speculation (IBPB) for AMD cpus.
 187
 188 @item
 189 @code{AMD_SSBD} -- Speculative Store Bypass Disable (SSBD) for AMD cpus.
 190
 191 @item
 192 @code{AMD_STIBP} -- Single thread indirect branch predictors (STIBP) for AMD cpus.
 193
 194 @item
 195 @code{AMD_VIRT_SSBD} -- Speculative Store Bypass Disable (SSBD) for AMD cpus (older systems).
 196
 197 @item
 198 @code{AMX_BF16} -- Tile computational operations on bfloat16 numbers.
 199
 200 @item
 201 @code{AMX_COMPLEX} -- Tile computational operations on complex FP16 numbers.
 202
 203 @item
 204 @code{AMX_INT8} -- Tile computational operations on 8-bit numbers.
 205
 206 @item
 207 @code{AMX_FP16} -- Tile computational operations on FP16 numbers.
 208
 209 @item
 210 @code{AMX_TILE} -- Tile architecture.
 211
 212 @item
 213 @code{ARCH_CAPABILITIES} -- IA32_ARCH_CAPABILITIES MSR.
 214
 215 @item
 216 @code{ArchPerfmonExt} -- Architectural Performance Monitoring Extended
 217 Leaf (EAX = 23H).
 218
 219 @item
 220 @code{AVX} -- The AVX instruction extensions.
 221
 222 @item
 223 @code{AVX2} -- The AVX2 instruction extensions.
 224
 225 @item
 226 @code{AVX_IFMA} -- The AVX-IFMA instruction extensions.
 227
 228 @item
 229 @code{AVX_NE_CONVERT} -- The AVX-NE-CONVERT instruction extensions.
 230
 231 @item
 232 @code{AVX_VNNI} -- The AVX-VNNI instruction extensions.
 233
 234 @item
 235 @code{AVX_VNNI_INT8} -- The AVX-VNNI-INT8 instruction extensions.
 236
 237 @item
 238 @code{AVX512_4FMAPS} -- The AVX512_4FMAPS instruction extensions.
 239
 240 @item
 241 @code{AVX512_4VNNIW} -- The AVX512_4VNNIW instruction extensions.
 242
 243 @item
 244 @code{AVX512_BF16} -- The AVX512_BF16 instruction extensions.
 245
 246 @item
 247 @code{AVX512_BITALG} -- The AVX512_BITALG instruction extensions.
 248
 249 @item
 250 @code{AVX512_FP16} -- The AVX512_FP16 instruction extensions.
 251
 252 @item
 253 @code{AVX512_IFMA} -- The AVX512_IFMA instruction extensions.
 254
 255 @item
 256 @code{AVX512_VBMI} -- The AVX512_VBMI instruction extensions.
 257
 258 @item
 259 @code{AVX512_VBMI2} -- The AVX512_VBMI2 instruction extensions.
 260
 261 @item
 262 @code{AVX512_VNNI} -- The AVX512_VNNI instruction extensions.
 263
 264 @item
 265 @code{AVX512_VP2INTERSECT} -- The AVX512_VP2INTERSECT instruction
 266 extensions.
 267
 268 @item
 269 @code{AVX512_VPOPCNTDQ} -- The AVX512_VPOPCNTDQ instruction extensions.
 270
 271 @item
 272 @code{AVX512BW} -- The AVX512BW instruction extensions.
 273
 274 @item
 275 @code{AVX512CD} -- The AVX512CD instruction extensions.
 276
 277 @item
 278 @code{AVX512ER} -- The AVX512ER instruction extensions.
 279
 280 @item
 281 @code{AVX512DQ} -- The AVX512DQ instruction extensions.
 282
 283 @item
 284 @code{AVX512F} -- The AVX512F instruction extensions.
 285
 286 @item
 287 @code{AVX512PF} -- The AVX512PF instruction extensions.
 288
 289 @item
 290 @code{AVX512VL} -- The AVX512VL instruction extensions.
 291
 292 @item
 293 @code{BMI1} -- BMI1 instructions.
 294
 295 @item
 296 @code{BMI2} -- BMI2 instructions.
 297
 298 @item
 299 @code{BUS_LOCK_DETECT} -- Bus lock debug exceptions.
 300
 301 @item
 302 @code{CLDEMOTE} -- CLDEMOTE instruction.
 303
 304 @item
 305 @code{CLFLUSHOPT} -- CLFLUSHOPT instruction.
 306
 307 @item
 308 @code{CLFSH} -- CLFLUSH instruction.
 309
 310 @item
 311 @code{CLWB} -- CLWB instruction.
 312
 313 @item
 314 @code{CMOV} -- Conditional Move instructions.
 315
 316 @item
 317 @code{CMPCCXADD} -- CMPccXADD instruction.
 318
 319 @item
 320 @code{CMPXCHG16B} -- CMPXCHG16B instruction.
 321
 322 @item
 323 @code{CNXT_ID} -- L1 Context ID.
 324
 325 @item
 326 @code{CORE_CAPABILITIES} -- IA32_CORE_CAPABILITIES MSR.
 327
 328 @item
 329 @code{CX8} -- CMPXCHG8B instruction.
 330
 331 @item
 332 @code{DCA} -- Data prefetch from a memory mapped device.
 333
 334 @item
 335 @code{DE} -- Debugging Extensions.
 336
 337 @item
 338 @code{DEPR_FPU_CS_DS} -- Deprecates FPU CS and FPU DS values.
 339
 340 @item
 341 @code{DS} -- Debug Store.
 342
 343 @item
 344 @code{DS_CPL} -- CPL Qualified Debug Store.
 345
 346 @item
 347 @code{DTES64} -- 64-bit DS Area.
 348
 349 @item
 350 @code{EIST} -- Enhanced Intel SpeedStep technology.
 351
 352 @item
 353 @code{ENQCMD} -- Enqueue Stores instructions.
 354
 355 @item
 356 @code{ERMS} -- Enhanced REP MOVSB/STOSB.
 357
 358 @item
 359 @code{F16C} -- 16-bit floating-point conversion instructions.
 360
 361 @item
 362 @code{FMA} -- FMA extensions using YMM state.
 363
 364 @item
 365 @code{FMA4} -- FMA4 instruction extensions.
 366
 367 @item
 368 @code{FPU} -- X87 Floating Point Unit On-Chip.
 369
 370 @item
 371 @code{FSGSBASE} -- RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instructions.
 372
 373 @item
 374 @code{FSRCS} -- Fast Short REP CMP and SCA.
 375
 376 @item
 377 @code{FSRM} -- Fast Short REP MOV.
 378
 379 @item
 380 @code{FSRS} -- Fast Short REP STO.
 381
 382 @item
 383 @code{FXSR} -- FXSAVE and FXRSTOR instructions.
 384
 385 @item
 386 @code{FZLRM} -- Fast Zero-Length REP MOV.
 387
 388 @item
 389 @code{GFNI} -- GFNI instruction extensions.
 390
 391 @item
 392 @code{HLE} -- HLE instruction extensions.
 393
 394 @item
 395 @code{HTT} -- Max APIC IDs reserved field is Valid.
 396
 397 @item
 398 @code{HRESET} -- History reset.
 399
 400 @item
 401 @code{HYBRID} -- Hybrid processor.
 402
 403 @item
 404 @code{IBRS_IBPB} -- Indirect branch restricted speculation (IBRS) and
 405 the indirect branch predictor barrier (IBPB).
 406
 407 @item
 408 @code{IBT} -- Intel Indirect Branch Tracking instruction extensions.
 409
 410 @item
 411 @code{INVARIANT_TSC} -- Invariant TSC.
 412
 413 @item
 414 @code{INVPCID} -- INVPCID instruction.
 415
 416 @item
 417 @code{KL} -- AES Key Locker instructions.
 418
 419 @item
 420 @code{L1D_FLUSH} -- IA32_FLUSH_CMD MSR.
 421
 422 @item
 423 @code{LA57} -- 57-bit linear addresses and five-level paging.
 424
 425 @item
 426 @code{LAHF64_SAHF64} -- LAHF/SAHF available in 64-bit mode.
 427
 428 @item
 429 @code{LAM} -- Linear Address Masking.
 430
 431 @item
 432 @code{LASS} -- Linear Address Space Separation.
 433
 434 @item
 435 @code{LBR} -- Architectural LBR.
 436
 437 @item
 438 @code{LM} -- Long mode.
 439
 440 @item
 441 @code{LWP} -- Lightweight profiling.
 442
 443 @item
 444 @code{LZCNT} -- LZCNT instruction.
 445
 446 @item
 447 @code{MCA} -- Machine Check Architecture.
 448
 449 @item
 450 @code{MCE} -- Machine Check Exception.
 451
 452 @item
 453 @code{MD_CLEAR} -- MD_CLEAR.
 454
 455 @item
 456 @code{MMX} -- Intel MMX Technology.
 457
 458 @item
 459 @code{MONITOR} --  MONITOR/MWAIT instructions.
 460
 461 @item
 462 @code{MOVBE} -- MOVBE instruction.
 463
 464 @item
 465 @code{MOVDIRI} -- MOVDIRI instruction.
 466
 467 @item
 468 @code{MOVDIR64B} -- MOVDIR64B instruction.
 469
 470 @item
 471 @code{MPX} -- Intel Memory Protection Extensions.
 472
 473 @item
 474 @code{MSR} -- Model Specific Registers RDMSR and WRMSR instructions.
 475
 476 @item
 477 @code{MSRLIST} -- RDMSRLIST/WRMSRLIST instructions and IA32_BARRIER
 478 MSR.
 479
 480 @item
 481 @code{MTRR} -- Memory Type Range Registers.
 482
 483 @item
 484 @code{NX} -- No-execute page protection.
 485
 486 @item
 487 @code{OSPKE} -- OS has set CR4.PKE to enable protection keys.
 488
 489 @item
 490 @code{OSXSAVE} -- The OS has set CR4.OSXSAVE[bit 18] to enable
 491 XSETBV/XGETBV instructions to access XCR0 and to support processor
 492 extended state management using XSAVE/XRSTOR.
 493
 494 @item
 495 @code{PAE} -- Physical Address Extension.
 496
 497 @item
 498 @code{PAGE1GB} -- 1-GByte page.
 499
 500 @item
 501 @code{PAT} -- Page Attribute Table.
 502
 503 @item
 504 @code{PBE} -- Pending Break Enable.
 505
 506 @item
 507 @code{PCID} -- Process-context identifiers.
 508
 509 @item
 510 @code{PCLMULQDQ} -- PCLMULQDQ instruction.
 511
 512 @item
 513 @code{PCONFIG} -- PCONFIG instruction.
 514
 515 @item
 516 @code{PDCM} -- Perfmon and Debug Capability.
 517
 518 @item
 519 @code{PGE} -- Page Global Bit.
 520
 521 @item
 522 @code{PKS} -- Protection keys for supervisor-mode pages.
 523
 524 @item
 525 @code{PKU} -- Protection keys for user-mode pages.
 526
 527 @item
 528 @code{POPCNT} -- POPCNT instruction.
 529
 530 @item
 531 @code{PREFETCHW} -- PREFETCHW instruction.
 532
 533 @item
 534 @code{PREFETCHWT1} -- PREFETCHWT1 instruction.
 535
 536 @item
 537 @code{PREFETCHI} -- PREFETCHIT0/1 instructions.
 538
 539 @item
 540 @code{PSE} -- Page Size Extension.
 541
 542 @item
 543 @code{PSE_36} -- 36-Bit Page Size Extension.
 544
 545 @item
 546 @code{PSN} -- Processor Serial Number.
 547
 548 @item
 549 @code{PTWRITE} -- PTWRITE instruction.
 550
 551 @item
 552 @code{RAO_INT} -- RAO-INT instructions.
 553
 554 @item
 555 @code{RDPID} -- RDPID instruction.
 556
 557 @item
 558 @code{RDRAND} -- RDRAND instruction.
 559
 560 @item
 561 @code{RDSEED} -- RDSEED instruction.
 562
 563 @item
 564 @code{RDT_A} -- Intel Resource Director Technology (Intel RDT) Allocation
 565 capability.
 566
 567 @item
 568 @code{RDT_M} -- Intel Resource Director Technology (Intel RDT) Monitoring
 569 capability.
 570
 571 @item
 572 @code{RDTSCP} -- RDTSCP instruction.
 573
 574 @item
 575 @code{RTM} -- RTM instruction extensions.
 576
 577 @item
 578 @code{RTM_ALWAYS_ABORT} -- Transactions always abort, making RTM unusable.
 579
 580 @item
 581 @code{RTM_FORCE_ABORT} -- TSX_FORCE_ABORT MSR.
 582
 583 @item
 584 @code{SDBG} -- IA32_DEBUG_INTERFACE MSR for silicon debug.
 585
 586 @item
 587 @code{SEP} -- SYSENTER and SYSEXIT instructions.
 588
 589 @item
 590 @code{SERIALIZE} -- SERIALIZE instruction.
 591
 592 @item
 593 @code{SGX} -- Intel Software Guard Extensions.
 594
 595 @item
 596 @code{SGX_KEYS} -- Attestation Services for SGX.
 597
 598 @item
 599 @code{SGX_LC} -- SGX Launch Configuration.
 600
 601 @item
 602 @code{SHA} -- SHA instruction extensions.
 603
 604 @item
 605 @code{SHSTK} -- Intel Shadow Stack instruction extensions.
 606
 607 @item
 608 @code{SMAP} -- Supervisor-Mode Access Prevention.
 609
 610 @item
 611 @code{SMEP} -- Supervisor-Mode Execution Prevention.
 612
 613 @item
 614 @code{SMX} -- Safer Mode Extensions.
 615
 616 @item
 617 @code{SS} -- Self Snoop.
 618
 619 @item
 620 @code{SSBD} -- Speculative Store Bypass Disable (SSBD).
 621
 622 @item
 623 @code{SSE} -- Streaming SIMD Extensions.
 624
 625 @item
 626 @code{SSE2} -- Streaming SIMD Extensions 2.
 627
 628 @item
 629 @code{SSE3} -- Streaming SIMD Extensions 3.
 630
 631 @item
 632 @code{SSE4_1} -- Streaming SIMD Extensions 4.1.
 633
 634 @item
 635 @code{SSE4_2} -- Streaming SIMD Extensions 4.2.
 636
 637 @item
 638 @code{SSE4A} -- SSE4A instruction extensions.
 639
 640 @item
 641 @code{SSSE3} -- Supplemental Streaming SIMD Extensions 3.
 642
 643 @item
 644 @code{STIBP} -- Single thread indirect branch predictors (STIBP).
 645
 646 @item
 647 @code{SVM} -- Secure Virtual Machine.
 648
 649 @item
 650 @code{SYSCALL_SYSRET} -- SYSCALL/SYSRET instructions.
 651
 652 @item
 653 @code{TBM} -- Trailing bit manipulation instructions.
 654
 655 @item
 656 @code{TM} -- Thermal Monitor.
 657
 658 @item
 659 @code{TM2} -- Thermal Monitor 2.
 660
 661 @item
 662 @code{TRACE} -- Intel Processor Trace.
 663
 664 @item
 665 @code{TSC} -- Time Stamp Counter.  RDTSC instruction.
 666
 667 @item
 668 @code{TSC_ADJUST} -- IA32_TSC_ADJUST MSR.
 669
 670 @item
 671 @code{TSC_DEADLINE} -- Local APIC timer supports one-shot operation
 672 using a TSC deadline value.
 673
 674 @item
 675 @code{TSXLDTRK} -- TSXLDTRK instructions.
 676
 677 @item
 678 @code{UINTR} -- User interrupts.
 679
 680 @item
 681 @code{UMIP} -- User-mode instruction prevention.
 682
 683 @item
 684 @code{VAES} -- VAES instruction extensions.
 685
 686 @item
 687 @code{VME} -- Virtual 8086 Mode Enhancements.
 688
 689 @item
 690 @code{VMX} -- Virtual Machine Extensions.
 691
 692 @item
 693 @code{VPCLMULQDQ} -- VPCLMULQDQ instruction.
 694
 695 @item
 696 @code{WAITPKG} -- WAITPKG instruction extensions.
 697
 698 @item
 699 @code{WBNOINVD} -- WBINVD/WBNOINVD instructions.
 700
 701 @item
 702 @code{WIDE_KL} -- AES wide Key Locker instructions.
 703
 704 @item
 705 @code{WRMSRNS} -- WRMSRNS instruction.
 706
 707 @item
 708 @code{X2APIC} -- x2APIC.
 709
 710 @item
 711 @code{XFD} -- Extended Feature Disable (XFD).
 712
 713 @item
 714 @code{XGETBV_ECX_1} -- XGETBV with ECX = 1.
 715
 716 @item
 717 @code{XOP} -- XOP instruction extensions.
 718
 719 @item
 720 @code{XSAVE} -- The XSAVE/XRSTOR processor extended states feature, the
 721 XSETBV/XGETBV instructions, and XCR0.
 722
 723 @item
 724 @code{XSAVEC} -- XSAVEC instruction.
 725
 726 @item
 727 @code{XSAVEOPT} -- XSAVEOPT instruction.
 728
 729 @item
 730 @code{XSAVES} -- XSAVES/XRSTORS instructions.
 731
 732 @item
 733 @code{XTPRUPDCTRL} -- xTPR Update Control.
 734
 735 @end itemize
 736
 737 You could query if a processor supports @code{AVX} with:
 738
 739 @smallexample
 740 #include <sys/platform/x86.h>
 741
 742 int
 743 avx_present (void)
 744 @{
 745   return CPU_FEATURE_PRESENT (AVX);
 746 @}
 747 @end smallexample
 748
 749 and if @code{AVX} is active and may be used with:
 750
 751 @smallexample
 752 #include <sys/platform/x86.h>
 753
 754 int
 755 avx_active (void)
 756 @{
 757   return CPU_FEATURE_ACTIVE (AVX);
 758 @}
 759 @end smallexample