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memory: Fix access_with_adjusted_size(small size) on big-endian memory regions
[thirdparty/qemu.git] / memory.c
1 /*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
14 */
15
16 #include "qemu/osdep.h"
17 #include "qapi/error.h"
18 #include "qemu-common.h"
19 #include "cpu.h"
20 #include "exec/memory.h"
21 #include "exec/address-spaces.h"
22 #include "qapi/visitor.h"
23 #include "qemu/bitops.h"
24 #include "qemu/error-report.h"
25 #include "qom/object.h"
26 #include "trace-root.h"
27
28 #include "exec/memory-internal.h"
29 #include "exec/ram_addr.h"
30 #include "sysemu/kvm.h"
31 #include "sysemu/sysemu.h"
32 #include "hw/qdev-properties.h"
33 #include "migration/vmstate.h"
34
35 //#define DEBUG_UNASSIGNED
36
37 static unsigned memory_region_transaction_depth;
38 static bool memory_region_update_pending;
39 static bool ioeventfd_update_pending;
40 static bool global_dirty_log = false;
41
42 static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
43 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
44
45 static QTAILQ_HEAD(, AddressSpace) address_spaces
46 = QTAILQ_HEAD_INITIALIZER(address_spaces);
47
48 static GHashTable *flat_views;
49
50 typedef struct AddrRange AddrRange;
51
52 /*
53 * Note that signed integers are needed for negative offsetting in aliases
54 * (large MemoryRegion::alias_offset).
55 */
56 struct AddrRange {
57 Int128 start;
58 Int128 size;
59 };
60
61 static AddrRange addrrange_make(Int128 start, Int128 size)
62 {
63 return (AddrRange) { start, size };
64 }
65
66 static bool addrrange_equal(AddrRange r1, AddrRange r2)
67 {
68 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
69 }
70
71 static Int128 addrrange_end(AddrRange r)
72 {
73 return int128_add(r.start, r.size);
74 }
75
76 static AddrRange addrrange_shift(AddrRange range, Int128 delta)
77 {
78 int128_addto(&range.start, delta);
79 return range;
80 }
81
82 static bool addrrange_contains(AddrRange range, Int128 addr)
83 {
84 return int128_ge(addr, range.start)
85 && int128_lt(addr, addrrange_end(range));
86 }
87
88 static bool addrrange_intersects(AddrRange r1, AddrRange r2)
89 {
90 return addrrange_contains(r1, r2.start)
91 || addrrange_contains(r2, r1.start);
92 }
93
94 static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
95 {
96 Int128 start = int128_max(r1.start, r2.start);
97 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
98 return addrrange_make(start, int128_sub(end, start));
99 }
100
101 enum ListenerDirection { Forward, Reverse };
102
103 #define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
104 do { \
105 MemoryListener *_listener; \
106 \
107 switch (_direction) { \
108 case Forward: \
109 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
110 if (_listener->_callback) { \
111 _listener->_callback(_listener, ##_args); \
112 } \
113 } \
114 break; \
115 case Reverse: \
116 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
117 memory_listeners, link) { \
118 if (_listener->_callback) { \
119 _listener->_callback(_listener, ##_args); \
120 } \
121 } \
122 break; \
123 default: \
124 abort(); \
125 } \
126 } while (0)
127
128 #define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
129 do { \
130 MemoryListener *_listener; \
131 struct memory_listeners_as *list = &(_as)->listeners; \
132 \
133 switch (_direction) { \
134 case Forward: \
135 QTAILQ_FOREACH(_listener, list, link_as) { \
136 if (_listener->_callback) { \
137 _listener->_callback(_listener, _section, ##_args); \
138 } \
139 } \
140 break; \
141 case Reverse: \
142 QTAILQ_FOREACH_REVERSE(_listener, list, memory_listeners_as, \
143 link_as) { \
144 if (_listener->_callback) { \
145 _listener->_callback(_listener, _section, ##_args); \
146 } \
147 } \
148 break; \
149 default: \
150 abort(); \
151 } \
152 } while (0)
153
154 /* No need to ref/unref .mr, the FlatRange keeps it alive. */
155 #define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
156 do { \
157 MemoryRegionSection mrs = section_from_flat_range(fr, \
158 address_space_to_flatview(as)); \
159 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
160 } while(0)
161
162 struct CoalescedMemoryRange {
163 AddrRange addr;
164 QTAILQ_ENTRY(CoalescedMemoryRange) link;
165 };
166
167 struct MemoryRegionIoeventfd {
168 AddrRange addr;
169 bool match_data;
170 uint64_t data;
171 EventNotifier *e;
172 };
173
174 static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a,
175 MemoryRegionIoeventfd *b)
176 {
177 if (int128_lt(a->addr.start, b->addr.start)) {
178 return true;
179 } else if (int128_gt(a->addr.start, b->addr.start)) {
180 return false;
181 } else if (int128_lt(a->addr.size, b->addr.size)) {
182 return true;
183 } else if (int128_gt(a->addr.size, b->addr.size)) {
184 return false;
185 } else if (a->match_data < b->match_data) {
186 return true;
187 } else if (a->match_data > b->match_data) {
188 return false;
189 } else if (a->match_data) {
190 if (a->data < b->data) {
191 return true;
192 } else if (a->data > b->data) {
193 return false;
194 }
195 }
196 if (a->e < b->e) {
197 return true;
198 } else if (a->e > b->e) {
199 return false;
200 }
201 return false;
202 }
203
204 static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a,
205 MemoryRegionIoeventfd *b)
206 {
207 return !memory_region_ioeventfd_before(a, b)
208 && !memory_region_ioeventfd_before(b, a);
209 }
210
211 /* Range of memory in the global map. Addresses are absolute. */
212 struct FlatRange {
213 MemoryRegion *mr;
214 hwaddr offset_in_region;
215 AddrRange addr;
216 uint8_t dirty_log_mask;
217 bool romd_mode;
218 bool readonly;
219 };
220
221 #define FOR_EACH_FLAT_RANGE(var, view) \
222 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
223
224 static inline MemoryRegionSection
225 section_from_flat_range(FlatRange *fr, FlatView *fv)
226 {
227 return (MemoryRegionSection) {
228 .mr = fr->mr,
229 .fv = fv,
230 .offset_within_region = fr->offset_in_region,
231 .size = fr->addr.size,
232 .offset_within_address_space = int128_get64(fr->addr.start),
233 .readonly = fr->readonly,
234 };
235 }
236
237 static bool flatrange_equal(FlatRange *a, FlatRange *b)
238 {
239 return a->mr == b->mr
240 && addrrange_equal(a->addr, b->addr)
241 && a->offset_in_region == b->offset_in_region
242 && a->romd_mode == b->romd_mode
243 && a->readonly == b->readonly;
244 }
245
246 static FlatView *flatview_new(MemoryRegion *mr_root)
247 {
248 FlatView *view;
249
250 view = g_new0(FlatView, 1);
251 view->ref = 1;
252 view->root = mr_root;
253 memory_region_ref(mr_root);
254 trace_flatview_new(view, mr_root);
255
256 return view;
257 }
258
259 /* Insert a range into a given position. Caller is responsible for maintaining
260 * sorting order.
261 */
262 static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
263 {
264 if (view->nr == view->nr_allocated) {
265 view->nr_allocated = MAX(2 * view->nr, 10);
266 view->ranges = g_realloc(view->ranges,
267 view->nr_allocated * sizeof(*view->ranges));
268 }
269 memmove(view->ranges + pos + 1, view->ranges + pos,
270 (view->nr - pos) * sizeof(FlatRange));
271 view->ranges[pos] = *range;
272 memory_region_ref(range->mr);
273 ++view->nr;
274 }
275
276 static void flatview_destroy(FlatView *view)
277 {
278 int i;
279
280 trace_flatview_destroy(view, view->root);
281 if (view->dispatch) {
282 address_space_dispatch_free(view->dispatch);
283 }
284 for (i = 0; i < view->nr; i++) {
285 memory_region_unref(view->ranges[i].mr);
286 }
287 g_free(view->ranges);
288 memory_region_unref(view->root);
289 g_free(view);
290 }
291
292 static bool flatview_ref(FlatView *view)
293 {
294 return atomic_fetch_inc_nonzero(&view->ref) > 0;
295 }
296
297 void flatview_unref(FlatView *view)
298 {
299 if (atomic_fetch_dec(&view->ref) == 1) {
300 trace_flatview_destroy_rcu(view, view->root);
301 assert(view->root);
302 call_rcu(view, flatview_destroy, rcu);
303 }
304 }
305
306 static bool can_merge(FlatRange *r1, FlatRange *r2)
307 {
308 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
309 && r1->mr == r2->mr
310 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
311 r1->addr.size),
312 int128_make64(r2->offset_in_region))
313 && r1->dirty_log_mask == r2->dirty_log_mask
314 && r1->romd_mode == r2->romd_mode
315 && r1->readonly == r2->readonly;
316 }
317
318 /* Attempt to simplify a view by merging adjacent ranges */
319 static void flatview_simplify(FlatView *view)
320 {
321 unsigned i, j;
322
323 i = 0;
324 while (i < view->nr) {
325 j = i + 1;
326 while (j < view->nr
327 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
328 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
329 ++j;
330 }
331 ++i;
332 memmove(&view->ranges[i], &view->ranges[j],
333 (view->nr - j) * sizeof(view->ranges[j]));
334 view->nr -= j - i;
335 }
336 }
337
338 static bool memory_region_big_endian(MemoryRegion *mr)
339 {
340 #ifdef TARGET_WORDS_BIGENDIAN
341 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
342 #else
343 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
344 #endif
345 }
346
347 static bool memory_region_wrong_endianness(MemoryRegion *mr)
348 {
349 #ifdef TARGET_WORDS_BIGENDIAN
350 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
351 #else
352 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
353 #endif
354 }
355
356 static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
357 {
358 if (memory_region_wrong_endianness(mr)) {
359 switch (size) {
360 case 1:
361 break;
362 case 2:
363 *data = bswap16(*data);
364 break;
365 case 4:
366 *data = bswap32(*data);
367 break;
368 case 8:
369 *data = bswap64(*data);
370 break;
371 default:
372 abort();
373 }
374 }
375 }
376
377 static inline void memory_region_shift_read_access(uint64_t *value,
378 signed shift,
379 uint64_t mask,
380 uint64_t tmp)
381 {
382 if (shift >= 0) {
383 *value |= (tmp & mask) << shift;
384 } else {
385 *value |= (tmp & mask) >> -shift;
386 }
387 }
388
389 static inline uint64_t memory_region_shift_write_access(uint64_t *value,
390 signed shift,
391 uint64_t mask)
392 {
393 uint64_t tmp;
394
395 if (shift >= 0) {
396 tmp = (*value >> shift) & mask;
397 } else {
398 tmp = (*value << -shift) & mask;
399 }
400
401 return tmp;
402 }
403
404 static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
405 {
406 MemoryRegion *root;
407 hwaddr abs_addr = offset;
408
409 abs_addr += mr->addr;
410 for (root = mr; root->container; ) {
411 root = root->container;
412 abs_addr += root->addr;
413 }
414
415 return abs_addr;
416 }
417
418 static int get_cpu_index(void)
419 {
420 if (current_cpu) {
421 return current_cpu->cpu_index;
422 }
423 return -1;
424 }
425
426 static MemTxResult memory_region_oldmmio_read_accessor(MemoryRegion *mr,
427 hwaddr addr,
428 uint64_t *value,
429 unsigned size,
430 signed shift,
431 uint64_t mask,
432 MemTxAttrs attrs)
433 {
434 uint64_t tmp;
435
436 tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
437 if (mr->subpage) {
438 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
439 } else if (mr == &io_mem_notdirty) {
440 /* Accesses to code which has previously been translated into a TB show
441 * up in the MMIO path, as accesses to the io_mem_notdirty
442 * MemoryRegion. */
443 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
444 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
445 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
446 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
447 }
448 memory_region_shift_read_access(value, shift, mask, tmp);
449 return MEMTX_OK;
450 }
451
452 static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
453 hwaddr addr,
454 uint64_t *value,
455 unsigned size,
456 signed shift,
457 uint64_t mask,
458 MemTxAttrs attrs)
459 {
460 uint64_t tmp;
461
462 tmp = mr->ops->read(mr->opaque, addr, size);
463 if (mr->subpage) {
464 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
465 } else if (mr == &io_mem_notdirty) {
466 /* Accesses to code which has previously been translated into a TB show
467 * up in the MMIO path, as accesses to the io_mem_notdirty
468 * MemoryRegion. */
469 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
470 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
471 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
472 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
473 }
474 memory_region_shift_read_access(value, shift, mask, tmp);
475 return MEMTX_OK;
476 }
477
478 static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
479 hwaddr addr,
480 uint64_t *value,
481 unsigned size,
482 signed shift,
483 uint64_t mask,
484 MemTxAttrs attrs)
485 {
486 uint64_t tmp = 0;
487 MemTxResult r;
488
489 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
490 if (mr->subpage) {
491 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
492 } else if (mr == &io_mem_notdirty) {
493 /* Accesses to code which has previously been translated into a TB show
494 * up in the MMIO path, as accesses to the io_mem_notdirty
495 * MemoryRegion. */
496 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
497 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
498 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
499 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
500 }
501 memory_region_shift_read_access(value, shift, mask, tmp);
502 return r;
503 }
504
505 static MemTxResult memory_region_oldmmio_write_accessor(MemoryRegion *mr,
506 hwaddr addr,
507 uint64_t *value,
508 unsigned size,
509 signed shift,
510 uint64_t mask,
511 MemTxAttrs attrs)
512 {
513 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
514
515 if (mr->subpage) {
516 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
517 } else if (mr == &io_mem_notdirty) {
518 /* Accesses to code which has previously been translated into a TB show
519 * up in the MMIO path, as accesses to the io_mem_notdirty
520 * MemoryRegion. */
521 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
522 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
523 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
524 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
525 }
526 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
527 return MEMTX_OK;
528 }
529
530 static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
531 hwaddr addr,
532 uint64_t *value,
533 unsigned size,
534 signed shift,
535 uint64_t mask,
536 MemTxAttrs attrs)
537 {
538 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
539
540 if (mr->subpage) {
541 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
542 } else if (mr == &io_mem_notdirty) {
543 /* Accesses to code which has previously been translated into a TB show
544 * up in the MMIO path, as accesses to the io_mem_notdirty
545 * MemoryRegion. */
546 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
547 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
548 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
549 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
550 }
551 mr->ops->write(mr->opaque, addr, tmp, size);
552 return MEMTX_OK;
553 }
554
555 static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
556 hwaddr addr,
557 uint64_t *value,
558 unsigned size,
559 signed shift,
560 uint64_t mask,
561 MemTxAttrs attrs)
562 {
563 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
564
565 if (mr->subpage) {
566 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
567 } else if (mr == &io_mem_notdirty) {
568 /* Accesses to code which has previously been translated into a TB show
569 * up in the MMIO path, as accesses to the io_mem_notdirty
570 * MemoryRegion. */
571 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
572 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
573 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
574 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
575 }
576 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
577 }
578
579 static MemTxResult access_with_adjusted_size(hwaddr addr,
580 uint64_t *value,
581 unsigned size,
582 unsigned access_size_min,
583 unsigned access_size_max,
584 MemTxResult (*access_fn)
585 (MemoryRegion *mr,
586 hwaddr addr,
587 uint64_t *value,
588 unsigned size,
589 signed shift,
590 uint64_t mask,
591 MemTxAttrs attrs),
592 MemoryRegion *mr,
593 MemTxAttrs attrs)
594 {
595 uint64_t access_mask;
596 unsigned access_size;
597 unsigned i;
598 MemTxResult r = MEMTX_OK;
599
600 if (!access_size_min) {
601 access_size_min = 1;
602 }
603 if (!access_size_max) {
604 access_size_max = 4;
605 }
606
607 /* FIXME: support unaligned access? */
608 access_size = MAX(MIN(size, access_size_max), access_size_min);
609 access_mask = MAKE_64BIT_MASK(0, access_size * 8);
610 if (memory_region_big_endian(mr)) {
611 for (i = 0; i < size; i += access_size) {
612 r |= access_fn(mr, addr + i, value, access_size,
613 (size - access_size - i) * 8, access_mask, attrs);
614 }
615 } else {
616 for (i = 0; i < size; i += access_size) {
617 r |= access_fn(mr, addr + i, value, access_size, i * 8,
618 access_mask, attrs);
619 }
620 }
621 return r;
622 }
623
624 static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
625 {
626 AddressSpace *as;
627
628 while (mr->container) {
629 mr = mr->container;
630 }
631 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
632 if (mr == as->root) {
633 return as;
634 }
635 }
636 return NULL;
637 }
638
639 /* Render a memory region into the global view. Ranges in @view obscure
640 * ranges in @mr.
641 */
642 static void render_memory_region(FlatView *view,
643 MemoryRegion *mr,
644 Int128 base,
645 AddrRange clip,
646 bool readonly)
647 {
648 MemoryRegion *subregion;
649 unsigned i;
650 hwaddr offset_in_region;
651 Int128 remain;
652 Int128 now;
653 FlatRange fr;
654 AddrRange tmp;
655
656 if (!mr->enabled) {
657 return;
658 }
659
660 int128_addto(&base, int128_make64(mr->addr));
661 readonly |= mr->readonly;
662
663 tmp = addrrange_make(base, mr->size);
664
665 if (!addrrange_intersects(tmp, clip)) {
666 return;
667 }
668
669 clip = addrrange_intersection(tmp, clip);
670
671 if (mr->alias) {
672 int128_subfrom(&base, int128_make64(mr->alias->addr));
673 int128_subfrom(&base, int128_make64(mr->alias_offset));
674 render_memory_region(view, mr->alias, base, clip, readonly);
675 return;
676 }
677
678 /* Render subregions in priority order. */
679 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
680 render_memory_region(view, subregion, base, clip, readonly);
681 }
682
683 if (!mr->terminates) {
684 return;
685 }
686
687 offset_in_region = int128_get64(int128_sub(clip.start, base));
688 base = clip.start;
689 remain = clip.size;
690
691 fr.mr = mr;
692 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
693 fr.romd_mode = mr->romd_mode;
694 fr.readonly = readonly;
695
696 /* Render the region itself into any gaps left by the current view. */
697 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
698 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
699 continue;
700 }
701 if (int128_lt(base, view->ranges[i].addr.start)) {
702 now = int128_min(remain,
703 int128_sub(view->ranges[i].addr.start, base));
704 fr.offset_in_region = offset_in_region;
705 fr.addr = addrrange_make(base, now);
706 flatview_insert(view, i, &fr);
707 ++i;
708 int128_addto(&base, now);
709 offset_in_region += int128_get64(now);
710 int128_subfrom(&remain, now);
711 }
712 now = int128_sub(int128_min(int128_add(base, remain),
713 addrrange_end(view->ranges[i].addr)),
714 base);
715 int128_addto(&base, now);
716 offset_in_region += int128_get64(now);
717 int128_subfrom(&remain, now);
718 }
719 if (int128_nz(remain)) {
720 fr.offset_in_region = offset_in_region;
721 fr.addr = addrrange_make(base, remain);
722 flatview_insert(view, i, &fr);
723 }
724 }
725
726 static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
727 {
728 while (mr->enabled) {
729 if (mr->alias) {
730 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
731 /* The alias is included in its entirety. Use it as
732 * the "real" root, so that we can share more FlatViews.
733 */
734 mr = mr->alias;
735 continue;
736 }
737 } else if (!mr->terminates) {
738 unsigned int found = 0;
739 MemoryRegion *child, *next = NULL;
740 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
741 if (child->enabled) {
742 if (++found > 1) {
743 next = NULL;
744 break;
745 }
746 if (!child->addr && int128_ge(mr->size, child->size)) {
747 /* A child is included in its entirety. If it's the only
748 * enabled one, use it in the hope of finding an alias down the
749 * way. This will also let us share FlatViews.
750 */
751 next = child;
752 }
753 }
754 }
755 if (found == 0) {
756 return NULL;
757 }
758 if (next) {
759 mr = next;
760 continue;
761 }
762 }
763
764 return mr;
765 }
766
767 return NULL;
768 }
769
770 /* Render a memory topology into a list of disjoint absolute ranges. */
771 static FlatView *generate_memory_topology(MemoryRegion *mr)
772 {
773 int i;
774 FlatView *view;
775
776 view = flatview_new(mr);
777
778 if (mr) {
779 render_memory_region(view, mr, int128_zero(),
780 addrrange_make(int128_zero(), int128_2_64()), false);
781 }
782 flatview_simplify(view);
783
784 view->dispatch = address_space_dispatch_new(view);
785 for (i = 0; i < view->nr; i++) {
786 MemoryRegionSection mrs =
787 section_from_flat_range(&view->ranges[i], view);
788 flatview_add_to_dispatch(view, &mrs);
789 }
790 address_space_dispatch_compact(view->dispatch);
791 g_hash_table_replace(flat_views, mr, view);
792
793 return view;
794 }
795
796 static void address_space_add_del_ioeventfds(AddressSpace *as,
797 MemoryRegionIoeventfd *fds_new,
798 unsigned fds_new_nb,
799 MemoryRegionIoeventfd *fds_old,
800 unsigned fds_old_nb)
801 {
802 unsigned iold, inew;
803 MemoryRegionIoeventfd *fd;
804 MemoryRegionSection section;
805
806 /* Generate a symmetric difference of the old and new fd sets, adding
807 * and deleting as necessary.
808 */
809
810 iold = inew = 0;
811 while (iold < fds_old_nb || inew < fds_new_nb) {
812 if (iold < fds_old_nb
813 && (inew == fds_new_nb
814 || memory_region_ioeventfd_before(&fds_old[iold],
815 &fds_new[inew]))) {
816 fd = &fds_old[iold];
817 section = (MemoryRegionSection) {
818 .fv = address_space_to_flatview(as),
819 .offset_within_address_space = int128_get64(fd->addr.start),
820 .size = fd->addr.size,
821 };
822 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
823 fd->match_data, fd->data, fd->e);
824 ++iold;
825 } else if (inew < fds_new_nb
826 && (iold == fds_old_nb
827 || memory_region_ioeventfd_before(&fds_new[inew],
828 &fds_old[iold]))) {
829 fd = &fds_new[inew];
830 section = (MemoryRegionSection) {
831 .fv = address_space_to_flatview(as),
832 .offset_within_address_space = int128_get64(fd->addr.start),
833 .size = fd->addr.size,
834 };
835 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
836 fd->match_data, fd->data, fd->e);
837 ++inew;
838 } else {
839 ++iold;
840 ++inew;
841 }
842 }
843 }
844
845 FlatView *address_space_get_flatview(AddressSpace *as)
846 {
847 FlatView *view;
848
849 rcu_read_lock();
850 do {
851 view = address_space_to_flatview(as);
852 /* If somebody has replaced as->current_map concurrently,
853 * flatview_ref returns false.
854 */
855 } while (!flatview_ref(view));
856 rcu_read_unlock();
857 return view;
858 }
859
860 static void address_space_update_ioeventfds(AddressSpace *as)
861 {
862 FlatView *view;
863 FlatRange *fr;
864 unsigned ioeventfd_nb = 0;
865 MemoryRegionIoeventfd *ioeventfds = NULL;
866 AddrRange tmp;
867 unsigned i;
868
869 view = address_space_get_flatview(as);
870 FOR_EACH_FLAT_RANGE(fr, view) {
871 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
872 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
873 int128_sub(fr->addr.start,
874 int128_make64(fr->offset_in_region)));
875 if (addrrange_intersects(fr->addr, tmp)) {
876 ++ioeventfd_nb;
877 ioeventfds = g_realloc(ioeventfds,
878 ioeventfd_nb * sizeof(*ioeventfds));
879 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
880 ioeventfds[ioeventfd_nb-1].addr = tmp;
881 }
882 }
883 }
884
885 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
886 as->ioeventfds, as->ioeventfd_nb);
887
888 g_free(as->ioeventfds);
889 as->ioeventfds = ioeventfds;
890 as->ioeventfd_nb = ioeventfd_nb;
891 flatview_unref(view);
892 }
893
894 static void address_space_update_topology_pass(AddressSpace *as,
895 const FlatView *old_view,
896 const FlatView *new_view,
897 bool adding)
898 {
899 unsigned iold, inew;
900 FlatRange *frold, *frnew;
901
902 /* Generate a symmetric difference of the old and new memory maps.
903 * Kill ranges in the old map, and instantiate ranges in the new map.
904 */
905 iold = inew = 0;
906 while (iold < old_view->nr || inew < new_view->nr) {
907 if (iold < old_view->nr) {
908 frold = &old_view->ranges[iold];
909 } else {
910 frold = NULL;
911 }
912 if (inew < new_view->nr) {
913 frnew = &new_view->ranges[inew];
914 } else {
915 frnew = NULL;
916 }
917
918 if (frold
919 && (!frnew
920 || int128_lt(frold->addr.start, frnew->addr.start)
921 || (int128_eq(frold->addr.start, frnew->addr.start)
922 && !flatrange_equal(frold, frnew)))) {
923 /* In old but not in new, or in both but attributes changed. */
924
925 if (!adding) {
926 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
927 }
928
929 ++iold;
930 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
931 /* In both and unchanged (except logging may have changed) */
932
933 if (adding) {
934 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
935 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
936 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
937 frold->dirty_log_mask,
938 frnew->dirty_log_mask);
939 }
940 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
941 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
942 frold->dirty_log_mask,
943 frnew->dirty_log_mask);
944 }
945 }
946
947 ++iold;
948 ++inew;
949 } else {
950 /* In new */
951
952 if (adding) {
953 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
954 }
955
956 ++inew;
957 }
958 }
959 }
960
961 static void flatviews_init(void)
962 {
963 static FlatView *empty_view;
964
965 if (flat_views) {
966 return;
967 }
968
969 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
970 (GDestroyNotify) flatview_unref);
971 if (!empty_view) {
972 empty_view = generate_memory_topology(NULL);
973 /* We keep it alive forever in the global variable. */
974 flatview_ref(empty_view);
975 } else {
976 g_hash_table_replace(flat_views, NULL, empty_view);
977 flatview_ref(empty_view);
978 }
979 }
980
981 static void flatviews_reset(void)
982 {
983 AddressSpace *as;
984
985 if (flat_views) {
986 g_hash_table_unref(flat_views);
987 flat_views = NULL;
988 }
989 flatviews_init();
990
991 /* Render unique FVs */
992 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
993 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
994
995 if (g_hash_table_lookup(flat_views, physmr)) {
996 continue;
997 }
998
999 generate_memory_topology(physmr);
1000 }
1001 }
1002
1003 static void address_space_set_flatview(AddressSpace *as)
1004 {
1005 FlatView *old_view = address_space_to_flatview(as);
1006 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1007 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
1008
1009 assert(new_view);
1010
1011 if (old_view == new_view) {
1012 return;
1013 }
1014
1015 if (old_view) {
1016 flatview_ref(old_view);
1017 }
1018
1019 flatview_ref(new_view);
1020
1021 if (!QTAILQ_EMPTY(&as->listeners)) {
1022 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1023
1024 if (!old_view2) {
1025 old_view2 = &tmpview;
1026 }
1027 address_space_update_topology_pass(as, old_view2, new_view, false);
1028 address_space_update_topology_pass(as, old_view2, new_view, true);
1029 }
1030
1031 /* Writes are protected by the BQL. */
1032 atomic_rcu_set(&as->current_map, new_view);
1033 if (old_view) {
1034 flatview_unref(old_view);
1035 }
1036
1037 /* Note that all the old MemoryRegions are still alive up to this
1038 * point. This relieves most MemoryListeners from the need to
1039 * ref/unref the MemoryRegions they get---unless they use them
1040 * outside the iothread mutex, in which case precise reference
1041 * counting is necessary.
1042 */
1043 if (old_view) {
1044 flatview_unref(old_view);
1045 }
1046 }
1047
1048 static void address_space_update_topology(AddressSpace *as)
1049 {
1050 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1051
1052 flatviews_init();
1053 if (!g_hash_table_lookup(flat_views, physmr)) {
1054 generate_memory_topology(physmr);
1055 }
1056 address_space_set_flatview(as);
1057 }
1058
1059 void memory_region_transaction_begin(void)
1060 {
1061 qemu_flush_coalesced_mmio_buffer();
1062 ++memory_region_transaction_depth;
1063 }
1064
1065 void memory_region_transaction_commit(void)
1066 {
1067 AddressSpace *as;
1068
1069 assert(memory_region_transaction_depth);
1070 assert(qemu_mutex_iothread_locked());
1071
1072 --memory_region_transaction_depth;
1073 if (!memory_region_transaction_depth) {
1074 if (memory_region_update_pending) {
1075 flatviews_reset();
1076
1077 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
1078
1079 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1080 address_space_set_flatview(as);
1081 address_space_update_ioeventfds(as);
1082 }
1083 memory_region_update_pending = false;
1084 ioeventfd_update_pending = false;
1085 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1086 } else if (ioeventfd_update_pending) {
1087 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1088 address_space_update_ioeventfds(as);
1089 }
1090 ioeventfd_update_pending = false;
1091 }
1092 }
1093 }
1094
1095 static void memory_region_destructor_none(MemoryRegion *mr)
1096 {
1097 }
1098
1099 static void memory_region_destructor_ram(MemoryRegion *mr)
1100 {
1101 qemu_ram_free(mr->ram_block);
1102 }
1103
1104 static bool memory_region_need_escape(char c)
1105 {
1106 return c == '/' || c == '[' || c == '\\' || c == ']';
1107 }
1108
1109 static char *memory_region_escape_name(const char *name)
1110 {
1111 const char *p;
1112 char *escaped, *q;
1113 uint8_t c;
1114 size_t bytes = 0;
1115
1116 for (p = name; *p; p++) {
1117 bytes += memory_region_need_escape(*p) ? 4 : 1;
1118 }
1119 if (bytes == p - name) {
1120 return g_memdup(name, bytes + 1);
1121 }
1122
1123 escaped = g_malloc(bytes + 1);
1124 for (p = name, q = escaped; *p; p++) {
1125 c = *p;
1126 if (unlikely(memory_region_need_escape(c))) {
1127 *q++ = '\\';
1128 *q++ = 'x';
1129 *q++ = "0123456789abcdef"[c >> 4];
1130 c = "0123456789abcdef"[c & 15];
1131 }
1132 *q++ = c;
1133 }
1134 *q = 0;
1135 return escaped;
1136 }
1137
1138 static void memory_region_do_init(MemoryRegion *mr,
1139 Object *owner,
1140 const char *name,
1141 uint64_t size)
1142 {
1143 mr->size = int128_make64(size);
1144 if (size == UINT64_MAX) {
1145 mr->size = int128_2_64();
1146 }
1147 mr->name = g_strdup(name);
1148 mr->owner = owner;
1149 mr->ram_block = NULL;
1150
1151 if (name) {
1152 char *escaped_name = memory_region_escape_name(name);
1153 char *name_array = g_strdup_printf("%s[*]", escaped_name);
1154
1155 if (!owner) {
1156 owner = container_get(qdev_get_machine(), "/unattached");
1157 }
1158
1159 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
1160 object_unref(OBJECT(mr));
1161 g_free(name_array);
1162 g_free(escaped_name);
1163 }
1164 }
1165
1166 void memory_region_init(MemoryRegion *mr,
1167 Object *owner,
1168 const char *name,
1169 uint64_t size)
1170 {
1171 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1172 memory_region_do_init(mr, owner, name, size);
1173 }
1174
1175 static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1176 void *opaque, Error **errp)
1177 {
1178 MemoryRegion *mr = MEMORY_REGION(obj);
1179 uint64_t value = mr->addr;
1180
1181 visit_type_uint64(v, name, &value, errp);
1182 }
1183
1184 static void memory_region_get_container(Object *obj, Visitor *v,
1185 const char *name, void *opaque,
1186 Error **errp)
1187 {
1188 MemoryRegion *mr = MEMORY_REGION(obj);
1189 gchar *path = (gchar *)"";
1190
1191 if (mr->container) {
1192 path = object_get_canonical_path(OBJECT(mr->container));
1193 }
1194 visit_type_str(v, name, &path, errp);
1195 if (mr->container) {
1196 g_free(path);
1197 }
1198 }
1199
1200 static Object *memory_region_resolve_container(Object *obj, void *opaque,
1201 const char *part)
1202 {
1203 MemoryRegion *mr = MEMORY_REGION(obj);
1204
1205 return OBJECT(mr->container);
1206 }
1207
1208 static void memory_region_get_priority(Object *obj, Visitor *v,
1209 const char *name, void *opaque,
1210 Error **errp)
1211 {
1212 MemoryRegion *mr = MEMORY_REGION(obj);
1213 int32_t value = mr->priority;
1214
1215 visit_type_int32(v, name, &value, errp);
1216 }
1217
1218 static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1219 void *opaque, Error **errp)
1220 {
1221 MemoryRegion *mr = MEMORY_REGION(obj);
1222 uint64_t value = memory_region_size(mr);
1223
1224 visit_type_uint64(v, name, &value, errp);
1225 }
1226
1227 static void memory_region_initfn(Object *obj)
1228 {
1229 MemoryRegion *mr = MEMORY_REGION(obj);
1230 ObjectProperty *op;
1231
1232 mr->ops = &unassigned_mem_ops;
1233 mr->enabled = true;
1234 mr->romd_mode = true;
1235 mr->global_locking = true;
1236 mr->destructor = memory_region_destructor_none;
1237 QTAILQ_INIT(&mr->subregions);
1238 QTAILQ_INIT(&mr->coalesced);
1239
1240 op = object_property_add(OBJECT(mr), "container",
1241 "link<" TYPE_MEMORY_REGION ">",
1242 memory_region_get_container,
1243 NULL, /* memory_region_set_container */
1244 NULL, NULL, &error_abort);
1245 op->resolve = memory_region_resolve_container;
1246
1247 object_property_add(OBJECT(mr), "addr", "uint64",
1248 memory_region_get_addr,
1249 NULL, /* memory_region_set_addr */
1250 NULL, NULL, &error_abort);
1251 object_property_add(OBJECT(mr), "priority", "uint32",
1252 memory_region_get_priority,
1253 NULL, /* memory_region_set_priority */
1254 NULL, NULL, &error_abort);
1255 object_property_add(OBJECT(mr), "size", "uint64",
1256 memory_region_get_size,
1257 NULL, /* memory_region_set_size, */
1258 NULL, NULL, &error_abort);
1259 }
1260
1261 static void iommu_memory_region_initfn(Object *obj)
1262 {
1263 MemoryRegion *mr = MEMORY_REGION(obj);
1264
1265 mr->is_iommu = true;
1266 }
1267
1268 static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1269 unsigned size)
1270 {
1271 #ifdef DEBUG_UNASSIGNED
1272 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1273 #endif
1274 if (current_cpu != NULL) {
1275 bool is_exec = current_cpu->mem_io_access_type == MMU_INST_FETCH;
1276 cpu_unassigned_access(current_cpu, addr, false, is_exec, 0, size);
1277 }
1278 return 0;
1279 }
1280
1281 static void unassigned_mem_write(void *opaque, hwaddr addr,
1282 uint64_t val, unsigned size)
1283 {
1284 #ifdef DEBUG_UNASSIGNED
1285 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1286 #endif
1287 if (current_cpu != NULL) {
1288 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
1289 }
1290 }
1291
1292 static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1293 unsigned size, bool is_write,
1294 MemTxAttrs attrs)
1295 {
1296 return false;
1297 }
1298
1299 const MemoryRegionOps unassigned_mem_ops = {
1300 .valid.accepts = unassigned_mem_accepts,
1301 .endianness = DEVICE_NATIVE_ENDIAN,
1302 };
1303
1304 static uint64_t memory_region_ram_device_read(void *opaque,
1305 hwaddr addr, unsigned size)
1306 {
1307 MemoryRegion *mr = opaque;
1308 uint64_t data = (uint64_t)~0;
1309
1310 switch (size) {
1311 case 1:
1312 data = *(uint8_t *)(mr->ram_block->host + addr);
1313 break;
1314 case 2:
1315 data = *(uint16_t *)(mr->ram_block->host + addr);
1316 break;
1317 case 4:
1318 data = *(uint32_t *)(mr->ram_block->host + addr);
1319 break;
1320 case 8:
1321 data = *(uint64_t *)(mr->ram_block->host + addr);
1322 break;
1323 }
1324
1325 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1326
1327 return data;
1328 }
1329
1330 static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1331 uint64_t data, unsigned size)
1332 {
1333 MemoryRegion *mr = opaque;
1334
1335 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1336
1337 switch (size) {
1338 case 1:
1339 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1340 break;
1341 case 2:
1342 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1343 break;
1344 case 4:
1345 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1346 break;
1347 case 8:
1348 *(uint64_t *)(mr->ram_block->host + addr) = data;
1349 break;
1350 }
1351 }
1352
1353 static const MemoryRegionOps ram_device_mem_ops = {
1354 .read = memory_region_ram_device_read,
1355 .write = memory_region_ram_device_write,
1356 .endianness = DEVICE_HOST_ENDIAN,
1357 .valid = {
1358 .min_access_size = 1,
1359 .max_access_size = 8,
1360 .unaligned = true,
1361 },
1362 .impl = {
1363 .min_access_size = 1,
1364 .max_access_size = 8,
1365 .unaligned = true,
1366 },
1367 };
1368
1369 bool memory_region_access_valid(MemoryRegion *mr,
1370 hwaddr addr,
1371 unsigned size,
1372 bool is_write,
1373 MemTxAttrs attrs)
1374 {
1375 int access_size_min, access_size_max;
1376 int access_size, i;
1377
1378 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1379 return false;
1380 }
1381
1382 if (!mr->ops->valid.accepts) {
1383 return true;
1384 }
1385
1386 access_size_min = mr->ops->valid.min_access_size;
1387 if (!mr->ops->valid.min_access_size) {
1388 access_size_min = 1;
1389 }
1390
1391 access_size_max = mr->ops->valid.max_access_size;
1392 if (!mr->ops->valid.max_access_size) {
1393 access_size_max = 4;
1394 }
1395
1396 access_size = MAX(MIN(size, access_size_max), access_size_min);
1397 for (i = 0; i < size; i += access_size) {
1398 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1399 is_write, attrs)) {
1400 return false;
1401 }
1402 }
1403
1404 return true;
1405 }
1406
1407 static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1408 hwaddr addr,
1409 uint64_t *pval,
1410 unsigned size,
1411 MemTxAttrs attrs)
1412 {
1413 *pval = 0;
1414
1415 if (mr->ops->read) {
1416 return access_with_adjusted_size(addr, pval, size,
1417 mr->ops->impl.min_access_size,
1418 mr->ops->impl.max_access_size,
1419 memory_region_read_accessor,
1420 mr, attrs);
1421 } else if (mr->ops->read_with_attrs) {
1422 return access_with_adjusted_size(addr, pval, size,
1423 mr->ops->impl.min_access_size,
1424 mr->ops->impl.max_access_size,
1425 memory_region_read_with_attrs_accessor,
1426 mr, attrs);
1427 } else {
1428 return access_with_adjusted_size(addr, pval, size, 1, 4,
1429 memory_region_oldmmio_read_accessor,
1430 mr, attrs);
1431 }
1432 }
1433
1434 MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1435 hwaddr addr,
1436 uint64_t *pval,
1437 unsigned size,
1438 MemTxAttrs attrs)
1439 {
1440 MemTxResult r;
1441
1442 if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
1443 *pval = unassigned_mem_read(mr, addr, size);
1444 return MEMTX_DECODE_ERROR;
1445 }
1446
1447 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
1448 adjust_endianness(mr, pval, size);
1449 return r;
1450 }
1451
1452 /* Return true if an eventfd was signalled */
1453 static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1454 hwaddr addr,
1455 uint64_t data,
1456 unsigned size,
1457 MemTxAttrs attrs)
1458 {
1459 MemoryRegionIoeventfd ioeventfd = {
1460 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1461 .data = data,
1462 };
1463 unsigned i;
1464
1465 for (i = 0; i < mr->ioeventfd_nb; i++) {
1466 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1467 ioeventfd.e = mr->ioeventfds[i].e;
1468
1469 if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) {
1470 event_notifier_set(ioeventfd.e);
1471 return true;
1472 }
1473 }
1474
1475 return false;
1476 }
1477
1478 MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1479 hwaddr addr,
1480 uint64_t data,
1481 unsigned size,
1482 MemTxAttrs attrs)
1483 {
1484 if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
1485 unassigned_mem_write(mr, addr, data, size);
1486 return MEMTX_DECODE_ERROR;
1487 }
1488
1489 adjust_endianness(mr, &data, size);
1490
1491 if ((!kvm_eventfds_enabled()) &&
1492 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1493 return MEMTX_OK;
1494 }
1495
1496 if (mr->ops->write) {
1497 return access_with_adjusted_size(addr, &data, size,
1498 mr->ops->impl.min_access_size,
1499 mr->ops->impl.max_access_size,
1500 memory_region_write_accessor, mr,
1501 attrs);
1502 } else if (mr->ops->write_with_attrs) {
1503 return
1504 access_with_adjusted_size(addr, &data, size,
1505 mr->ops->impl.min_access_size,
1506 mr->ops->impl.max_access_size,
1507 memory_region_write_with_attrs_accessor,
1508 mr, attrs);
1509 } else {
1510 return access_with_adjusted_size(addr, &data, size, 1, 4,
1511 memory_region_oldmmio_write_accessor,
1512 mr, attrs);
1513 }
1514 }
1515
1516 void memory_region_init_io(MemoryRegion *mr,
1517 Object *owner,
1518 const MemoryRegionOps *ops,
1519 void *opaque,
1520 const char *name,
1521 uint64_t size)
1522 {
1523 memory_region_init(mr, owner, name, size);
1524 mr->ops = ops ? ops : &unassigned_mem_ops;
1525 mr->opaque = opaque;
1526 mr->terminates = true;
1527 }
1528
1529 void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1530 Object *owner,
1531 const char *name,
1532 uint64_t size,
1533 Error **errp)
1534 {
1535 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1536 }
1537
1538 void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1539 Object *owner,
1540 const char *name,
1541 uint64_t size,
1542 bool share,
1543 Error **errp)
1544 {
1545 Error *err = NULL;
1546 memory_region_init(mr, owner, name, size);
1547 mr->ram = true;
1548 mr->terminates = true;
1549 mr->destructor = memory_region_destructor_ram;
1550 mr->ram_block = qemu_ram_alloc(size, share, mr, &err);
1551 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1552 if (err) {
1553 mr->size = int128_zero();
1554 object_unparent(OBJECT(mr));
1555 error_propagate(errp, err);
1556 }
1557 }
1558
1559 void memory_region_init_resizeable_ram(MemoryRegion *mr,
1560 Object *owner,
1561 const char *name,
1562 uint64_t size,
1563 uint64_t max_size,
1564 void (*resized)(const char*,
1565 uint64_t length,
1566 void *host),
1567 Error **errp)
1568 {
1569 Error *err = NULL;
1570 memory_region_init(mr, owner, name, size);
1571 mr->ram = true;
1572 mr->terminates = true;
1573 mr->destructor = memory_region_destructor_ram;
1574 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1575 mr, &err);
1576 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1577 if (err) {
1578 mr->size = int128_zero();
1579 object_unparent(OBJECT(mr));
1580 error_propagate(errp, err);
1581 }
1582 }
1583
1584 #ifdef CONFIG_POSIX
1585 void memory_region_init_ram_from_file(MemoryRegion *mr,
1586 struct Object *owner,
1587 const char *name,
1588 uint64_t size,
1589 uint64_t align,
1590 uint32_t ram_flags,
1591 const char *path,
1592 Error **errp)
1593 {
1594 Error *err = NULL;
1595 memory_region_init(mr, owner, name, size);
1596 mr->ram = true;
1597 mr->terminates = true;
1598 mr->destructor = memory_region_destructor_ram;
1599 mr->align = align;
1600 mr->ram_block = qemu_ram_alloc_from_file(size, mr, ram_flags, path, &err);
1601 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1602 if (err) {
1603 mr->size = int128_zero();
1604 object_unparent(OBJECT(mr));
1605 error_propagate(errp, err);
1606 }
1607 }
1608
1609 void memory_region_init_ram_from_fd(MemoryRegion *mr,
1610 struct Object *owner,
1611 const char *name,
1612 uint64_t size,
1613 bool share,
1614 int fd,
1615 Error **errp)
1616 {
1617 Error *err = NULL;
1618 memory_region_init(mr, owner, name, size);
1619 mr->ram = true;
1620 mr->terminates = true;
1621 mr->destructor = memory_region_destructor_ram;
1622 mr->ram_block = qemu_ram_alloc_from_fd(size, mr,
1623 share ? RAM_SHARED : 0,
1624 fd, &err);
1625 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1626 if (err) {
1627 mr->size = int128_zero();
1628 object_unparent(OBJECT(mr));
1629 error_propagate(errp, err);
1630 }
1631 }
1632 #endif
1633
1634 void memory_region_init_ram_ptr(MemoryRegion *mr,
1635 Object *owner,
1636 const char *name,
1637 uint64_t size,
1638 void *ptr)
1639 {
1640 memory_region_init(mr, owner, name, size);
1641 mr->ram = true;
1642 mr->terminates = true;
1643 mr->destructor = memory_region_destructor_ram;
1644 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1645
1646 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1647 assert(ptr != NULL);
1648 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1649 }
1650
1651 void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1652 Object *owner,
1653 const char *name,
1654 uint64_t size,
1655 void *ptr)
1656 {
1657 memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1658 mr->ram_device = true;
1659 mr->ops = &ram_device_mem_ops;
1660 mr->opaque = mr;
1661 }
1662
1663 void memory_region_init_alias(MemoryRegion *mr,
1664 Object *owner,
1665 const char *name,
1666 MemoryRegion *orig,
1667 hwaddr offset,
1668 uint64_t size)
1669 {
1670 memory_region_init(mr, owner, name, size);
1671 mr->alias = orig;
1672 mr->alias_offset = offset;
1673 }
1674
1675 void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1676 struct Object *owner,
1677 const char *name,
1678 uint64_t size,
1679 Error **errp)
1680 {
1681 Error *err = NULL;
1682 memory_region_init(mr, owner, name, size);
1683 mr->ram = true;
1684 mr->readonly = true;
1685 mr->terminates = true;
1686 mr->destructor = memory_region_destructor_ram;
1687 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1688 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1689 if (err) {
1690 mr->size = int128_zero();
1691 object_unparent(OBJECT(mr));
1692 error_propagate(errp, err);
1693 }
1694 }
1695
1696 void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1697 Object *owner,
1698 const MemoryRegionOps *ops,
1699 void *opaque,
1700 const char *name,
1701 uint64_t size,
1702 Error **errp)
1703 {
1704 Error *err = NULL;
1705 assert(ops);
1706 memory_region_init(mr, owner, name, size);
1707 mr->ops = ops;
1708 mr->opaque = opaque;
1709 mr->terminates = true;
1710 mr->rom_device = true;
1711 mr->destructor = memory_region_destructor_ram;
1712 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1713 if (err) {
1714 mr->size = int128_zero();
1715 object_unparent(OBJECT(mr));
1716 error_propagate(errp, err);
1717 }
1718 }
1719
1720 void memory_region_init_iommu(void *_iommu_mr,
1721 size_t instance_size,
1722 const char *mrtypename,
1723 Object *owner,
1724 const char *name,
1725 uint64_t size)
1726 {
1727 struct IOMMUMemoryRegion *iommu_mr;
1728 struct MemoryRegion *mr;
1729
1730 object_initialize(_iommu_mr, instance_size, mrtypename);
1731 mr = MEMORY_REGION(_iommu_mr);
1732 memory_region_do_init(mr, owner, name, size);
1733 iommu_mr = IOMMU_MEMORY_REGION(mr);
1734 mr->terminates = true; /* then re-forwards */
1735 QLIST_INIT(&iommu_mr->iommu_notify);
1736 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
1737 }
1738
1739 static void memory_region_finalize(Object *obj)
1740 {
1741 MemoryRegion *mr = MEMORY_REGION(obj);
1742
1743 assert(!mr->container);
1744
1745 /* We know the region is not visible in any address space (it
1746 * does not have a container and cannot be a root either because
1747 * it has no references, so we can blindly clear mr->enabled.
1748 * memory_region_set_enabled instead could trigger a transaction
1749 * and cause an infinite loop.
1750 */
1751 mr->enabled = false;
1752 memory_region_transaction_begin();
1753 while (!QTAILQ_EMPTY(&mr->subregions)) {
1754 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1755 memory_region_del_subregion(mr, subregion);
1756 }
1757 memory_region_transaction_commit();
1758
1759 mr->destructor(mr);
1760 memory_region_clear_coalescing(mr);
1761 g_free((char *)mr->name);
1762 g_free(mr->ioeventfds);
1763 }
1764
1765 Object *memory_region_owner(MemoryRegion *mr)
1766 {
1767 Object *obj = OBJECT(mr);
1768 return obj->parent;
1769 }
1770
1771 void memory_region_ref(MemoryRegion *mr)
1772 {
1773 /* MMIO callbacks most likely will access data that belongs
1774 * to the owner, hence the need to ref/unref the owner whenever
1775 * the memory region is in use.
1776 *
1777 * The memory region is a child of its owner. As long as the
1778 * owner doesn't call unparent itself on the memory region,
1779 * ref-ing the owner will also keep the memory region alive.
1780 * Memory regions without an owner are supposed to never go away;
1781 * we do not ref/unref them because it slows down DMA sensibly.
1782 */
1783 if (mr && mr->owner) {
1784 object_ref(mr->owner);
1785 }
1786 }
1787
1788 void memory_region_unref(MemoryRegion *mr)
1789 {
1790 if (mr && mr->owner) {
1791 object_unref(mr->owner);
1792 }
1793 }
1794
1795 uint64_t memory_region_size(MemoryRegion *mr)
1796 {
1797 if (int128_eq(mr->size, int128_2_64())) {
1798 return UINT64_MAX;
1799 }
1800 return int128_get64(mr->size);
1801 }
1802
1803 const char *memory_region_name(const MemoryRegion *mr)
1804 {
1805 if (!mr->name) {
1806 ((MemoryRegion *)mr)->name =
1807 object_get_canonical_path_component(OBJECT(mr));
1808 }
1809 return mr->name;
1810 }
1811
1812 bool memory_region_is_ram_device(MemoryRegion *mr)
1813 {
1814 return mr->ram_device;
1815 }
1816
1817 uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
1818 {
1819 uint8_t mask = mr->dirty_log_mask;
1820 if (global_dirty_log && mr->ram_block) {
1821 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1822 }
1823 return mask;
1824 }
1825
1826 bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1827 {
1828 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1829 }
1830
1831 static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
1832 {
1833 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1834 IOMMUNotifier *iommu_notifier;
1835 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1836
1837 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1838 flags |= iommu_notifier->notifier_flags;
1839 }
1840
1841 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1842 imrc->notify_flag_changed(iommu_mr,
1843 iommu_mr->iommu_notify_flags,
1844 flags);
1845 }
1846
1847 iommu_mr->iommu_notify_flags = flags;
1848 }
1849
1850 void memory_region_register_iommu_notifier(MemoryRegion *mr,
1851 IOMMUNotifier *n)
1852 {
1853 IOMMUMemoryRegion *iommu_mr;
1854
1855 if (mr->alias) {
1856 memory_region_register_iommu_notifier(mr->alias, n);
1857 return;
1858 }
1859
1860 /* We need to register for at least one bitfield */
1861 iommu_mr = IOMMU_MEMORY_REGION(mr);
1862 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
1863 assert(n->start <= n->end);
1864 assert(n->iommu_idx >= 0 &&
1865 n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr));
1866
1867 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1868 memory_region_update_iommu_notify_flags(iommu_mr);
1869 }
1870
1871 uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
1872 {
1873 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1874
1875 if (imrc->get_min_page_size) {
1876 return imrc->get_min_page_size(iommu_mr);
1877 }
1878 return TARGET_PAGE_SIZE;
1879 }
1880
1881 void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
1882 {
1883 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1884 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1885 hwaddr addr, granularity;
1886 IOMMUTLBEntry iotlb;
1887
1888 /* If the IOMMU has its own replay callback, override */
1889 if (imrc->replay) {
1890 imrc->replay(iommu_mr, n);
1891 return;
1892 }
1893
1894 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
1895
1896 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1897 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
1898 if (iotlb.perm != IOMMU_NONE) {
1899 n->notify(n, &iotlb);
1900 }
1901
1902 /* if (2^64 - MR size) < granularity, it's possible to get an
1903 * infinite loop here. This should catch such a wraparound */
1904 if ((addr + granularity) < addr) {
1905 break;
1906 }
1907 }
1908 }
1909
1910 void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
1911 {
1912 IOMMUNotifier *notifier;
1913
1914 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1915 memory_region_iommu_replay(iommu_mr, notifier);
1916 }
1917 }
1918
1919 void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1920 IOMMUNotifier *n)
1921 {
1922 IOMMUMemoryRegion *iommu_mr;
1923
1924 if (mr->alias) {
1925 memory_region_unregister_iommu_notifier(mr->alias, n);
1926 return;
1927 }
1928 QLIST_REMOVE(n, node);
1929 iommu_mr = IOMMU_MEMORY_REGION(mr);
1930 memory_region_update_iommu_notify_flags(iommu_mr);
1931 }
1932
1933 void memory_region_notify_one(IOMMUNotifier *notifier,
1934 IOMMUTLBEntry *entry)
1935 {
1936 IOMMUNotifierFlag request_flags;
1937
1938 /*
1939 * Skip the notification if the notification does not overlap
1940 * with registered range.
1941 */
1942 if (notifier->start > entry->iova + entry->addr_mask ||
1943 notifier->end < entry->iova) {
1944 return;
1945 }
1946
1947 if (entry->perm & IOMMU_RW) {
1948 request_flags = IOMMU_NOTIFIER_MAP;
1949 } else {
1950 request_flags = IOMMU_NOTIFIER_UNMAP;
1951 }
1952
1953 if (notifier->notifier_flags & request_flags) {
1954 notifier->notify(notifier, entry);
1955 }
1956 }
1957
1958 void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
1959 int iommu_idx,
1960 IOMMUTLBEntry entry)
1961 {
1962 IOMMUNotifier *iommu_notifier;
1963
1964 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
1965
1966 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1967 if (iommu_notifier->iommu_idx == iommu_idx) {
1968 memory_region_notify_one(iommu_notifier, &entry);
1969 }
1970 }
1971 }
1972
1973 int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
1974 enum IOMMUMemoryRegionAttr attr,
1975 void *data)
1976 {
1977 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1978
1979 if (!imrc->get_attr) {
1980 return -EINVAL;
1981 }
1982
1983 return imrc->get_attr(iommu_mr, attr, data);
1984 }
1985
1986 int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr,
1987 MemTxAttrs attrs)
1988 {
1989 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1990
1991 if (!imrc->attrs_to_index) {
1992 return 0;
1993 }
1994
1995 return imrc->attrs_to_index(iommu_mr, attrs);
1996 }
1997
1998 int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr)
1999 {
2000 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2001
2002 if (!imrc->num_indexes) {
2003 return 1;
2004 }
2005
2006 return imrc->num_indexes(iommu_mr);
2007 }
2008
2009 void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
2010 {
2011 uint8_t mask = 1 << client;
2012 uint8_t old_logging;
2013
2014 assert(client == DIRTY_MEMORY_VGA);
2015 old_logging = mr->vga_logging_count;
2016 mr->vga_logging_count += log ? 1 : -1;
2017 if (!!old_logging == !!mr->vga_logging_count) {
2018 return;
2019 }
2020
2021 memory_region_transaction_begin();
2022 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
2023 memory_region_update_pending |= mr->enabled;
2024 memory_region_transaction_commit();
2025 }
2026
2027 bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
2028 hwaddr size, unsigned client)
2029 {
2030 assert(mr->ram_block);
2031 return cpu_physical_memory_get_dirty(memory_region_get_ram_addr(mr) + addr,
2032 size, client);
2033 }
2034
2035 void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
2036 hwaddr size)
2037 {
2038 assert(mr->ram_block);
2039 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
2040 size,
2041 memory_region_get_dirty_log_mask(mr));
2042 }
2043
2044 static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
2045 {
2046 MemoryListener *listener;
2047 AddressSpace *as;
2048 FlatView *view;
2049 FlatRange *fr;
2050
2051 /* If the same address space has multiple log_sync listeners, we
2052 * visit that address space's FlatView multiple times. But because
2053 * log_sync listeners are rare, it's still cheaper than walking each
2054 * address space once.
2055 */
2056 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2057 if (!listener->log_sync) {
2058 continue;
2059 }
2060 as = listener->address_space;
2061 view = address_space_get_flatview(as);
2062 FOR_EACH_FLAT_RANGE(fr, view) {
2063 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
2064 MemoryRegionSection mrs = section_from_flat_range(fr, view);
2065 listener->log_sync(listener, &mrs);
2066 }
2067 }
2068 flatview_unref(view);
2069 }
2070 }
2071
2072 DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
2073 hwaddr addr,
2074 hwaddr size,
2075 unsigned client)
2076 {
2077 assert(mr->ram_block);
2078 memory_region_sync_dirty_bitmap(mr);
2079 return cpu_physical_memory_snapshot_and_clear_dirty(
2080 memory_region_get_ram_addr(mr) + addr, size, client);
2081 }
2082
2083 bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
2084 hwaddr addr, hwaddr size)
2085 {
2086 assert(mr->ram_block);
2087 return cpu_physical_memory_snapshot_get_dirty(snap,
2088 memory_region_get_ram_addr(mr) + addr, size);
2089 }
2090
2091 void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2092 {
2093 if (mr->readonly != readonly) {
2094 memory_region_transaction_begin();
2095 mr->readonly = readonly;
2096 memory_region_update_pending |= mr->enabled;
2097 memory_region_transaction_commit();
2098 }
2099 }
2100
2101 void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
2102 {
2103 if (mr->romd_mode != romd_mode) {
2104 memory_region_transaction_begin();
2105 mr->romd_mode = romd_mode;
2106 memory_region_update_pending |= mr->enabled;
2107 memory_region_transaction_commit();
2108 }
2109 }
2110
2111 void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2112 hwaddr size, unsigned client)
2113 {
2114 assert(mr->ram_block);
2115 cpu_physical_memory_test_and_clear_dirty(
2116 memory_region_get_ram_addr(mr) + addr, size, client);
2117 }
2118
2119 int memory_region_get_fd(MemoryRegion *mr)
2120 {
2121 int fd;
2122
2123 rcu_read_lock();
2124 while (mr->alias) {
2125 mr = mr->alias;
2126 }
2127 fd = mr->ram_block->fd;
2128 rcu_read_unlock();
2129
2130 return fd;
2131 }
2132
2133 void *memory_region_get_ram_ptr(MemoryRegion *mr)
2134 {
2135 void *ptr;
2136 uint64_t offset = 0;
2137
2138 rcu_read_lock();
2139 while (mr->alias) {
2140 offset += mr->alias_offset;
2141 mr = mr->alias;
2142 }
2143 assert(mr->ram_block);
2144 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
2145 rcu_read_unlock();
2146
2147 return ptr;
2148 }
2149
2150 MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2151 {
2152 RAMBlock *block;
2153
2154 block = qemu_ram_block_from_host(ptr, false, offset);
2155 if (!block) {
2156 return NULL;
2157 }
2158
2159 return block->mr;
2160 }
2161
2162 ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2163 {
2164 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2165 }
2166
2167 void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2168 {
2169 assert(mr->ram_block);
2170
2171 qemu_ram_resize(mr->ram_block, newsize, errp);
2172 }
2173
2174 static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
2175 {
2176 FlatView *view;
2177 FlatRange *fr;
2178 CoalescedMemoryRange *cmr;
2179 AddrRange tmp;
2180 MemoryRegionSection section;
2181
2182 view = address_space_get_flatview(as);
2183 FOR_EACH_FLAT_RANGE(fr, view) {
2184 if (fr->mr == mr) {
2185 section = (MemoryRegionSection) {
2186 .fv = view,
2187 .offset_within_address_space = int128_get64(fr->addr.start),
2188 .size = fr->addr.size,
2189 };
2190
2191 MEMORY_LISTENER_CALL(as, coalesced_mmio_del, Reverse, &section,
2192 int128_get64(fr->addr.start),
2193 int128_get64(fr->addr.size));
2194 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
2195 tmp = addrrange_shift(cmr->addr,
2196 int128_sub(fr->addr.start,
2197 int128_make64(fr->offset_in_region)));
2198 if (!addrrange_intersects(tmp, fr->addr)) {
2199 continue;
2200 }
2201 tmp = addrrange_intersection(tmp, fr->addr);
2202 MEMORY_LISTENER_CALL(as, coalesced_mmio_add, Forward, &section,
2203 int128_get64(tmp.start),
2204 int128_get64(tmp.size));
2205 }
2206 }
2207 }
2208 flatview_unref(view);
2209 }
2210
2211 static void memory_region_update_coalesced_range(MemoryRegion *mr)
2212 {
2213 AddressSpace *as;
2214
2215 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2216 memory_region_update_coalesced_range_as(mr, as);
2217 }
2218 }
2219
2220 void memory_region_set_coalescing(MemoryRegion *mr)
2221 {
2222 memory_region_clear_coalescing(mr);
2223 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
2224 }
2225
2226 void memory_region_add_coalescing(MemoryRegion *mr,
2227 hwaddr offset,
2228 uint64_t size)
2229 {
2230 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
2231
2232 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
2233 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2234 memory_region_update_coalesced_range(mr);
2235 memory_region_set_flush_coalesced(mr);
2236 }
2237
2238 void memory_region_clear_coalescing(MemoryRegion *mr)
2239 {
2240 CoalescedMemoryRange *cmr;
2241 bool updated = false;
2242
2243 qemu_flush_coalesced_mmio_buffer();
2244 mr->flush_coalesced_mmio = false;
2245
2246 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2247 cmr = QTAILQ_FIRST(&mr->coalesced);
2248 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
2249 g_free(cmr);
2250 updated = true;
2251 }
2252
2253 if (updated) {
2254 memory_region_update_coalesced_range(mr);
2255 }
2256 }
2257
2258 void memory_region_set_flush_coalesced(MemoryRegion *mr)
2259 {
2260 mr->flush_coalesced_mmio = true;
2261 }
2262
2263 void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2264 {
2265 qemu_flush_coalesced_mmio_buffer();
2266 if (QTAILQ_EMPTY(&mr->coalesced)) {
2267 mr->flush_coalesced_mmio = false;
2268 }
2269 }
2270
2271 void memory_region_clear_global_locking(MemoryRegion *mr)
2272 {
2273 mr->global_locking = false;
2274 }
2275
2276 static bool userspace_eventfd_warning;
2277
2278 void memory_region_add_eventfd(MemoryRegion *mr,
2279 hwaddr addr,
2280 unsigned size,
2281 bool match_data,
2282 uint64_t data,
2283 EventNotifier *e)
2284 {
2285 MemoryRegionIoeventfd mrfd = {
2286 .addr.start = int128_make64(addr),
2287 .addr.size = int128_make64(size),
2288 .match_data = match_data,
2289 .data = data,
2290 .e = e,
2291 };
2292 unsigned i;
2293
2294 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2295 userspace_eventfd_warning))) {
2296 userspace_eventfd_warning = true;
2297 error_report("Using eventfd without MMIO binding in KVM. "
2298 "Suboptimal performance expected");
2299 }
2300
2301 if (size) {
2302 adjust_endianness(mr, &mrfd.data, size);
2303 }
2304 memory_region_transaction_begin();
2305 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2306 if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) {
2307 break;
2308 }
2309 }
2310 ++mr->ioeventfd_nb;
2311 mr->ioeventfds = g_realloc(mr->ioeventfds,
2312 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2313 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2314 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2315 mr->ioeventfds[i] = mrfd;
2316 ioeventfd_update_pending |= mr->enabled;
2317 memory_region_transaction_commit();
2318 }
2319
2320 void memory_region_del_eventfd(MemoryRegion *mr,
2321 hwaddr addr,
2322 unsigned size,
2323 bool match_data,
2324 uint64_t data,
2325 EventNotifier *e)
2326 {
2327 MemoryRegionIoeventfd mrfd = {
2328 .addr.start = int128_make64(addr),
2329 .addr.size = int128_make64(size),
2330 .match_data = match_data,
2331 .data = data,
2332 .e = e,
2333 };
2334 unsigned i;
2335
2336 if (size) {
2337 adjust_endianness(mr, &mrfd.data, size);
2338 }
2339 memory_region_transaction_begin();
2340 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2341 if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) {
2342 break;
2343 }
2344 }
2345 assert(i != mr->ioeventfd_nb);
2346 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2347 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2348 --mr->ioeventfd_nb;
2349 mr->ioeventfds = g_realloc(mr->ioeventfds,
2350 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
2351 ioeventfd_update_pending |= mr->enabled;
2352 memory_region_transaction_commit();
2353 }
2354
2355 static void memory_region_update_container_subregions(MemoryRegion *subregion)
2356 {
2357 MemoryRegion *mr = subregion->container;
2358 MemoryRegion *other;
2359
2360 memory_region_transaction_begin();
2361
2362 memory_region_ref(subregion);
2363 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2364 if (subregion->priority >= other->priority) {
2365 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2366 goto done;
2367 }
2368 }
2369 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2370 done:
2371 memory_region_update_pending |= mr->enabled && subregion->enabled;
2372 memory_region_transaction_commit();
2373 }
2374
2375 static void memory_region_add_subregion_common(MemoryRegion *mr,
2376 hwaddr offset,
2377 MemoryRegion *subregion)
2378 {
2379 assert(!subregion->container);
2380 subregion->container = mr;
2381 subregion->addr = offset;
2382 memory_region_update_container_subregions(subregion);
2383 }
2384
2385 void memory_region_add_subregion(MemoryRegion *mr,
2386 hwaddr offset,
2387 MemoryRegion *subregion)
2388 {
2389 subregion->priority = 0;
2390 memory_region_add_subregion_common(mr, offset, subregion);
2391 }
2392
2393 void memory_region_add_subregion_overlap(MemoryRegion *mr,
2394 hwaddr offset,
2395 MemoryRegion *subregion,
2396 int priority)
2397 {
2398 subregion->priority = priority;
2399 memory_region_add_subregion_common(mr, offset, subregion);
2400 }
2401
2402 void memory_region_del_subregion(MemoryRegion *mr,
2403 MemoryRegion *subregion)
2404 {
2405 memory_region_transaction_begin();
2406 assert(subregion->container == mr);
2407 subregion->container = NULL;
2408 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
2409 memory_region_unref(subregion);
2410 memory_region_update_pending |= mr->enabled && subregion->enabled;
2411 memory_region_transaction_commit();
2412 }
2413
2414 void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2415 {
2416 if (enabled == mr->enabled) {
2417 return;
2418 }
2419 memory_region_transaction_begin();
2420 mr->enabled = enabled;
2421 memory_region_update_pending = true;
2422 memory_region_transaction_commit();
2423 }
2424
2425 void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2426 {
2427 Int128 s = int128_make64(size);
2428
2429 if (size == UINT64_MAX) {
2430 s = int128_2_64();
2431 }
2432 if (int128_eq(s, mr->size)) {
2433 return;
2434 }
2435 memory_region_transaction_begin();
2436 mr->size = s;
2437 memory_region_update_pending = true;
2438 memory_region_transaction_commit();
2439 }
2440
2441 static void memory_region_readd_subregion(MemoryRegion *mr)
2442 {
2443 MemoryRegion *container = mr->container;
2444
2445 if (container) {
2446 memory_region_transaction_begin();
2447 memory_region_ref(mr);
2448 memory_region_del_subregion(container, mr);
2449 mr->container = container;
2450 memory_region_update_container_subregions(mr);
2451 memory_region_unref(mr);
2452 memory_region_transaction_commit();
2453 }
2454 }
2455
2456 void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2457 {
2458 if (addr != mr->addr) {
2459 mr->addr = addr;
2460 memory_region_readd_subregion(mr);
2461 }
2462 }
2463
2464 void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
2465 {
2466 assert(mr->alias);
2467
2468 if (offset == mr->alias_offset) {
2469 return;
2470 }
2471
2472 memory_region_transaction_begin();
2473 mr->alias_offset = offset;
2474 memory_region_update_pending |= mr->enabled;
2475 memory_region_transaction_commit();
2476 }
2477
2478 uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2479 {
2480 return mr->align;
2481 }
2482
2483 static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2484 {
2485 const AddrRange *addr = addr_;
2486 const FlatRange *fr = fr_;
2487
2488 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2489 return -1;
2490 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2491 return 1;
2492 }
2493 return 0;
2494 }
2495
2496 static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
2497 {
2498 return bsearch(&addr, view->ranges, view->nr,
2499 sizeof(FlatRange), cmp_flatrange_addr);
2500 }
2501
2502 bool memory_region_is_mapped(MemoryRegion *mr)
2503 {
2504 return mr->container ? true : false;
2505 }
2506
2507 /* Same as memory_region_find, but it does not add a reference to the
2508 * returned region. It must be called from an RCU critical section.
2509 */
2510 static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2511 hwaddr addr, uint64_t size)
2512 {
2513 MemoryRegionSection ret = { .mr = NULL };
2514 MemoryRegion *root;
2515 AddressSpace *as;
2516 AddrRange range;
2517 FlatView *view;
2518 FlatRange *fr;
2519
2520 addr += mr->addr;
2521 for (root = mr; root->container; ) {
2522 root = root->container;
2523 addr += root->addr;
2524 }
2525
2526 as = memory_region_to_address_space(root);
2527 if (!as) {
2528 return ret;
2529 }
2530 range = addrrange_make(int128_make64(addr), int128_make64(size));
2531
2532 view = address_space_to_flatview(as);
2533 fr = flatview_lookup(view, range);
2534 if (!fr) {
2535 return ret;
2536 }
2537
2538 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
2539 --fr;
2540 }
2541
2542 ret.mr = fr->mr;
2543 ret.fv = view;
2544 range = addrrange_intersection(range, fr->addr);
2545 ret.offset_within_region = fr->offset_in_region;
2546 ret.offset_within_region += int128_get64(int128_sub(range.start,
2547 fr->addr.start));
2548 ret.size = range.size;
2549 ret.offset_within_address_space = int128_get64(range.start);
2550 ret.readonly = fr->readonly;
2551 return ret;
2552 }
2553
2554 MemoryRegionSection memory_region_find(MemoryRegion *mr,
2555 hwaddr addr, uint64_t size)
2556 {
2557 MemoryRegionSection ret;
2558 rcu_read_lock();
2559 ret = memory_region_find_rcu(mr, addr, size);
2560 if (ret.mr) {
2561 memory_region_ref(ret.mr);
2562 }
2563 rcu_read_unlock();
2564 return ret;
2565 }
2566
2567 bool memory_region_present(MemoryRegion *container, hwaddr addr)
2568 {
2569 MemoryRegion *mr;
2570
2571 rcu_read_lock();
2572 mr = memory_region_find_rcu(container, addr, 1).mr;
2573 rcu_read_unlock();
2574 return mr && mr != container;
2575 }
2576
2577 void memory_global_dirty_log_sync(void)
2578 {
2579 memory_region_sync_dirty_bitmap(NULL);
2580 }
2581
2582 static VMChangeStateEntry *vmstate_change;
2583
2584 void memory_global_dirty_log_start(void)
2585 {
2586 if (vmstate_change) {
2587 qemu_del_vm_change_state_handler(vmstate_change);
2588 vmstate_change = NULL;
2589 }
2590
2591 global_dirty_log = true;
2592
2593 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
2594
2595 /* Refresh DIRTY_LOG_MIGRATION bit. */
2596 memory_region_transaction_begin();
2597 memory_region_update_pending = true;
2598 memory_region_transaction_commit();
2599 }
2600
2601 static void memory_global_dirty_log_do_stop(void)
2602 {
2603 global_dirty_log = false;
2604
2605 /* Refresh DIRTY_LOG_MIGRATION bit. */
2606 memory_region_transaction_begin();
2607 memory_region_update_pending = true;
2608 memory_region_transaction_commit();
2609
2610 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
2611 }
2612
2613 static void memory_vm_change_state_handler(void *opaque, int running,
2614 RunState state)
2615 {
2616 if (running) {
2617 memory_global_dirty_log_do_stop();
2618
2619 if (vmstate_change) {
2620 qemu_del_vm_change_state_handler(vmstate_change);
2621 vmstate_change = NULL;
2622 }
2623 }
2624 }
2625
2626 void memory_global_dirty_log_stop(void)
2627 {
2628 if (!runstate_is_running()) {
2629 if (vmstate_change) {
2630 return;
2631 }
2632 vmstate_change = qemu_add_vm_change_state_handler(
2633 memory_vm_change_state_handler, NULL);
2634 return;
2635 }
2636
2637 memory_global_dirty_log_do_stop();
2638 }
2639
2640 static void listener_add_address_space(MemoryListener *listener,
2641 AddressSpace *as)
2642 {
2643 FlatView *view;
2644 FlatRange *fr;
2645
2646 if (listener->begin) {
2647 listener->begin(listener);
2648 }
2649 if (global_dirty_log) {
2650 if (listener->log_global_start) {
2651 listener->log_global_start(listener);
2652 }
2653 }
2654
2655 view = address_space_get_flatview(as);
2656 FOR_EACH_FLAT_RANGE(fr, view) {
2657 MemoryRegionSection section = section_from_flat_range(fr, view);
2658
2659 if (listener->region_add) {
2660 listener->region_add(listener, &section);
2661 }
2662 if (fr->dirty_log_mask && listener->log_start) {
2663 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2664 }
2665 }
2666 if (listener->commit) {
2667 listener->commit(listener);
2668 }
2669 flatview_unref(view);
2670 }
2671
2672 static void listener_del_address_space(MemoryListener *listener,
2673 AddressSpace *as)
2674 {
2675 FlatView *view;
2676 FlatRange *fr;
2677
2678 if (listener->begin) {
2679 listener->begin(listener);
2680 }
2681 view = address_space_get_flatview(as);
2682 FOR_EACH_FLAT_RANGE(fr, view) {
2683 MemoryRegionSection section = section_from_flat_range(fr, view);
2684
2685 if (fr->dirty_log_mask && listener->log_stop) {
2686 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2687 }
2688 if (listener->region_del) {
2689 listener->region_del(listener, &section);
2690 }
2691 }
2692 if (listener->commit) {
2693 listener->commit(listener);
2694 }
2695 flatview_unref(view);
2696 }
2697
2698 void memory_listener_register(MemoryListener *listener, AddressSpace *as)
2699 {
2700 MemoryListener *other = NULL;
2701
2702 listener->address_space = as;
2703 if (QTAILQ_EMPTY(&memory_listeners)
2704 || listener->priority >= QTAILQ_LAST(&memory_listeners,
2705 memory_listeners)->priority) {
2706 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2707 } else {
2708 QTAILQ_FOREACH(other, &memory_listeners, link) {
2709 if (listener->priority < other->priority) {
2710 break;
2711 }
2712 }
2713 QTAILQ_INSERT_BEFORE(other, listener, link);
2714 }
2715
2716 if (QTAILQ_EMPTY(&as->listeners)
2717 || listener->priority >= QTAILQ_LAST(&as->listeners,
2718 memory_listeners)->priority) {
2719 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2720 } else {
2721 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2722 if (listener->priority < other->priority) {
2723 break;
2724 }
2725 }
2726 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2727 }
2728
2729 listener_add_address_space(listener, as);
2730 }
2731
2732 void memory_listener_unregister(MemoryListener *listener)
2733 {
2734 if (!listener->address_space) {
2735 return;
2736 }
2737
2738 listener_del_address_space(listener, listener->address_space);
2739 QTAILQ_REMOVE(&memory_listeners, listener, link);
2740 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
2741 listener->address_space = NULL;
2742 }
2743
2744 void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
2745 {
2746 memory_region_ref(root);
2747 as->root = root;
2748 as->current_map = NULL;
2749 as->ioeventfd_nb = 0;
2750 as->ioeventfds = NULL;
2751 QTAILQ_INIT(&as->listeners);
2752 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
2753 as->name = g_strdup(name ? name : "anonymous");
2754 address_space_update_topology(as);
2755 address_space_update_ioeventfds(as);
2756 }
2757
2758 static void do_address_space_destroy(AddressSpace *as)
2759 {
2760 assert(QTAILQ_EMPTY(&as->listeners));
2761
2762 flatview_unref(as->current_map);
2763 g_free(as->name);
2764 g_free(as->ioeventfds);
2765 memory_region_unref(as->root);
2766 }
2767
2768 void address_space_destroy(AddressSpace *as)
2769 {
2770 MemoryRegion *root = as->root;
2771
2772 /* Flush out anything from MemoryListeners listening in on this */
2773 memory_region_transaction_begin();
2774 as->root = NULL;
2775 memory_region_transaction_commit();
2776 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2777
2778 /* At this point, as->dispatch and as->current_map are dummy
2779 * entries that the guest should never use. Wait for the old
2780 * values to expire before freeing the data.
2781 */
2782 as->root = root;
2783 call_rcu(as, do_address_space_destroy, rcu);
2784 }
2785
2786 static const char *memory_region_type(MemoryRegion *mr)
2787 {
2788 if (memory_region_is_ram_device(mr)) {
2789 return "ramd";
2790 } else if (memory_region_is_romd(mr)) {
2791 return "romd";
2792 } else if (memory_region_is_rom(mr)) {
2793 return "rom";
2794 } else if (memory_region_is_ram(mr)) {
2795 return "ram";
2796 } else {
2797 return "i/o";
2798 }
2799 }
2800
2801 typedef struct MemoryRegionList MemoryRegionList;
2802
2803 struct MemoryRegionList {
2804 const MemoryRegion *mr;
2805 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
2806 };
2807
2808 typedef QTAILQ_HEAD(mrqueue, MemoryRegionList) MemoryRegionListHead;
2809
2810 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2811 int128_sub((size), int128_one())) : 0)
2812 #define MTREE_INDENT " "
2813
2814 static void mtree_expand_owner(fprintf_function mon_printf, void *f,
2815 const char *label, Object *obj)
2816 {
2817 DeviceState *dev = (DeviceState *) object_dynamic_cast(obj, TYPE_DEVICE);
2818
2819 mon_printf(f, " %s:{%s", label, dev ? "dev" : "obj");
2820 if (dev && dev->id) {
2821 mon_printf(f, " id=%s", dev->id);
2822 } else {
2823 gchar *canonical_path = object_get_canonical_path(obj);
2824 if (canonical_path) {
2825 mon_printf(f, " path=%s", canonical_path);
2826 g_free(canonical_path);
2827 } else {
2828 mon_printf(f, " type=%s", object_get_typename(obj));
2829 }
2830 }
2831 mon_printf(f, "}");
2832 }
2833
2834 static void mtree_print_mr_owner(fprintf_function mon_printf, void *f,
2835 const MemoryRegion *mr)
2836 {
2837 Object *owner = mr->owner;
2838 Object *parent = memory_region_owner((MemoryRegion *)mr);
2839
2840 if (!owner && !parent) {
2841 mon_printf(f, " orphan");
2842 return;
2843 }
2844 if (owner) {
2845 mtree_expand_owner(mon_printf, f, "owner", owner);
2846 }
2847 if (parent && parent != owner) {
2848 mtree_expand_owner(mon_printf, f, "parent", parent);
2849 }
2850 }
2851
2852 static void mtree_print_mr(fprintf_function mon_printf, void *f,
2853 const MemoryRegion *mr, unsigned int level,
2854 hwaddr base,
2855 MemoryRegionListHead *alias_print_queue,
2856 bool owner)
2857 {
2858 MemoryRegionList *new_ml, *ml, *next_ml;
2859 MemoryRegionListHead submr_print_queue;
2860 const MemoryRegion *submr;
2861 unsigned int i;
2862 hwaddr cur_start, cur_end;
2863
2864 if (!mr) {
2865 return;
2866 }
2867
2868 for (i = 0; i < level; i++) {
2869 mon_printf(f, MTREE_INDENT);
2870 }
2871
2872 cur_start = base + mr->addr;
2873 cur_end = cur_start + MR_SIZE(mr->size);
2874
2875 /*
2876 * Try to detect overflow of memory region. This should never
2877 * happen normally. When it happens, we dump something to warn the
2878 * user who is observing this.
2879 */
2880 if (cur_start < base || cur_end < cur_start) {
2881 mon_printf(f, "[DETECTED OVERFLOW!] ");
2882 }
2883
2884 if (mr->alias) {
2885 MemoryRegionList *ml;
2886 bool found = false;
2887
2888 /* check if the alias is already in the queue */
2889 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
2890 if (ml->mr == mr->alias) {
2891 found = true;
2892 }
2893 }
2894
2895 if (!found) {
2896 ml = g_new(MemoryRegionList, 1);
2897 ml->mr = mr->alias;
2898 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
2899 }
2900 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
2901 " (prio %d, %s): alias %s @%s " TARGET_FMT_plx
2902 "-" TARGET_FMT_plx "%s",
2903 cur_start, cur_end,
2904 mr->priority,
2905 memory_region_type((MemoryRegion *)mr),
2906 memory_region_name(mr),
2907 memory_region_name(mr->alias),
2908 mr->alias_offset,
2909 mr->alias_offset + MR_SIZE(mr->size),
2910 mr->enabled ? "" : " [disabled]");
2911 if (owner) {
2912 mtree_print_mr_owner(mon_printf, f, mr);
2913 }
2914 } else {
2915 mon_printf(f,
2916 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %s): %s%s",
2917 cur_start, cur_end,
2918 mr->priority,
2919 memory_region_type((MemoryRegion *)mr),
2920 memory_region_name(mr),
2921 mr->enabled ? "" : " [disabled]");
2922 if (owner) {
2923 mtree_print_mr_owner(mon_printf, f, mr);
2924 }
2925 }
2926 mon_printf(f, "\n");
2927
2928 QTAILQ_INIT(&submr_print_queue);
2929
2930 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
2931 new_ml = g_new(MemoryRegionList, 1);
2932 new_ml->mr = submr;
2933 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
2934 if (new_ml->mr->addr < ml->mr->addr ||
2935 (new_ml->mr->addr == ml->mr->addr &&
2936 new_ml->mr->priority > ml->mr->priority)) {
2937 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
2938 new_ml = NULL;
2939 break;
2940 }
2941 }
2942 if (new_ml) {
2943 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
2944 }
2945 }
2946
2947 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
2948 mtree_print_mr(mon_printf, f, ml->mr, level + 1, cur_start,
2949 alias_print_queue, owner);
2950 }
2951
2952 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
2953 g_free(ml);
2954 }
2955 }
2956
2957 struct FlatViewInfo {
2958 fprintf_function mon_printf;
2959 void *f;
2960 int counter;
2961 bool dispatch_tree;
2962 bool owner;
2963 };
2964
2965 static void mtree_print_flatview(gpointer key, gpointer value,
2966 gpointer user_data)
2967 {
2968 FlatView *view = key;
2969 GArray *fv_address_spaces = value;
2970 struct FlatViewInfo *fvi = user_data;
2971 fprintf_function p = fvi->mon_printf;
2972 void *f = fvi->f;
2973 FlatRange *range = &view->ranges[0];
2974 MemoryRegion *mr;
2975 int n = view->nr;
2976 int i;
2977 AddressSpace *as;
2978
2979 p(f, "FlatView #%d\n", fvi->counter);
2980 ++fvi->counter;
2981
2982 for (i = 0; i < fv_address_spaces->len; ++i) {
2983 as = g_array_index(fv_address_spaces, AddressSpace*, i);
2984 p(f, " AS \"%s\", root: %s", as->name, memory_region_name(as->root));
2985 if (as->root->alias) {
2986 p(f, ", alias %s", memory_region_name(as->root->alias));
2987 }
2988 p(f, "\n");
2989 }
2990
2991 p(f, " Root memory region: %s\n",
2992 view->root ? memory_region_name(view->root) : "(none)");
2993
2994 if (n <= 0) {
2995 p(f, MTREE_INDENT "No rendered FlatView\n\n");
2996 return;
2997 }
2998
2999 while (n--) {
3000 mr = range->mr;
3001 if (range->offset_in_region) {
3002 p(f, MTREE_INDENT TARGET_FMT_plx "-"
3003 TARGET_FMT_plx " (prio %d, %s): %s @" TARGET_FMT_plx,
3004 int128_get64(range->addr.start),
3005 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
3006 mr->priority,
3007 range->readonly ? "rom" : memory_region_type(mr),
3008 memory_region_name(mr),
3009 range->offset_in_region);
3010 } else {
3011 p(f, MTREE_INDENT TARGET_FMT_plx "-"
3012 TARGET_FMT_plx " (prio %d, %s): %s",
3013 int128_get64(range->addr.start),
3014 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
3015 mr->priority,
3016 range->readonly ? "rom" : memory_region_type(mr),
3017 memory_region_name(mr));
3018 }
3019 if (fvi->owner) {
3020 mtree_print_mr_owner(p, f, mr);
3021 }
3022 p(f, "\n");
3023 range++;
3024 }
3025
3026 #if !defined(CONFIG_USER_ONLY)
3027 if (fvi->dispatch_tree && view->root) {
3028 mtree_print_dispatch(p, f, view->dispatch, view->root);
3029 }
3030 #endif
3031
3032 p(f, "\n");
3033 }
3034
3035 static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3036 gpointer user_data)
3037 {
3038 FlatView *view = key;
3039 GArray *fv_address_spaces = value;
3040
3041 g_array_unref(fv_address_spaces);
3042 flatview_unref(view);
3043
3044 return true;
3045 }
3046
3047 void mtree_info(fprintf_function mon_printf, void *f, bool flatview,
3048 bool dispatch_tree, bool owner)
3049 {
3050 MemoryRegionListHead ml_head;
3051 MemoryRegionList *ml, *ml2;
3052 AddressSpace *as;
3053
3054 if (flatview) {
3055 FlatView *view;
3056 struct FlatViewInfo fvi = {
3057 .mon_printf = mon_printf,
3058 .f = f,
3059 .counter = 0,
3060 .dispatch_tree = dispatch_tree,
3061 .owner = owner,
3062 };
3063 GArray *fv_address_spaces;
3064 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3065
3066 /* Gather all FVs in one table */
3067 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3068 view = address_space_get_flatview(as);
3069
3070 fv_address_spaces = g_hash_table_lookup(views, view);
3071 if (!fv_address_spaces) {
3072 fv_address_spaces = g_array_new(false, false, sizeof(as));
3073 g_hash_table_insert(views, view, fv_address_spaces);
3074 }
3075
3076 g_array_append_val(fv_address_spaces, as);
3077 }
3078
3079 /* Print */
3080 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3081
3082 /* Free */
3083 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3084 g_hash_table_unref(views);
3085
3086 return;
3087 }
3088
3089 QTAILQ_INIT(&ml_head);
3090
3091 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3092 mon_printf(f, "address-space: %s\n", as->name);
3093 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head, owner);
3094 mon_printf(f, "\n");
3095 }
3096
3097 /* print aliased regions */
3098 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
3099 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
3100 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head, owner);
3101 mon_printf(f, "\n");
3102 }
3103
3104 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
3105 g_free(ml);
3106 }
3107 }
3108
3109 void memory_region_init_ram(MemoryRegion *mr,
3110 struct Object *owner,
3111 const char *name,
3112 uint64_t size,
3113 Error **errp)
3114 {
3115 DeviceState *owner_dev;
3116 Error *err = NULL;
3117
3118 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3119 if (err) {
3120 error_propagate(errp, err);
3121 return;
3122 }
3123 /* This will assert if owner is neither NULL nor a DeviceState.
3124 * We only want the owner here for the purposes of defining a
3125 * unique name for migration. TODO: Ideally we should implement
3126 * a naming scheme for Objects which are not DeviceStates, in
3127 * which case we can relax this restriction.
3128 */
3129 owner_dev = DEVICE(owner);
3130 vmstate_register_ram(mr, owner_dev);
3131 }
3132
3133 void memory_region_init_rom(MemoryRegion *mr,
3134 struct Object *owner,
3135 const char *name,
3136 uint64_t size,
3137 Error **errp)
3138 {
3139 DeviceState *owner_dev;
3140 Error *err = NULL;
3141
3142 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3143 if (err) {
3144 error_propagate(errp, err);
3145 return;
3146 }
3147 /* This will assert if owner is neither NULL nor a DeviceState.
3148 * We only want the owner here for the purposes of defining a
3149 * unique name for migration. TODO: Ideally we should implement
3150 * a naming scheme for Objects which are not DeviceStates, in
3151 * which case we can relax this restriction.
3152 */
3153 owner_dev = DEVICE(owner);
3154 vmstate_register_ram(mr, owner_dev);
3155 }
3156
3157 void memory_region_init_rom_device(MemoryRegion *mr,
3158 struct Object *owner,
3159 const MemoryRegionOps *ops,
3160 void *opaque,
3161 const char *name,
3162 uint64_t size,
3163 Error **errp)
3164 {
3165 DeviceState *owner_dev;
3166 Error *err = NULL;
3167
3168 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3169 name, size, &err);
3170 if (err) {
3171 error_propagate(errp, err);
3172 return;
3173 }
3174 /* This will assert if owner is neither NULL nor a DeviceState.
3175 * We only want the owner here for the purposes of defining a
3176 * unique name for migration. TODO: Ideally we should implement
3177 * a naming scheme for Objects which are not DeviceStates, in
3178 * which case we can relax this restriction.
3179 */
3180 owner_dev = DEVICE(owner);
3181 vmstate_register_ram(mr, owner_dev);
3182 }
3183
3184 static const TypeInfo memory_region_info = {
3185 .parent = TYPE_OBJECT,
3186 .name = TYPE_MEMORY_REGION,
3187 .instance_size = sizeof(MemoryRegion),
3188 .instance_init = memory_region_initfn,
3189 .instance_finalize = memory_region_finalize,
3190 };
3191
3192 static const TypeInfo iommu_memory_region_info = {
3193 .parent = TYPE_MEMORY_REGION,
3194 .name = TYPE_IOMMU_MEMORY_REGION,
3195 .class_size = sizeof(IOMMUMemoryRegionClass),
3196 .instance_size = sizeof(IOMMUMemoryRegion),
3197 .instance_init = iommu_memory_region_initfn,
3198 .abstract = true,
3199 };
3200
3201 static void memory_register_types(void)
3202 {
3203 type_register_static(&memory_region_info);
3204 type_register_static(&iommu_memory_region_info);
3205 }
3206
3207 type_init(memory_register_types)
Mirror of https://git.qemu.org/git/qemu.git