nand_spl/board/amcc/bamboo/sdram.c

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/ppc4xx.h>
  10 #include <asm/processor.h>
  11 #include <asm/io.h>
  12
  13 static void wait_init_complete(void)
  14 {
  15         u32 val;
  16
  17         do {
  18                 mfsdram(SDRAM0_MCSTS, val);
  19         } while (!(val & 0x80000000));
  20 }
  21
  22 /*
  23  * phys_size_t initdram(int board_type)
  24  *
  25  * As the name already indicates, this function is called very early
  26  * from start.S and configures the SDRAM with fixed values. This is needed,
  27  * since the 440EP has no internal SRAM and the 4kB NAND_SPL loader has
  28  * not enough free space to implement the complete I2C SPD DDR autodetection
  29  * routines. Therefore the Bamboo only supports the onboard 64MBytes of SDRAM
  30  * when booting from NAND flash.
  31  *
  32  * Note:
  33  * As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed
  34  * DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM
  35  * modules are still plugged in. So it is recommended to remove the DIMM
  36  * modules while using the NAND booting code with the fixed SDRAM setup!
  37  */
  38 phys_size_t initdram(int board_type)
  39 {
  40         /*
  41          * Soft-reset SDRAM controller.
  42          */
  43         mtsdr(SDR0_SRST, SDR0_SRST_DMC);
  44         mtsdr(SDR0_SRST, 0x00000000);
  45
  46         /*
  47          * Disable memory controller.
  48          */
  49         mtsdram(SDRAM0_CFG0, 0x00000000);
  50
  51         /*
  52          * Setup some default
  53          */
  54         mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default)          */
  55         mtsdram(SDRAM0_SLIO, 0x00000000);       /* rdre=0 wrre=0 rarw=0         */
  56         mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal)              */
  57         mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0             */
  58         mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
  59
  60         /*
  61          * Following for CAS Latency = 2.5 @ 133 MHz PLB
  62          */
  63         mtsdram(SDRAM0_B0CR, 0x00082001);
  64         mtsdram(SDRAM0_TR0, 0x41094012);
  65         mtsdram(SDRAM0_TR1, 0x8080083d);        /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
  66         mtsdram(SDRAM0_RTR, 0x04100000);        /* Interval 7.8µs @ 133MHz PLB */
  67         mtsdram(SDRAM0_CFG1, 0x00000000);       /* Self-refresh exit, disable PM*/
  68
  69         /*
  70          * Enable the controller, then wait for DCEN to complete
  71          */
  72         mtsdram(SDRAM0_CFG0, 0x80000000); /* DCEN=1, PMUD=0*/
  73         wait_init_complete();
  74
  75         return CONFIG_SYS_MBYTES_SDRAM << 20;
  76 }