nand_spl/board/freescale/p1023rds/nand_boot.c

   1 /*
   2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3  * Author: Roy Zang <tie-fei.zang@freescale.com>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13  *
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  *
  21  */
  22
  23 #include <common.h>
  24 #include <ns16550.h>
  25 #include <asm/io.h>
  26 #include <nand.h>
  27 #include <asm/fsl_law.h>
  28
  29 /* Fixed sdram init -- doesn't use serial presence detect. */
  30 void sdram_init(void)
  31 {
  32         ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
  33
  34         set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
  35
  36         out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
  37         out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
  38         out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS);
  39         out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG);
  40         out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
  41         out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
  42         out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
  43         out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
  44         out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
  45         out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
  46         out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
  47         out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
  48         out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
  49         out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
  50         out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
  51         out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
  52         out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
  53         out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
  54         out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1);
  55         out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2);
  56         out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
  57 }
  58
  59 void board_init_f(ulong bootflag)
  60 {
  61         u32 plat_ratio, bus_clk;
  62         ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  63
  64         /* initialize selected port with appropriate baud rate */
  65         plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
  66         plat_ratio >>= 1;
  67         bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
  68         NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  69                         bus_clk / 16 / CONFIG_BAUDRATE);
  70
  71         puts("\nNAND boot... ");
  72         /* Initialize the DDR3 */
  73         sdram_init();
  74         /* copy code to RAM and jump to it - this should not return */
  75         /* NOTE - code has to be copied out of NAND buffer before
  76          * other blocks can be read.
  77          */
  78         relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
  79                         CONFIG_SYS_NAND_U_BOOT_RELOC);
  80 }
  81
  82 void board_init_r(gd_t *gd, ulong dest_addr)
  83 {
  84         nand_boot();
  85 }
  86
  87 void putc(char c)
  88 {
  89         if (c == '\n')
  90                 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
  91
  92         NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
  93 }
  94
  95 void puts(const char *str)
  96 {
  97         while (*str)
  98                 putc(*str++);
  99 }