opcodes/ChangeLog

   1 2019-11-05  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
   4         (REG_0F1C_P_0_MOD_0): ... this.
   5         (REG_0F1E_MOD_3): Rename to ...
   6         (REG_0F1E_P_1_MOD_3): ... this.
   7         (RM_0F01_REG_5): Rename to ...
   8         (RM_0F01_REG_5_MOD_3): ... this.
   9         (RM_0F01_REG_7): Rename to ...
  10         (RM_0F01_REG_7_MOD_3): ... this.
  11         (RM_0F1E_MOD_3_REG_7): Rename to ...
  12         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
  13         (RM_0FAE_REG_6): Rename to ...
  14         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
  15         (RM_0FAE_REG_7): Rename to ...
  16         (RM_0FAE_REG_7_MOD_3): ... this.
  17         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
  18         (PREFIX_0F01_REG_5_MOD_0): ... this.
  19         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
  20         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
  21         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
  22         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
  23         (PREFIX_0FAE_REG_0): Rename to ...
  24         (PREFIX_0FAE_REG_0_MOD_3): ... this.
  25         (PREFIX_0FAE_REG_1): Rename to ...
  26         (PREFIX_0FAE_REG_1_MOD_3): ... this.
  27         (PREFIX_0FAE_REG_2): Rename to ...
  28         (PREFIX_0FAE_REG_2_MOD_3): ... this.
  29         (PREFIX_0FAE_REG_3): Rename to ...
  30         (PREFIX_0FAE_REG_3_MOD_3): ... this.
  31         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
  32         (PREFIX_0FAE_REG_4_MOD_0): ... this.
  33         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
  34         (PREFIX_0FAE_REG_4_MOD_3): ... this.
  35         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
  36         (PREFIX_0FAE_REG_5_MOD_0): ... this.
  37         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
  38         (PREFIX_0FAE_REG_5_MOD_3): ... this.
  39         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
  40         (PREFIX_0FAE_REG_6_MOD_0): ... this.
  41         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
  42         (PREFIX_0FAE_REG_6_MOD_3): ... this.
  43         (PREFIX_0FAE_REG_7): Rename to ...
  44         (PREFIX_0FAE_REG_7_MOD_0): ... this.
  45         (PREFIX_MOD_0_0FC3): Rename to ...
  46         (PREFIX_0FC3_MOD_0): ... this.
  47         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
  48         (PREFIX_0FC7_REG_6_MOD_0): ... this.
  49         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
  50         (PREFIX_0FC7_REG_6_MOD_3): ... this.
  51         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
  52         (PREFIX_0FC7_REG_7_MOD_3): ... this.
  53         (reg_table, prefix_table, mod_table, rm_table): Adjust
  54         accordingly.
  55
  56 2019-11-04  Nick Clifton  <nickc@redhat.com>
  57
  58         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
  59         of a v850 system register.  Move the v850_sreg_names array into
  60         this function.
  61         (get_v850_reg_name): Likewise for ordinary register names.
  62         (get_v850_vreg_name): Likewise for vector register names.
  63         (get_v850_cc_name): Likewise for condition codes.
  64         * get_v850_float_cc_name): Likewise for floating point condition
  65         codes.
  66         (get_v850_cacheop_name): Likewise for cache-ops.
  67         (get_v850_prefop_name): Likewise for pref-ops.
  68         (disassemble): Use the new accessor functions.
  69
  70 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
  71
  72         * aarch64-opc.c (print_immediate_offset_address): Don't print the
  73         immediate for the writeback form of ldraa/ldrab if it is 0.
  74         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
  75         * aarch64-opc-2.c: Regenerated.
  76
  77 2019-10-30  Jan Beulich  <jbeulich@suse.com>
  78
  79         * i386-gen.c (operand_type_shorthands): Delete.
  80         (operand_type_init): Expand previous shorthands.
  81         (set_bitfield_from_shorthand): Rename back to ...
  82         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
  83         of operand_type_init[].
  84         (set_bitfield): Adjust call to the above function.
  85         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
  86         RegXMM, RegYMM, RegZMM): Define.
  87         * i386-reg.tbl: Expand prior shorthands.
  88
  89 2019-10-30  Jan Beulich  <jbeulich@suse.com>
  90
  91         * i386-gen.c (output_i386_opcode): Change order of fields
  92         emitted to output.
  93         * i386-opc.h (struct insn_template): Move operands field.
  94         Convert extension_opcode field to unsigned short.
  95         * i386-tbl.h: Re-generate.
  96
  97 2019-10-30  Jan Beulich  <jbeulich@suse.com>
  98
  99         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 100         of W.
 101         * i386-opc.h (W): Extend comment.
 102         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 103         general purpose variants not allowing for byte operands.
 104         * i386-tbl.h: Re-generate.
 105
 106 2019-10-29  Nick Clifton  <nickc@redhat.com>
 107
 108         * tic30-dis.c (print_branch): Correct size of operand array.
 109
 110 2019-10-29  Nick Clifton  <nickc@redhat.com>
 111
 112         * d30v-dis.c (print_insn): Check that operand index is valid
 113         before attempting to access the operands array.
 114
 115 2019-10-29  Nick Clifton  <nickc@redhat.com>
 116
 117         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 118         locating the bit to be tested.
 119
 120 2019-10-29  Nick Clifton  <nickc@redhat.com>
 121
 122         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 123         values.
 124         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 125         (print_insn_s12z):  Check for illegal size values.
 126
 127 2019-10-28  Nick Clifton  <nickc@redhat.com>
 128
 129         * csky-dis.c (csky_chars_to_number): Check for a negative
 130         count. Use an unsigned integer to construct the return value.
 131
 132 2019-10-28  Nick Clifton  <nickc@redhat.com>
 133
 134         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 135         operand buffer.  Set value to 15 not 13.
 136         (get_register_operand): Use OPERAND_BUFFER_LEN.
 137         (get_indirect_operand): Likewise.
 138         (print_two_operand): Likewise.
 139         (print_three_operand): Likewise.
 140         (print_oar_insn): Likewise.
 141
 142 2019-10-28  Nick Clifton  <nickc@redhat.com>
 143
 144         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 145         (bit_extract_simple): Likewise.
 146         (bit_copy): Likewise.
 147         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 148         index_offset array are not accessed.
 149
 150 2019-10-28  Nick Clifton  <nickc@redhat.com>
 151
 152         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 153         operand.
 154
 155 2019-10-25  Nick Clifton  <nickc@redhat.com>
 156
 157         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 158         access to opcodes.op array element.
 159
 160 2019-10-23  Nick Clifton  <nickc@redhat.com>
 161
 162         * rx-dis.c (get_register_name): Fix spelling typo in error
 163         message.
 164         (get_condition_name, get_flag_name, get_double_register_name)
 165         (get_double_register_high_name, get_double_register_low_name)
 166         (get_double_control_register_name, get_double_condition_name)
 167         (get_opsize_name, get_size_name): Likewise.
 168
 169 2019-10-22  Nick Clifton  <nickc@redhat.com>
 170
 171         * rx-dis.c (get_size_name): New function.  Provides safe
 172         access to name array.
 173         (get_opsize_name): Likewise.
 174         (print_insn_rx): Use the accessor functions.
 175
 176 2019-10-16  Nick Clifton  <nickc@redhat.com>
 177
 178         * rx-dis.c (get_register_name): New function.  Provides safe
 179         access to name array.
 180         (get_condition_name, get_flag_name, get_double_register_name)
 181         (get_double_register_high_name, get_double_register_low_name)
 182         (get_double_control_register_name, get_double_condition_name):
 183         Likewise.
 184         (print_insn_rx): Use the accessor functions.
 185
 186 2019-10-09  Nick Clifton  <nickc@redhat.com>
 187
 188         PR 25041
 189         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 190         instructions.
 191
 192 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 193
 194         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 195         (cmpsd): Likewise. Move EsSeg to other operand.
 196         * opcodes/i386-tbl.h: Re-generate.
 197
 198 2019-09-23  Alan Modra  <amodra@gmail.com>
 199
 200         * m68k-dis.c: Include cpu-m68k.h
 201
 202 2019-09-23  Alan Modra  <amodra@gmail.com>
 203
 204         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 205         "elf/mips.h" earlier.
 206
 207 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 208
 209         PR gas/25012
 210         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 211         with SReg operand.
 212         * i386-tbl.h: Re-generate.
 213
 214 2019-09-18  Alan Modra  <amodra@gmail.com>
 215
 216         * arc-ext.c: Update throughout for bfd section macro changes.
 217
 218 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 219
 220         * Makefile.in: Re-generate.
 221         * configure: Re-generate.
 222
 223 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 224
 225         * riscv-opc.c (riscv_opcodes): Change subset field
 226         to insn_class field for all instructions.
 227         (riscv_insn_types): Likewise.
 228
 229 2019-09-16  Phil Blundell  <pb@pbcl.net>
 230
 231         * configure: Regenerated.
 232
 233 2019-09-10  Miod Vallat  <miod@online.fr>
 234
 235         PR 24982
 236         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 237
 238 2019-09-09  Phil Blundell  <pb@pbcl.net>
 239
 240         binutils 2.33 branch created.
 241
 242 2019-09-03  Nick Clifton  <nickc@redhat.com>
 243
 244         PR 24961
 245         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 246         greater than zero before indexing via (bufcnt -1).
 247
 248 2019-09-03  Nick Clifton  <nickc@redhat.com>
 249
 250         PR 24958
 251         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 252         (MAX_SPEC_REG_NAME_LEN): Define.
 253         (struct mmix_dis_info): Use defined constants for array lengths.
 254         (get_reg_name): New function.
 255         (get_sprec_reg_name): New function.
 256         (print_insn_mmix): Use new functions.
 257
 258 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 259
 260         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 261         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 262         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 263
 264 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 265
 266         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 267         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 268         (aarch64_sys_reg_supported_p): Update checks for the above.
 269
 270 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 271
 272         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 273         cases MVE_SQRSHRL and MVE_UQRSHLL.
 274         (print_insn_mve): Add case for specifier 'k' to check
 275         specific bit of the instruction.
 276
 277 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 278
 279         PR 24854
 280         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 281         encountering an unknown machine type.
 282         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 283         cases return -1 rather than calling abort.
 284
 285 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 286
 287         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 288         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 289         IgnoreSize.
 290         * i386-tbl.h: Re-generate.
 291
 292 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 293
 294         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 295         instructions.
 296
 297 2019-07-30  Mel Chen <mel.chen@sifive.com>
 298
 299         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 300         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 301
 302         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 303         fscsr.
 304
 305 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 306
 307         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 308         and MPY class instructions.
 309         (parse_option): Add nps400 option.
 310         (print_arc_disassembler_options): Add nps400 info.
 311
 312 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 313
 314         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 315         (bspop): Likewise.
 316         (modapp): Likewise.
 317         * arc-opc.c (RAD_CHK): Add.
 318         * arc-tbl.h: Regenerate.
 319
 320 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 321
 322         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 323         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 324
 325 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 326
 327         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 328         instructions as UNPREDICTABLE.
 329
 330 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 331
 332         * bpf-desc.c: Regenerated.
 333
 334 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 335
 336         * i386-gen.c (static_assert): Define.
 337         (main): Use it.
 338         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 339         (Opcode_Modifier_Num): ... this.
 340         (Mem): Delete.
 341
 342 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 343
 344         * i386-gen.c (operand_types): Move RegMem ...
 345         (opcode_modifiers): ... here.
 346         * i386-opc.h (RegMem): Move to opcode modifer enum.
 347         (union i386_operand_type): Move regmem field ...
 348         (struct i386_opcode_modifier): ... here.
 349         * i386-opc.tbl (RegMem): Define.
 350         (mov, movq): Move RegMem on segment, control, debug, and test
 351         register flavors.
 352         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 353         to non-SSE2AVX flavor.
 354         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 355         Move RegMem on register only flavors. Drop IgnoreSize from
 356         legacy encoding flavors.
 357         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 358         flavors.
 359         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 360         register only flavors.
 361         (vmovd): Move RegMem and drop IgnoreSize on register only
 362         flavor. Change opcode and operand order to store form.
 363         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 364
 365 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 366
 367         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 368         entries.
 369         * i386-opc.h (SReg2, SReg3): Replace by ...
 370         (SReg): ... this.
 371         (union i386_operand_type): Replace sreg fields.
 372         * i386-opc.tbl (mov, ): Use SReg.
 373         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 374         register flavors.
 375         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 376         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 377
 378 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 379
 380         * bpf-desc.c: Regenerate.
 381         * bpf-opc.c: Likewise.
 382         * bpf-opc.h: Likewise.
 383
 384 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 385
 386         * bpf-desc.c: Regenerate.
 387         * bpf-opc.c: Likewise.
 388
 389 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 390
 391         * arm-dis.c (print_insn_coprocessor): Rename index to
 392         index_operand.
 393
 394 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 395
 396         * riscv-opc.c (riscv_insn_types): Add r4 type.
 397
 398         * riscv-opc.c (riscv_insn_types): Add b and j type.
 399
 400         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 401         format for sb type and correct s type.
 402
 403 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 404
 405         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 406         SVE FMOV alias of FCPY.
 407
 408 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 409
 410         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 411         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 412
 413 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 414
 415         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 416         registers in an instruction prefixed by MOVPRFX.
 417
 418 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 419
 420         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 421         sve_size_13 icode to account for variant behaviour of
 422         pmull{t,b}.
 423         * aarch64-dis-2.c: Regenerate.
 424         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 425         sve_size_13 icode to account for variant behaviour of
 426         pmull{t,b}.
 427         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 428         (OP_SVE_VVV_Q_D): Add new qualifier.
 429         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 430         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 431         AES and those not.
 432
 433 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 434
 435         * opcodes/i386-gen.c (operand_type_init): Remove
 436         OPERAND_TYPE_VEC_IMM4 entry.
 437         (operand_types): Remove Vec_Imm4.
 438         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 439         (union i386_operand_type): Remove vec_imm4.
 440         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 441         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 442
 443 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 444
 445         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 446         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 447         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 448         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 449         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 450         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 451         * i386-tbl.h: Re-generate.
 452
 453 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 454
 455         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 456         register operands.
 457         * i386-tbl.h: Re-generate.
 458
 459 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 460
 461         * i386-opc.tbl (C): New.
 462         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 463         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 464         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 465         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 466         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 467         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 468         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 469         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 470         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 471         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 472         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 473         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 474         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 475         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 476         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 477         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 478         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 479         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 480         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 481         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 482         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 483         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 484         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 485         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 486         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 487         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 488         flavors.
 489         * i386-tbl.h: Re-generate.
 490
 491 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 492
 493         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 494         register operands.
 495         * i386-tbl.h: Re-generate.
 496
 497 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 498
 499         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 500         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 501         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 502         * i386-tbl.h: Re-generate.
 503
 504 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 505
 506         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 507         Disp8MemShift from register only templates.
 508         * i386-tbl.h: Re-generate.
 509
 510 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 511
 512         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 513         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 514         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 515         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 516         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 517         EVEX_W_0F11_P_3_M_1): Delete.
 518         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 519         EVEX_W_0F11_P_3): New.
 520         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 521         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 522         MOD_EVEX_0F11_PREFIX_3 table entries.
 523         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 524         PREFIX_EVEX_0F11 table entries.
 525         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 526         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 527         EVEX_W_0F11_P_3_M_{0,1} table entries.
 528
 529 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 530
 531         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 532         Delete.
 533
 534 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 535
 536         PR binutils/24719
 537         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 538         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 539         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 540         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 541         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 542         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 543         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 544         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 545         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 546         PREFIX_EVEX_0F38C6_REG_6 entries.
 547         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 548         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 549         EVEX_W_0F38C7_R_6_P_2 entries.
 550         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 551         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 552         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 553         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 554         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 555         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 556         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 557
 558 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 559
 560         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 561         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 562         VEX_LEN_0F2D_P_3): Delete.
 563         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 564         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 565         (prefix_table): ... here.
 566
 567 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 568
 569         * i386-dis.c (Iq): Delete.
 570         (Id): New.
 571         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 572         TBM insns.
 573         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 574         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 575         (OP_E_memory): Also honor needindex when deciding whether an
 576         address size prefix needs printing.
 577         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 578
 579 2019-06-26  Jim Wilson  <jimw@sifive.com>
 580
 581         PR binutils/24739
 582         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 583         Set info->display_endian to info->endian_code.
 584
 585 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 586
 587         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 588         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 589         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 590         OPERAND_TYPE_ACC64 entries.
 591         * i386-init.h: Re-generate.
 592
 593 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 594
 595         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 596         Delete.
 597         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 598         of dqa_mode.
 599         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 600         entries here.
 601         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 602         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 603
 604 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 605
 606         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 607         variables.
 608
 609 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 610
 611         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 612         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 613         movnti.
 614         * i386-opc.tbl (movnti): Add IgnoreSize.
 615         * i386-tbl.h: Re-generate.
 616
 617 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 618
 619         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 620         * i386-tbl.h: Re-generate.
 621
 622 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 623
 624         * i386-dis-evex.h: Break into ...
 625         * i386-dis-evex-len.h: New file.
 626         * i386-dis-evex-mod.h: Likewise.
 627         * i386-dis-evex-prefix.h: Likewise.
 628         * i386-dis-evex-reg.h: Likewise.
 629         * i386-dis-evex-w.h: Likewise.
 630         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 631         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 632         i386-dis-evex-mod.h.
 633
 634 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 635
 636         PR binutils/24700
 637         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 638         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 639         EVEX_W_0F385B_P_2.
 640         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 641         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 642         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 643         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 644         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 645         EVEX_LEN_0F385B_P_2_W_1.
 646         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 647         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 648         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 649         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 650         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 651         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 652         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 653         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 654         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 655         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 656
 657 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 658
 659         PR binutils/24691
 660         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 661         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 662         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 663         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 664         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 665         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 666         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 667         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 668         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 669         EVEX_LEN_0F3A43_P_2_W_1.
 670         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 671         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 672         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 673         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 674         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 675         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 676         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 677         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 678         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 679         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 680         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 681         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 682
 683 2019-06-14  Nick Clifton  <nickc@redhat.com>
 684
 685         * po/fr.po; Updated French translation.
 686
 687 2019-06-13  Stafford Horne  <shorne@gmail.com>
 688
 689         * or1k-asm.c: Regenerated.
 690         * or1k-desc.c: Regenerated.
 691         * or1k-desc.h: Regenerated.
 692         * or1k-dis.c: Regenerated.
 693         * or1k-ibld.c: Regenerated.
 694         * or1k-opc.c: Regenerated.
 695         * or1k-opc.h: Regenerated.
 696         * or1k-opinst.c: Regenerated.
 697
 698 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 699
 700         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 701
 702 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 703
 704         PR binutils/24633
 705         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 706         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 707         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 708         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 709         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 710         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 711         EVEX_LEN_0F3A1B_P_2_W_1.
 712         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 713         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 714         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 715         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 716         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 717         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 718         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 719         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 720
 721 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 722
 723         PR binutils/24626
 724         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 725         EVEX.vvvv when disassembling VEX and EVEX instructions.
 726         (OP_VEX): Set vex.register_specifier to 0 after readding
 727         vex.register_specifier.
 728         (OP_Vex_2src_1): Likewise.
 729         (OP_Vex_2src_2): Likewise.
 730         (OP_LWP_E): Likewise.
 731         (OP_EX_Vex): Don't check vex.register_specifier.
 732         (OP_XMM_Vex): Likewise.
 733
 734 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 735             Lili Cui  <lili.cui@intel.com>
 736
 737         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 738         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 739         instructions.
 740         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 741         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 742         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 743         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 744         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 745         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 746         * i386-init.h: Regenerated.
 747         * i386-tbl.h: Likewise.
 748
 749 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 750             Lili Cui  <lili.cui@intel.com>
 751
 752         * doc/c-i386.texi: Document enqcmd.
 753         * testsuite/gas/i386/enqcmd-intel.d: New file.
 754         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 755         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 756         * testsuite/gas/i386/enqcmd.d: Likewise.
 757         * testsuite/gas/i386/enqcmd.s: Likewise.
 758         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 759         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 760         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 761         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 762         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 763         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 764         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 765         and x86-64-enqcmd.
 766
 767 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 768
 769         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 770
 771 2019-06-03  Alan Modra  <amodra@gmail.com>
 772
 773         * ppc-dis.c (prefix_opcd_indices): Correct size.
 774
 775 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 776
 777         PR gas/24625
 778         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 779         Disp8ShiftVL.
 780         * i386-tbl.h: Regenerated.
 781
 782 2019-05-24  Alan Modra  <amodra@gmail.com>
 783
 784         * po/POTFILES.in: Regenerate.
 785
 786 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 787             Alan Modra  <amodra@gmail.com>
 788
 789         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 790         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 791         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 792         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 793         XTOP>): Define and add entries.
 794         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 795         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 796         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 797         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 798
 799 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 800             Alan Modra  <amodra@gmail.com>
 801
 802         * ppc-dis.c (ppc_opts): Add "future" entry.
 803         (PREFIX_OPCD_SEGS): Define.
 804         (prefix_opcd_indices): New array.
 805         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 806         (lookup_prefix): New function.
 807         (print_insn_powerpc): Handle 64-bit prefix instructions.
 808         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 809         (PMRR, POWERXX): Define.
 810         (prefix_opcodes): New instruction table.
 811         (prefix_num_opcodes): New constant.
 812
 813 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 814
 815         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 816         * configure: Regenerated.
 817         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 818         and cpu/bpf.opc.
 819         (HFILES): Add bpf-desc.h and bpf-opc.h.
 820         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 821         bpf-ibld.c and bpf-opc.c.
 822         (BPF_DEPS): Define.
 823         * Makefile.in: Regenerated.
 824         * disassemble.c (ARCH_bpf): Define.
 825         (disassembler): Add case for bfd_arch_bpf.
 826         (disassemble_init_for_target): Likewise.
 827         (enum epbf_isa_attr): Define.
 828         * disassemble.h: extern print_insn_bpf.
 829         * bpf-asm.c: Generated.
 830         * bpf-opc.h: Likewise.
 831         * bpf-opc.c: Likewise.
 832         * bpf-ibld.c: Likewise.
 833         * bpf-dis.c: Likewise.
 834         * bpf-desc.h: Likewise.
 835         * bpf-desc.c: Likewise.
 836
 837 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 838
 839         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 840         and VMSR with the new operands.
 841
 842 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 843
 844         * arm-dis.c (enum mve_instructions): New enum
 845         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 846         and cneg.
 847         (mve_opcodes): New instructions as above.
 848         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 849         csneg and csel.
 850         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 851
 852 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 853
 854         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 855         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 856         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 857         uqshl, urshrl and urshr.
 858         (is_mve_okay_in_it): Add new instructions to TRUE list.
 859         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 860         (print_insn_mve): Updated to accept new %j,
 861         %<bitfield>m and %<bitfield>n patterns.
 862
 863 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 864
 865         * mips-opc.c (mips_builtin_opcodes): Change source register
 866         constraint for DAUI.
 867
 868 2019-05-20  Nick Clifton  <nickc@redhat.com>
 869
 870         * po/fr.po: Updated French translation.
 871
 872 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 873             Michael Collison <michael.collison@arm.com>
 874
 875         * arm-dis.c (thumb32_opcodes): Add new instructions.
 876         (enum mve_instructions): Likewise.
 877         (enum mve_undefined): Add new reasons.
 878         (is_mve_encoding_conflict): Handle new instructions.
 879         (is_mve_undefined): Likewise.
 880         (is_mve_unpredictable): Likewise.
 881         (print_mve_undefined): Likewise.
 882         (print_mve_size): Likewise.
 883
 884 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 885             Michael Collison <michael.collison@arm.com>
 886
 887         * arm-dis.c (thumb32_opcodes): Add new instructions.
 888         (enum mve_instructions): Likewise.
 889         (is_mve_encoding_conflict): Handle new instructions.
 890         (is_mve_undefined): Likewise.
 891         (is_mve_unpredictable): Likewise.
 892         (print_mve_size): Likewise.
 893
 894 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 895             Michael Collison <michael.collison@arm.com>
 896
 897         * arm-dis.c (thumb32_opcodes): Add new instructions.
 898         (enum mve_instructions): Likewise.
 899         (is_mve_encoding_conflict): Likewise.
 900         (is_mve_unpredictable): Likewise.
 901         (print_mve_size): Likewise.
 902
 903 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 904             Michael Collison <michael.collison@arm.com>
 905
 906         * arm-dis.c (thumb32_opcodes): Add new instructions.
 907         (enum mve_instructions): Likewise.
 908         (is_mve_encoding_conflict): Handle new instructions.
 909         (is_mve_undefined): Likewise.
 910         (is_mve_unpredictable): Likewise.
 911         (print_mve_size): Likewise.
 912
 913 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 914             Michael Collison <michael.collison@arm.com>
 915
 916         * arm-dis.c (thumb32_opcodes): Add new instructions.
 917         (enum mve_instructions): Likewise.
 918         (is_mve_encoding_conflict): Handle new instructions.
 919         (is_mve_undefined): Likewise.
 920         (is_mve_unpredictable): Likewise.
 921         (print_mve_size): Likewise.
 922         (print_insn_mve): Likewise.
 923
 924 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 925             Michael Collison <michael.collison@arm.com>
 926
 927         * arm-dis.c (thumb32_opcodes): Add new instructions.
 928         (print_insn_thumb32): Handle new instructions.
 929
 930 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 931             Michael Collison <michael.collison@arm.com>
 932
 933         * arm-dis.c (enum mve_instructions): Add new instructions.
 934         (enum mve_undefined): Add new reasons.
 935         (is_mve_encoding_conflict): Handle new instructions.
 936         (is_mve_undefined): Likewise.
 937         (is_mve_unpredictable): Likewise.
 938         (print_mve_undefined): Likewise.
 939         (print_mve_size): Likewise.
 940         (print_mve_shift_n): Likewise.
 941         (print_insn_mve): Likewise.
 942
 943 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 944             Michael Collison <michael.collison@arm.com>
 945
 946         * arm-dis.c (enum mve_instructions): Add new instructions.
 947         (is_mve_encoding_conflict): Handle new instructions.
 948         (is_mve_unpredictable): Likewise.
 949         (print_mve_rotate): Likewise.
 950         (print_mve_size): Likewise.
 951         (print_insn_mve): Likewise.
 952
 953 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 954             Michael Collison <michael.collison@arm.com>
 955
 956         * arm-dis.c (enum mve_instructions): Add new instructions.
 957         (is_mve_encoding_conflict): Handle new instructions.
 958         (is_mve_unpredictable): Likewise.
 959         (print_mve_size): Likewise.
 960         (print_insn_mve): Likewise.
 961
 962 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 963             Michael Collison <michael.collison@arm.com>
 964
 965         * arm-dis.c (enum mve_instructions): Add new instructions.
 966         (enum mve_undefined): Add new reasons.
 967         (is_mve_encoding_conflict): Handle new instructions.
 968         (is_mve_undefined): Likewise.
 969         (is_mve_unpredictable): Likewise.
 970         (print_mve_undefined): Likewise.
 971         (print_mve_size): Likewise.
 972         (print_insn_mve): Likewise.
 973
 974 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 975             Michael Collison <michael.collison@arm.com>
 976
 977         * arm-dis.c (enum mve_instructions): Add new instructions.
 978         (is_mve_encoding_conflict): Handle new instructions.
 979         (is_mve_undefined): Likewise.
 980         (is_mve_unpredictable): Likewise.
 981         (print_mve_size): Likewise.
 982         (print_insn_mve): Likewise.
 983
 984 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 985             Michael Collison <michael.collison@arm.com>
 986
 987         * arm-dis.c (enum mve_instructions): Add new instructions.
 988         (enum mve_unpredictable): Add new reasons.
 989         (enum mve_undefined): Likewise.
 990         (is_mve_okay_in_it): Handle new isntructions.
 991         (is_mve_encoding_conflict): Likewise.
 992         (is_mve_undefined): Likewise.
 993         (is_mve_unpredictable): Likewise.
 994         (print_mve_vmov_index): Likewise.
 995         (print_simd_imm8): Likewise.
 996         (print_mve_undefined): Likewise.
 997         (print_mve_unpredictable): Likewise.
 998         (print_mve_size): Likewise.
 999         (print_insn_mve): Likewise.
1000
1001 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1002             Michael Collison <michael.collison@arm.com>
1003
1004         * arm-dis.c (enum mve_instructions): Add new instructions.
1005         (enum mve_unpredictable): Add new reasons.
1006         (enum mve_undefined): Likewise.
1007         (is_mve_encoding_conflict): Handle new instructions.
1008         (is_mve_undefined): Likewise.
1009         (is_mve_unpredictable): Likewise.
1010         (print_mve_undefined): Likewise.
1011         (print_mve_unpredictable): Likewise.
1012         (print_mve_rounding_mode): Likewise.
1013         (print_mve_vcvt_size): Likewise.
1014         (print_mve_size): Likewise.
1015         (print_insn_mve): Likewise.
1016
1017 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1018             Michael Collison <michael.collison@arm.com>
1019
1020         * arm-dis.c (enum mve_instructions): Add new instructions.
1021         (enum mve_unpredictable): Add new reasons.
1022         (enum mve_undefined): Likewise.
1023         (is_mve_undefined): Handle new instructions.
1024         (is_mve_unpredictable): Likewise.
1025         (print_mve_undefined): Likewise.
1026         (print_mve_unpredictable): Likewise.
1027         (print_mve_size): Likewise.
1028         (print_insn_mve): Likewise.
1029
1030 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1031             Michael Collison <michael.collison@arm.com>
1032
1033         * arm-dis.c (enum mve_instructions): Add new instructions.
1034         (enum mve_undefined): Add new reasons.
1035         (insns): Add new instructions.
1036         (is_mve_encoding_conflict):
1037         (print_mve_vld_str_addr): New print function.
1038         (is_mve_undefined): Handle new instructions.
1039         (is_mve_unpredictable): Likewise.
1040         (print_mve_undefined): Likewise.
1041         (print_mve_size): Likewise.
1042         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1043         (print_insn_mve):  Handle new operands.
1044
1045 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1046             Michael Collison <michael.collison@arm.com>
1047
1048         * arm-dis.c (enum mve_instructions): Add new instructions.
1049         (enum mve_unpredictable): Add new reasons.
1050         (is_mve_encoding_conflict): Handle new instructions.
1051         (is_mve_unpredictable): Likewise.
1052         (mve_opcodes): Add new instructions.
1053         (print_mve_unpredictable): Handle new reasons.
1054         (print_mve_register_blocks): New print function.
1055         (print_mve_size): Handle new instructions.
1056         (print_insn_mve): Likewise.
1057
1058 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1059             Michael Collison <michael.collison@arm.com>
1060
1061         * arm-dis.c (enum mve_instructions): Add new instructions.
1062         (enum mve_unpredictable): Add new reasons.
1063         (enum mve_undefined): Likewise.
1064         (is_mve_encoding_conflict): Handle new instructions.
1065         (is_mve_undefined): Likewise.
1066         (is_mve_unpredictable): Likewise.
1067         (coprocessor_opcodes): Move NEON VDUP from here...
1068         (neon_opcodes): ... to here.
1069         (mve_opcodes): Add new instructions.
1070         (print_mve_undefined):  Handle new reasons.
1071         (print_mve_unpredictable): Likewise.
1072         (print_mve_size): Handle new instructions.
1073         (print_insn_neon): Handle vdup.
1074         (print_insn_mve): Handle new operands.
1075
1076 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1077             Michael Collison <michael.collison@arm.com>
1078
1079         * arm-dis.c (enum mve_instructions): Add new instructions.
1080         (enum mve_unpredictable): Add new values.
1081         (mve_opcodes): Add new instructions.
1082         (vec_condnames): New array with vector conditions.
1083         (mve_predicatenames): New array with predicate suffixes.
1084         (mve_vec_sizename): New array with vector sizes.
1085         (enum vpt_pred_state): New enum with vector predication states.
1086         (struct vpt_block): New struct type for vpt blocks.
1087         (vpt_block_state): Global struct to keep track of state.
1088         (mve_extract_pred_mask): New helper function.
1089         (num_instructions_vpt_block): Likewise.
1090         (mark_outside_vpt_block): Likewise.
1091         (mark_inside_vpt_block): Likewise.
1092         (invert_next_predicate_state): Likewise.
1093         (update_next_predicate_state): Likewise.
1094         (update_vpt_block_state): Likewise.
1095         (is_vpt_instruction): Likewise.
1096         (is_mve_encoding_conflict): Add entries for new instructions.
1097         (is_mve_unpredictable): Likewise.
1098         (print_mve_unpredictable): Handle new cases.
1099         (print_instruction_predicate): Likewise.
1100         (print_mve_size): New function.
1101         (print_vec_condition): New function.
1102         (print_insn_mve): Handle vpt blocks and new print operands.
1103
1104 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1105
1106         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1107         8, 14 and 15 for Armv8.1-M Mainline.
1108
1109 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1110             Michael Collison <michael.collison@arm.com>
1111
1112         * arm-dis.c (enum mve_instructions): New enum.
1113         (enum mve_unpredictable): Likewise.
1114         (enum mve_undefined): Likewise.
1115         (struct mopcode32): New struct.
1116         (is_mve_okay_in_it): New function.
1117         (is_mve_architecture): Likewise.
1118         (arm_decode_field): Likewise.
1119         (arm_decode_field_multiple): Likewise.
1120         (is_mve_encoding_conflict): Likewise.
1121         (is_mve_undefined): Likewise.
1122         (is_mve_unpredictable): Likewise.
1123         (print_mve_undefined): Likewise.
1124         (print_mve_unpredictable): Likewise.
1125         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1126         (print_insn_mve): New function.
1127         (print_insn_thumb32): Handle MVE architecture.
1128         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1129
1130 2019-05-10  Nick Clifton  <nickc@redhat.com>
1131
1132         PR 24538
1133         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1134         end of the table prematurely.
1135
1136 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1137
1138         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1139         macros for R6.
1140
1141 2019-05-11  Alan Modra  <amodra@gmail.com>
1142
1143         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1144         when -Mraw is in effect.
1145
1146 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1147
1148         * aarch64-dis-2.c: Regenerate.
1149         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1150         (OP_SVE_BBB): New variant set.
1151         (OP_SVE_DDDD): New variant set.
1152         (OP_SVE_HHH): New variant set.
1153         (OP_SVE_HHHU): New variant set.
1154         (OP_SVE_SSS): New variant set.
1155         (OP_SVE_SSSU): New variant set.
1156         (OP_SVE_SHH): New variant set.
1157         (OP_SVE_SBBU): New variant set.
1158         (OP_SVE_DSS): New variant set.
1159         (OP_SVE_DHHU): New variant set.
1160         (OP_SVE_VMV_HSD_BHS): New variant set.
1161         (OP_SVE_VVU_HSD_BHS): New variant set.
1162         (OP_SVE_VVVU_SD_BH): New variant set.
1163         (OP_SVE_VVVU_BHSD): New variant set.
1164         (OP_SVE_VVV_QHD_DBS): New variant set.
1165         (OP_SVE_VVV_HSD_BHS): New variant set.
1166         (OP_SVE_VVV_HSD_BHS2): New variant set.
1167         (OP_SVE_VVV_BHS_HSD): New variant set.
1168         (OP_SVE_VV_BHS_HSD): New variant set.
1169         (OP_SVE_VVV_SD): New variant set.
1170         (OP_SVE_VVU_BHS_HSD): New variant set.
1171         (OP_SVE_VZVV_SD): New variant set.
1172         (OP_SVE_VZVV_BH): New variant set.
1173         (OP_SVE_VZV_SD): New variant set.
1174         (aarch64_opcode_table): Add sve2 instructions.
1175
1176 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1177
1178         * aarch64-asm-2.c: Regenerated.
1179         * aarch64-dis-2.c: Regenerated.
1180         * aarch64-opc-2.c: Regenerated.
1181         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1182         for SVE_SHLIMM_UNPRED_22.
1183         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1184         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1185         operand.
1186
1187 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1188
1189         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1190         sve_size_tsz_bhs iclass encode.
1191         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1192         sve_size_tsz_bhs iclass decode.
1193
1194 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1195
1196         * aarch64-asm-2.c: Regenerated.
1197         * aarch64-dis-2.c: Regenerated.
1198         * aarch64-opc-2.c: Regenerated.
1199         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1200         for SVE_Zm4_11_INDEX.
1201         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1202         (fields): Handle SVE_i2h field.
1203         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1204         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1205
1206 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1207
1208         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1209         sve_shift_tsz_bhsd iclass encode.
1210         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1211         sve_shift_tsz_bhsd iclass decode.
1212
1213 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1214
1215         * aarch64-asm-2.c: Regenerated.
1216         * aarch64-dis-2.c: Regenerated.
1217         * aarch64-opc-2.c: Regenerated.
1218         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1219         (aarch64_encode_variant_using_iclass): Handle
1220         sve_shift_tsz_hsd iclass encode.
1221         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1222         sve_shift_tsz_hsd iclass decode.
1223         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1224         for SVE_SHRIMM_UNPRED_22.
1225         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1226         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1227         operand.
1228
1229 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1230
1231         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1232         sve_size_013 iclass encode.
1233         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1234         sve_size_013 iclass decode.
1235
1236 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1237
1238         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1239         sve_size_bh iclass encode.
1240         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1241         sve_size_bh iclass decode.
1242
1243 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1244
1245         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1246         sve_size_sd2 iclass encode.
1247         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1248         sve_size_sd2 iclass decode.
1249         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1250         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1251
1252 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1253
1254         * aarch64-asm-2.c: Regenerated.
1255         * aarch64-dis-2.c: Regenerated.
1256         * aarch64-opc-2.c: Regenerated.
1257         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1258         for SVE_ADDR_ZX.
1259         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1260         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1261
1262 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1263
1264         * aarch64-asm-2.c: Regenerated.
1265         * aarch64-dis-2.c: Regenerated.
1266         * aarch64-opc-2.c: Regenerated.
1267         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1268         for SVE_Zm3_11_INDEX.
1269         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1270         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1271         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1272         fields.
1273         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1274
1275 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1276
1277         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1278         sve_size_hsd2 iclass encode.
1279         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1280         sve_size_hsd2 iclass decode.
1281         * aarch64-opc.c (fields): Handle SVE_size field.
1282         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1283
1284 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1285
1286         * aarch64-asm-2.c: Regenerated.
1287         * aarch64-dis-2.c: Regenerated.
1288         * aarch64-opc-2.c: Regenerated.
1289         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1290         for SVE_IMM_ROT3.
1291         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1292         (fields): Handle SVE_rot3 field.
1293         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1294         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1295
1296 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1297
1298         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1299         instructions.
1300
1301 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1302
1303         * aarch64-tbl.h
1304         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1305         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1306         aarch64_feature_sve2bitperm): New feature sets.
1307         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1308         for feature set addresses.
1309         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1310         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1311
1312 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1313             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1314
1315         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1316         argument and set ASE_EVA_R6 appropriately.
1317         (set_default_mips_dis_options): Pass ISA to above.
1318         (parse_mips_dis_option): Likewise.
1319         * mips-opc.c (EVAR6): New macro.
1320         (mips_builtin_opcodes): Add llwpe, scwpe.
1321
1322 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1323
1324         * aarch64-asm-2.c: Regenerated.
1325         * aarch64-dis-2.c: Regenerated.
1326         * aarch64-opc-2.c: Regenerated.
1327         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1328         AARCH64_OPND_TME_UIMM16.
1329         (aarch64_print_operand): Likewise.
1330         * aarch64-tbl.h (QL_IMM_NIL): New.
1331         (TME): New.
1332         (_TME_INSN): New.
1333         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1334
1335 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1336
1337         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1338
1339 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1340             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1341
1342         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1343
1344 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1345
1346         * s12z-opc.h: Add extern "C" bracketing to help
1347         users who wish to use this interface in c++ code.
1348
1349 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1350
1351         * s12z-opc.c (bm_decode): Handle bit map operations with the
1352         "reserved0" mode.
1353
1354 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1355
1356         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1357         specifier.  Add entries for VLDR and VSTR of system registers.
1358         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1359         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1360         of %J and %K format specifier.
1361
1362 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1363
1364         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1365         Add new entries for VSCCLRM instruction.
1366         (print_insn_coprocessor): Handle new %C format control code.
1367
1368 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1369
1370         * arm-dis.c (enum isa): New enum.
1371         (struct sopcode32): New structure.
1372         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1373         set isa field of all current entries to ANY.
1374         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1375         Only match an entry if its isa field allows the current mode.
1376
1377 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1378
1379         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1380         CLRM.
1381         (print_insn_thumb32): Add logic to print %n CLRM register list.
1382
1383 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1384
1385         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1386         and %Q patterns.
1387
1388 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1389
1390         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1391         (print_insn_thumb32): Edit the switch case for %Z.
1392
1393 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1394
1395         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1396
1397 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1398
1399         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1400
1401 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1402
1403         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1404
1405 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1406
1407         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1408         Arm register with r13 and r15 unpredictable.
1409         (thumb32_opcodes): New instructions for bfx and bflx.
1410
1411 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1412
1413         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1414
1415 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1416
1417         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1418
1419 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1420
1421         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1422
1423 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1424
1425         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1426
1427 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1428
1429         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1430         "optr". ("operator" is a reserved word in c++).
1431
1432 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1433
1434         * aarch64-opc.c (aarch64_print_operand): Add case for
1435         AARCH64_OPND_Rt_SP.
1436         (verify_constraints): Likewise.
1437         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1438         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1439         to accept Rt|SP as first operand.
1440         (AARCH64_OPERANDS): Add new Rt_SP.
1441         * aarch64-asm-2.c: Regenerated.
1442         * aarch64-dis-2.c: Regenerated.
1443         * aarch64-opc-2.c: Regenerated.
1444
1445 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1446
1447         * aarch64-asm-2.c: Regenerated.
1448         * aarch64-dis-2.c: Likewise.
1449         * aarch64-opc-2.c: Likewise.
1450         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1451
1452 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1453
1454         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1455
1456 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1457
1458         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1459         * i386-init.h: Regenerated.
1460
1461 2019-04-07  Alan Modra  <amodra@gmail.com>
1462
1463         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1464         op_separator to control printing of spaces, comma and parens
1465         rather than need_comma, need_paren and spaces vars.
1466
1467 2019-04-07  Alan Modra  <amodra@gmail.com>
1468
1469         PR 24421
1470         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1471         (print_insn_neon, print_insn_arm): Likewise.
1472
1473 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1474
1475         * i386-dis-evex.h (evex_table): Updated to support BF16
1476         instructions.
1477         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1478         and EVEX_W_0F3872_P_3.
1479         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1480         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1481         * i386-opc.h (enum): Add CpuAVX512_BF16.
1482         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1483         * i386-opc.tbl: Add AVX512 BF16 instructions.
1484         * i386-init.h: Regenerated.
1485         * i386-tbl.h: Likewise.
1486
1487 2019-04-05  Alan Modra  <amodra@gmail.com>
1488
1489         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1490         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1491         to favour printing of "-" branch hint when using the "y" bit.
1492         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1493
1494 2019-04-05  Alan Modra  <amodra@gmail.com>
1495
1496         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1497         opcode until first operand is output.
1498
1499 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1500
1501         PR gas/24349
1502         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1503         (valid_bo_post_v2): Add support for 'at' branch hints.
1504         (insert_bo): Only error on branch on ctr.
1505         (get_bo_hint_mask): New function.
1506         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1507         for inserting 'at' branch hints.
1508         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1509         for extracting 'at' branch hints.
1510         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1511         (BOE): Delete operand.
1512         (BOM, BOP): New operands.
1513         (RM): Update value.
1514         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1515         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1516         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1517         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1518         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1519         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1520         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1521         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1522         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1523         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1524         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1525         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1526         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1527         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1528         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1529         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1530         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1531         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1532         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1533         bttarl+>: New extended mnemonics.
1534
1535 2019-03-28  Alan Modra  <amodra@gmail.com>
1536
1537         PR 24390
1538         * ppc-opc.c (BTF): Define.
1539         (powerpc_opcodes): Use for mtfsb*.
1540         * ppc-dis.c (print_insn_powerpc): Print fields with both
1541         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1542
1543 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1544
1545         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1546         (mapping_symbol_for_insn): Implement new algorithm.
1547         (print_insn): Remove duplicate code.
1548
1549 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1550
1551         * aarch64-dis.c (print_insn_aarch64):
1552         Implement override.
1553
1554 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1555
1556         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1557         order.
1558
1559 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1560
1561         * aarch64-dis.c (last_stop_offset): New.
1562         (print_insn_aarch64): Use stop_offset.
1563
1564 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1565
1566         PR gas/24359
1567         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1568         CPU_ANY_AVX2_FLAGS.
1569         * i386-init.h: Regenerated.
1570
1571 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1572
1573         PR gas/24348
1574         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1575         vmovdqu16, vmovdqu32 and vmovdqu64.
1576         * i386-tbl.h: Regenerated.
1577
1578 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1579
1580         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1581         from vstrszb, vstrszh, and vstrszf.
1582
1583 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1584
1585         * s390-opc.txt: Add instruction descriptions.
1586
1587 2019-02-08  Jim Wilson  <jimw@sifive.com>
1588
1589         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1590         <bne>: Likewise.
1591
1592 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1593
1594         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1595
1596 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1597
1598         PR binutils/23212
1599         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1600         * aarch64-opc.c (verify_elem_sd): New.
1601         (fields): Add FLD_sz entr.
1602         * aarch64-tbl.h (_SIMD_INSN): New.
1603         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1604         fmulx scalar and vector by element isns.
1605
1606 2019-02-07  Nick Clifton  <nickc@redhat.com>
1607
1608         * po/sv.po: Updated Swedish translation.
1609
1610 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1611
1612         * s390-mkopc.c (main): Accept arch13 as cpu string.
1613         * s390-opc.c: Add new instruction formats and instruction opcode
1614         masks.
1615         * s390-opc.txt: Add new arch13 instructions.
1616
1617 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1618
1619         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1620         (aarch64_opcode): Change encoding for stg, stzg
1621         st2g and st2zg.
1622         * aarch64-asm-2.c: Regenerated.
1623         * aarch64-dis-2.c: Regenerated.
1624         * aarch64-opc-2.c: Regenerated.
1625
1626 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1627
1628         * aarch64-asm-2.c: Regenerated.
1629         * aarch64-dis-2.c: Likewise.
1630         * aarch64-opc-2.c: Likewise.
1631         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1632
1633 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1634             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1635
1636         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1637         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1638         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1639         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1640         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1641         case for ldstgv_indexed.
1642         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1643         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1644         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1645         * aarch64-asm-2.c: Regenerated.
1646         * aarch64-dis-2.c: Regenerated.
1647         * aarch64-opc-2.c: Regenerated.
1648
1649 2019-01-23  Nick Clifton  <nickc@redhat.com>
1650
1651         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1652
1653 2019-01-21  Nick Clifton  <nickc@redhat.com>
1654
1655         * po/de.po: Updated German translation.
1656         * po/uk.po: Updated Ukranian translation.
1657
1658 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1659         * mips-dis.c (mips_arch_choices): Fix typo in
1660         gs464, gs464e and gs264e descriptors.
1661
1662 2019-01-19  Nick Clifton  <nickc@redhat.com>
1663
1664         * configure: Regenerate.
1665         * po/opcodes.pot: Regenerate.
1666
1667 2018-06-24  Nick Clifton  <nickc@redhat.com>
1668
1669         2.32 branch created.
1670
1671 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1672
1673         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1674         if it is null.
1675         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1676         zero.
1677
1678 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1679
1680         * configure: Regenerate.
1681
1682 2019-01-07  Alan Modra  <amodra@gmail.com>
1683
1684         * configure: Regenerate.
1685         * po/POTFILES.in: Regenerate.
1686
1687 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1688
1689         * s12z-opc.c: New file.
1690         * s12z-opc.h: New file.
1691         * s12z-dis.c: Removed all code not directly related to display
1692         of instructions.  Used the interface provided by the new files
1693         instead.
1694         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1695         * Makefile.in: Regenerate.
1696         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1697         * configure: Regenerate.
1698
1699 2019-01-01  Alan Modra  <amodra@gmail.com>
1700
1701         Update year range in copyright notice of all files.
1702
1703 For older changes see ChangeLog-2018
1704 \f
1705 Copyright (C) 2019 Free Software Foundation, Inc.
1706
1707 Copying and distribution of this file, with or without modification,
1708 are permitted in any medium without royalty provided the copyright
1709 notice and this notice are preserved.
1710
1711 Local Variables:
1712 mode: change-log
1713 left-margin: 8
1714 fill-column: 74
1715 version-control: never
1716 End: