1 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
3 * csky-dis.c (csky_output_operand): Add handlers for
4 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
5 OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
6 to support FPUV3 instructions.
7 * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
8 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
9 OPRND_TYPE_DFLOAT_FMOVI.
10 (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
11 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
12 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
13 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
14 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
15 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
16 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
17 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
18 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
19 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
20 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
21 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
22 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
23 (csky_v2_opcodes): Add FPUV3 instructions.
25 2020-09-08 Alex Coplan <alex.coplan@arm.com>
27 * aarch64-dis.c (print_operands): Pass CPU features to
28 aarch64_print_operand().
29 * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
30 preferred disassembly of system registers.
31 (SR_RNG): Refactor to use new SR_FEAT2 macro.
38 (SR_EXPAND_EL12): New.
39 (aarch64_sys_regs): Specify which registers are only on
40 A-profile, add R-profile system registers.
44 (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
47 2020-09-08 Alex Coplan <alex.coplan@arm.com>
49 * aarch64-tbl.h (aarch64_feature_v8_r): New.
52 (aarch64_opcode_table): Add dfb.
53 * aarch64-opc-2.c: Regenerate.
54 * aarch64-asm-2.c: Regenerate.
55 * aarch64-dis-2.c: Regenerate.
57 2020-09-08 Alex Coplan <alex.coplan@arm.com>
59 * aarch64-dis.c (arch_variant): New.
60 (determine_disassembling_preference): Disassemble according to
62 (select_aarch64_variant): New.
63 (print_insn_aarch64): Set feature set.
65 2020-09-02 Alan Modra <amodra@gmail.com>
67 * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
68 (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
69 (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
70 (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
71 (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
72 (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
73 (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
74 for value parameter and update code to suit.
75 (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
76 (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
78 2020-09-02 Alan Modra <amodra@gmail.com>
80 * i386-dis.c (OP_E_memory): Don't cast to signed type when
82 (get32, get32s): Use unsigned types in shift expressions.
84 2020-09-02 Alan Modra <amodra@gmail.com>
86 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
88 2020-09-02 Alan Modra <amodra@gmail.com>
90 * crx-dis.c: Whitespace.
91 (print_arg): Use unsigned type for longdisp and mask variables,
92 and for left shift constant.
94 2020-09-02 Alan Modra <amodra@gmail.com>
96 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
97 * bpf-ibld.c: Regenerate.
98 * epiphany-ibld.c: Regenerate.
99 * fr30-ibld.c: Regenerate.
100 * frv-ibld.c: Regenerate.
101 * ip2k-ibld.c: Regenerate.
102 * iq2000-ibld.c: Regenerate.
103 * lm32-ibld.c: Regenerate.
104 * m32c-ibld.c: Regenerate.
105 * m32r-ibld.c: Regenerate.
106 * mep-ibld.c: Regenerate.
107 * mt-ibld.c: Regenerate.
108 * or1k-ibld.c: Regenerate.
109 * xc16x-ibld.c: Regenerate.
110 * xstormy16-ibld.c: Regenerate.
112 2020-09-02 Alan Modra <amodra@gmail.com>
114 * bfin-dis.c (MASKBITS): Use SIGNBIT.
116 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
118 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
119 to CSKYV2_ISA_3E3R3 instruction set.
121 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
123 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
125 2020-09-01 Alan Modra <amodra@gmail.com>
127 * mep-ibld.c: Regenerate.
129 2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
131 * csky-dis.c (csky_output_operand): Assign dis_info.value for
134 2020-08-30 Alan Modra <amodra@gmail.com>
136 * cr16-dis.c: Formatting.
137 (parameter): Delete struct typedef. Use dwordU instead
139 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
141 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
143 2020-08-29 Alan Modra <amodra@gmail.com>
146 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
147 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
149 2020-08-28 Alan Modra <amodra@gmail.com>
153 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
154 (extract_normal): Likewise.
155 (insert_normal): Likewise, and move past zero length test.
156 (put_insn_int_value): Handle mask for zero length, use 1UL.
157 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
158 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
159 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
160 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
162 2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
164 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
165 (csky_dis_info): Add member isa.
166 (csky_find_inst_info): Skip instructions that do not belong to
168 (csky_get_disassembler): Get infomation from attribute section.
169 (print_insn_csky): Set defualt ISA flag.
170 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
171 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
172 isa_flag32'type to unsigned 64 bits.
174 2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
176 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
178 2020-08-26 David Faust <david.faust@oracle.com>
180 * bpf-desc.c: Regenerate.
181 * bpf-desc.h: Likewise.
182 * bpf-opc.c: Likewise.
183 * bpf-opc.h: Likewise.
184 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
185 ISA when appropriate.
187 2020-08-25 Alan Modra <amodra@gmail.com>
190 * vax-dis.c (parse_disassembler_options): Always add at least one
191 to entry_addr_total_slots.
193 2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
195 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
196 in other CPUs to speed up disassembling.
197 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
198 Change plsli.u16 to plsli.16, change sync's operand format.
200 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
202 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
204 2020-08-21 Nick Clifton <nickc@redhat.com>
206 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
209 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
211 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
213 2020-08-19 Alan Modra <amodra@gmail.com>
215 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
218 2020-08-18 Peter Bergner <bergner@linux.ibm.com>
220 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
221 <xvcvbf16spn>: ...to this.
223 2020-08-12 Alex Coplan <alex.coplan@arm.com>
225 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
227 2020-08-12 Nick Clifton <nickc@redhat.com>
229 * po/sr.po: Updated Serbian translation.
231 2020-08-11 Alan Modra <amodra@gmail.com>
233 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
235 2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
237 * aarch64-opc.c (aarch64_print_operand):
238 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
239 (aarch64_sys_reg_supported_p): Function removed.
240 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
241 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
244 2020-08-10 Alan Modra <amodra@gmail.com>
246 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
249 2020-08-10 Alan Modra <amodra@gmail.com>
251 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
252 Enable icbt for power5, miso for power8.
254 2020-08-10 Alan Modra <amodra@gmail.com>
256 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
257 mtvsrd, and similarly for mfvsrd.
259 2020-08-04 Christian Groessler <chris@groessler.org>
260 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
262 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
263 opcodes (special "out" to absolute address).
264 * z8k-opc.h: Regenerate.
266 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
269 * i386-opc.h (Prefix_Disp8): New.
270 (Prefix_Disp16): Likewise.
271 (Prefix_Disp32): Likewise.
272 (Prefix_Load): Likewise.
273 (Prefix_Store): Likewise.
274 (Prefix_VEX): Likewise.
275 (Prefix_VEX3): Likewise.
276 (Prefix_EVEX): Likewise.
277 (Prefix_REX): Likewise.
278 (Prefix_NoOptimize): Likewise.
279 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
280 * i386-tbl.h: Regenerated.
282 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
284 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
285 default case with abort() instead of printing an error message and
286 continuing, to avoid a maybe-uninitialized warning.
288 2020-07-24 Nick Clifton <nickc@redhat.com>
290 * po/de.po: Updated German translation.
292 2020-07-21 Jan Beulich <jbeulich@suse.com>
294 * i386-dis.c (OP_E_memory): Revert previous change.
296 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
299 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
300 without base nor index registers.
302 2020-07-15 Jan Beulich <jbeulich@suse.com>
304 * i386-dis.c (putop): Move 'V' and 'W' handling.
306 2020-07-15 Jan Beulich <jbeulich@suse.com>
308 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
309 construct for push/pop of register.
310 (putop): Honor cond when handling 'P'. Drop handling of plain
313 2020-07-15 Jan Beulich <jbeulich@suse.com>
315 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
316 description. Drop '&' description. Use P for push of immediate,
317 pushf/popf, enter, and leave. Use %LP for lret/retf.
318 (dis386_twobyte): Use P for push/pop of fs/gs.
319 (reg_table): Use P for push/pop. Use @ for near call/jmp.
320 (x86_64_table): Use P for far call/jmp.
321 (putop): Drop handling of 'U' and '&'. Move and adjust handling
322 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
324 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
325 and dqw_mode (unconditional).
327 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
330 * i386-dis.c (OP_E_memory): Without base nor index registers,
331 32-bit displacement to 64 bits.
333 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
335 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
336 faulty double register pair is detected.
338 2020-07-14 Jan Beulich <jbeulich@suse.com>
340 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
342 2020-07-14 Jan Beulich <jbeulich@suse.com>
344 * i386-dis.c (OP_R, Rm): Delete.
345 (MOD_0F24, MOD_0F26): Rename to ...
346 (X86_64_0F24, X86_64_0F26): ... respectively.
347 (dis386): Update 'L' and 'Z' comments.
348 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
350 (mod_table): Move opcode 0F24 and 0F26 entries ...
351 (x86_64_table): ... here.
352 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
355 2020-07-14 Jan Beulich <jbeulich@suse.com>
357 * i386-dis.c (Rd, Rdq, MaskR): Delete.
358 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
359 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
360 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
361 MOD_EVEX_0F387C): New enumerators.
362 (reg_table): Use Edq for rdssp.
363 (prefix_table): Use Edq for incssp.
364 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
365 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
366 ktest*, and kshift*. Use Edq / MaskE for kmov*.
367 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
368 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
369 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
370 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
371 0F3828_P_1 and 0F3838_P_1.
372 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
373 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
375 2020-07-14 Jan Beulich <jbeulich@suse.com>
377 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
378 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
379 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
380 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
381 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
382 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
383 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
384 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
385 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
386 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
387 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
388 (reg_table, prefix_table, three_byte_table, vex_table,
389 vex_len_table, mod_table, rm_table): Replace / remove respective
391 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
392 of PREFIX_DATA in used_prefixes.
394 2020-07-14 Jan Beulich <jbeulich@suse.com>
396 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
397 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
398 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
399 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
400 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
401 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
402 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
403 VEX_W_0F3A33_L_0): Delete.
404 (dis386): Adjust "BW" description.
405 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
406 0F3A31, 0F3A32, and 0F3A33.
407 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
409 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
412 2020-07-14 Jan Beulich <jbeulich@suse.com>
414 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
415 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
416 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
417 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
418 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
419 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
420 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
421 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
422 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
423 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
424 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
425 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
426 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
427 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
428 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
429 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
430 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
431 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
432 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
433 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
434 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
435 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
436 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
437 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
438 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
439 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
440 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
441 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
442 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
443 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
444 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
445 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
446 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
447 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
448 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
449 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
450 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
451 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
452 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
453 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
454 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
455 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
456 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
457 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
458 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
459 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
460 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
461 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
462 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
463 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
464 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
465 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
466 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
467 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
468 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
469 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
470 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
471 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
472 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
473 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
474 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
475 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
476 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
477 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
478 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
479 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
480 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
481 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
482 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
483 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
484 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
485 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
486 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
487 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
488 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
489 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
490 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
491 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
492 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
493 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
494 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
495 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
496 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
497 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
498 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
499 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
500 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
501 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
502 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
503 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
504 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
505 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
506 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
507 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
508 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
509 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
510 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
511 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
512 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
513 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
514 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
515 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
516 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
517 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
518 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
519 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
520 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
521 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
522 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
523 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
524 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
525 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
526 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
527 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
528 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
529 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
530 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
531 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
532 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
533 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
534 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
535 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
536 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
537 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
538 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
539 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
540 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
541 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
542 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
543 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
544 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
545 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
546 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
547 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
548 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
549 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
550 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
551 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
552 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
553 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
554 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
555 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
556 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
557 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
558 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
559 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
560 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
561 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
562 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
563 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
564 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
565 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
566 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
567 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
568 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
569 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
570 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
571 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
572 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
573 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
574 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
575 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
576 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
577 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
578 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
579 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
580 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
581 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
582 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
583 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
584 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
585 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
586 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
587 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
588 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
589 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
590 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
591 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
592 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
593 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
594 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
595 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
596 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
597 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
598 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
599 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
600 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
601 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
602 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
603 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
604 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
605 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
606 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
607 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
608 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
609 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
610 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
611 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
612 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
613 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
614 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
615 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
616 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
617 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
618 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
619 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
620 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
621 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
622 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
623 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
624 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
625 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
626 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
627 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
628 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
629 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
630 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
631 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
632 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
633 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
634 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
635 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
636 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
637 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
638 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
639 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
640 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
641 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
642 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
643 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
644 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
645 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
646 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
647 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
648 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
649 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
650 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
651 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
652 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
653 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
654 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
655 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
656 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
657 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
658 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
659 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
660 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
661 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
662 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
663 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
664 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
665 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
666 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
667 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
668 EVEX_W_0F3A72_P_2): Rename to ...
669 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
670 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
671 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
672 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
673 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
674 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
675 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
676 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
677 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
678 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
679 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
680 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
681 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
682 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
683 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
684 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
685 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
686 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
687 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
688 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
689 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
690 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
691 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
692 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
693 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
694 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
695 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
696 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
697 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
698 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
699 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
700 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
701 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
702 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
703 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
704 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
705 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
706 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
707 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
708 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
709 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
710 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
711 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
712 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
713 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
714 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
715 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
716 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
717 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
718 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
719 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
720 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
721 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
722 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
723 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
724 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
725 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
726 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
727 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
728 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
729 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
730 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
731 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
732 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
733 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
734 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
735 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
736 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
737 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
738 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
739 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
740 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
742 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
743 vex_w_table, mod_table): Replace / remove respective entries.
744 (print_insn): Move up dp->prefix_requirement handling. Handle
746 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
747 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
748 Replace / remove respective entries.
750 2020-07-14 Jan Beulich <jbeulich@suse.com>
752 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
753 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
754 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
755 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
756 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
758 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
759 0F2C, 0F2D, 0F2E, and 0F2F.
760 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
763 2020-07-14 Jan Beulich <jbeulich@suse.com>
765 * i386-dis.c (OP_VexR, VexScalarR): New.
766 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
767 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
768 need_vex_reg): Delete.
769 (prefix_table): Replace VexScalar by VexScalarR and
770 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
771 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
772 (vex_len_table): Replace EXqVexScalarS by EXqS.
773 (get_valid_dis386): Don't set need_vex_reg.
774 (print_insn): Don't initialize need_vex_reg.
775 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
776 q_scalar_swap_mode cases.
777 (OP_EX): Don't check for d_scalar_swap_mode and
779 (OP_VEX): Done check need_vex_reg.
780 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
781 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
782 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
784 2020-07-14 Jan Beulich <jbeulich@suse.com>
786 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
787 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
788 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
789 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
790 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
791 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
792 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
793 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
794 (vex_table): Replace Vex128 by Vex.
795 (vex_len_table): Likewise. Adjust referenced enum names.
796 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
797 referenced enum names.
798 (OP_VEX): Drop vex128_mode and vex256_mode cases.
799 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
801 2020-07-14 Jan Beulich <jbeulich@suse.com>
803 * i386-dis.c (dis386): "LW" description now applies to "DQ".
804 (putop): Handle "DQ". Don't handle "LW" anymore.
805 (prefix_table, mod_table): Replace %LW by %DQ.
806 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
808 2020-07-14 Jan Beulich <jbeulich@suse.com>
810 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
811 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
812 d_scalar_swap_mode case handling. Move shift adjsutment into
813 the case its applicable to.
815 2020-07-14 Jan Beulich <jbeulich@suse.com>
817 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
818 (EXbScalar, EXwScalar): Fold to ...
819 (EXbwUnit): ... this.
820 (b_scalar_mode, w_scalar_mode): Fold to ...
821 (bw_unit_mode): ... this.
822 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
823 w_scalar_mode handling by bw_unit_mode one.
824 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
826 * i386-dis-evex-prefix.h: ... here.
828 2020-07-14 Jan Beulich <jbeulich@suse.com>
830 * i386-dis.c (PCMPESTR_Fixup): Delete.
831 (dis386): Adjust "LQ" description.
832 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
833 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
834 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
835 vpcmpestrm, and vpcmpestri.
836 (putop): Honor "cond" when handling LQ.
837 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
838 vcvtsi2ss and vcvtusi2ss.
839 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
840 vcvtsi2sd and vcvtusi2sd.
842 2020-07-14 Jan Beulich <jbeulich@suse.com>
844 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
845 (simd_cmp_op): Add const.
846 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
847 (CMP_Fixup): Handle VEX case.
848 (prefix_table): Replace VCMP by CMP.
849 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
851 2020-07-14 Jan Beulich <jbeulich@suse.com>
853 * i386-dis.c (MOVBE_Fixup): Delete.
855 (prefix_table): Use Mv for movbe entries.
857 2020-07-14 Jan Beulich <jbeulich@suse.com>
859 * i386-dis.c (CRC32_Fixup): Delete.
860 (prefix_table): Use Eb/Ev for crc32 entries.
862 2020-07-14 Jan Beulich <jbeulich@suse.com>
864 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
865 Conditionalize invocations of "USED_REX (0)".
867 2020-07-14 Jan Beulich <jbeulich@suse.com>
869 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
870 CH, DH, BH, AX, DX): Delete.
871 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
872 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
873 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
875 2020-07-10 Lili Cui <lili.cui@intel.com>
877 * i386-dis.c (TMM): New.
880 (MVexSIBMEM): Likewise.
881 (tmm_mode): Likewise.
882 (vex_sibmem_mode): Likewise.
883 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
884 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
885 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
886 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
887 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
888 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
889 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
890 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
891 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
892 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
893 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
894 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
895 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
896 (PREFIX_VEX_0F3849_X86_64): Likewise.
897 (PREFIX_VEX_0F384B_X86_64): Likewise.
898 (PREFIX_VEX_0F385C_X86_64): Likewise.
899 (PREFIX_VEX_0F385E_X86_64): Likewise.
900 (X86_64_VEX_0F3849): Likewise.
901 (X86_64_VEX_0F384B): Likewise.
902 (X86_64_VEX_0F385C): Likewise.
903 (X86_64_VEX_0F385E): Likewise.
904 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
905 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
906 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
907 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
908 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
909 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
910 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
911 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
912 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
913 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
914 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
915 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
916 (VEX_W_0F3849_X86_64_P_0): Likewise.
917 (VEX_W_0F3849_X86_64_P_2): Likewise.
918 (VEX_W_0F3849_X86_64_P_3): Likewise.
919 (VEX_W_0F384B_X86_64_P_1): Likewise.
920 (VEX_W_0F384B_X86_64_P_2): Likewise.
921 (VEX_W_0F384B_X86_64_P_3): Likewise.
922 (VEX_W_0F385C_X86_64_P_1): Likewise.
923 (VEX_W_0F385E_X86_64_P_0): Likewise.
924 (VEX_W_0F385E_X86_64_P_1): Likewise.
925 (VEX_W_0F385E_X86_64_P_2): Likewise.
926 (VEX_W_0F385E_X86_64_P_3): Likewise.
927 (names_tmm): Likewise.
928 (att_names_tmm): Likewise.
929 (intel_operand_size): Handle void_mode.
930 (OP_XMM): Handle tmm_mode.
933 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
934 CpuAMX_BF16 and CpuAMX_TILE.
935 (operand_type_shorthands): Add RegTMM.
936 (operand_type_init): Likewise.
937 (operand_types): Add Tmmword.
938 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
939 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
940 * i386-opc.h (CpuAMX_INT8): New.
941 (CpuAMX_BF16): Likewise.
942 (CpuAMX_TILE): Likewise.
945 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
946 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
947 (i386_operand_type): Add tmmword.
948 * i386-opc.tbl: Add AMX instructions.
949 * i386-reg.tbl: Add AMX registers.
950 * i386-init.h: Regenerated.
951 * i386-tbl.h: Likewise.
953 2020-07-08 Jan Beulich <jbeulich@suse.com>
955 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
956 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
958 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
959 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
961 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
962 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
963 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
964 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
965 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
966 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
967 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
968 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
969 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
970 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
971 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
972 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
973 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
974 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
975 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
976 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
977 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
978 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
979 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
980 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
981 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
982 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
983 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
984 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
985 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
986 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
987 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
988 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
989 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
990 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
991 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
992 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
993 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
994 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
995 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
996 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
997 (reg_table): Re-order XOP entries. Adjust their operands.
998 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
999 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1000 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1001 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1002 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1003 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1004 entries by references ...
1005 (vex_len_table): ... to resepctive new entries here. For several
1006 new and existing entries reference ...
1007 (vex_w_table): ... new entries here.
1008 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1010 2020-07-08 Jan Beulich <jbeulich@suse.com>
1012 * i386-dis.c (XMVexScalarI4): Define.
1013 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1014 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1015 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1016 (vex_len_table): Move scalar FMA4 entries ...
1017 (prefix_table): ... here.
1018 (OP_REG_VexI4): Handle scalar_mode.
1019 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1020 * i386-tbl.h: Re-generate.
1022 2020-07-08 Jan Beulich <jbeulich@suse.com>
1024 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1025 Vex_2src_2): Delete.
1026 (OP_VexW, VexW): New.
1027 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1028 for shifts and rotates by register.
1030 2020-07-08 Jan Beulich <jbeulich@suse.com>
1032 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1033 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1034 OP_EX_VexReg): Delete.
1035 (OP_VexI4, VexI4): New.
1036 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1037 (prefix_table): ... here.
1038 (print_insn): Drop setting of vex_w_done.
1040 2020-07-08 Jan Beulich <jbeulich@suse.com>
1042 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1043 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1044 (xop_table): Replace operands of 4-operand insns.
1045 (OP_REG_VexI4): Move VEX.W based operand swaping here.
1047 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
1049 * arc-opc.c (insert_rbd): New function.
1052 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1055 2020-07-07 Jan Beulich <jbeulich@suse.com>
1057 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1058 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1059 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1060 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1062 (putop): Handle "BW".
1063 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1064 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1066 * i386-dis-evex-prefix.h: ... here.
1068 2020-07-06 Jan Beulich <jbeulich@suse.com>
1070 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1071 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1072 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1073 VEX_W_0FXOP_09_83): New enumerators.
1074 (xop_table): Reference the above.
1075 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1076 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1077 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1078 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1080 2020-07-06 Jan Beulich <jbeulich@suse.com>
1082 * i386-dis.c (EVEX_W_0F3838_P_1,
1083 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1084 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1085 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1086 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1087 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1088 (putop): Centralize management of last[]. Delete SAVE_LAST.
1089 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1090 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1091 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1092 * i386-dis-evex-prefix.h: here.
1094 2020-07-06 Jan Beulich <jbeulich@suse.com>
1096 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1097 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1098 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1099 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1101 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1102 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1103 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1104 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1105 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1106 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1107 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1108 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1109 these, respectively.
1110 * i386-dis-evex-len.h: Adjust comments.
1111 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1112 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1113 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1114 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1115 MOD_EVEX_0F385B_P_2_W_1 table entries.
1116 * i386-dis-evex-w.h: Reference mod_table[] for
1117 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1120 2020-07-06 Jan Beulich <jbeulich@suse.com>
1122 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1123 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1125 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1126 Likewise. Mark 256-bit entries invalid.
1128 2020-07-06 Jan Beulich <jbeulich@suse.com>
1130 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1131 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1132 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1133 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1134 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1135 PREFIX_EVEX_0F382B): Delete.
1136 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1137 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1138 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1139 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1140 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1142 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1143 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1144 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1145 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1147 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1148 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1149 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1150 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1151 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1152 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1153 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1154 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1155 PREFIX_EVEX_0F382B): Remove table entries.
1156 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1157 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1158 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1160 2020-07-06 Jan Beulich <jbeulich@suse.com>
1162 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1163 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1165 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1166 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1167 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1168 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1171 2020-07-06 Jan Beulich <jbeulich@suse.com>
1173 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1174 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1175 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1176 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1177 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1178 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1179 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1180 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1181 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1184 2020-07-06 Jan Beulich <jbeulich@suse.com>
1186 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1187 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1188 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1190 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1192 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1194 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1196 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1198 2020-07-06 Jan Beulich <jbeulich@suse.com>
1200 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1201 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1202 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1203 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1204 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1205 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1206 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1207 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1208 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1209 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1210 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1211 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1212 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1213 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1214 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1215 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1216 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1217 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1218 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1219 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1220 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1221 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1222 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1223 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1224 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1225 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1226 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1227 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1228 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1229 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1230 (prefix_table): Add EXxEVexR to FMA table entries.
1231 (OP_Rounding): Move abort() invocation.
1232 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1233 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1234 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1235 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1236 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1237 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1238 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1239 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1240 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1241 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1243 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1244 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1245 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1246 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1247 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1248 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1249 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1250 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1251 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1252 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1253 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1254 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1255 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1256 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1257 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1258 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1259 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1260 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1261 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1262 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1263 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1264 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1265 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1266 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1267 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1268 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1269 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1270 Delete table entries.
1271 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1272 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1273 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1276 2020-07-06 Jan Beulich <jbeulich@suse.com>
1278 * i386-dis.c (EXqScalarS): Delete.
1279 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1280 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1282 2020-07-06 Jan Beulich <jbeulich@suse.com>
1284 * i386-dis.c (safe-ctype.h): Include.
1285 (EXdScalar, EXqScalar): Delete.
1286 (d_scalar_mode, q_scalar_mode): Delete.
1287 (prefix_table, vex_len_table): Use EXxmm_md in place of
1288 EXdScalar and EXxmm_mq in place of EXqScalar.
1289 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1290 d_scalar_mode and q_scalar_mode.
1291 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1292 (vmovsd): Use EXxmm_mq.
1294 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1297 * arc-dis.c: Fix spelling mistake.
1298 * po/opcodes.pot: Regenerate.
1300 2020-07-06 Nick Clifton <nickc@redhat.com>
1302 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1303 * po/uk.po: Updated Ukranian translation.
1305 2020-07-04 Nick Clifton <nickc@redhat.com>
1307 * configure: Regenerate.
1308 * po/opcodes.pot: Regenerate.
1310 2020-07-04 Nick Clifton <nickc@redhat.com>
1312 Binutils 2.35 branch created.
1314 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1316 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1317 * i386-opc.h (VexSwapSources): New.
1318 (i386_opcode_modifier): Add vexswapsources.
1319 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1320 with two source operands swapped.
1321 * i386-tbl.h: Regenerated.
1323 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1325 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1326 unprivileged CSR can also be initialized.
1328 2020-06-29 Alan Modra <amodra@gmail.com>
1330 * arm-dis.c: Use C style comments.
1331 * cr16-opc.c: Likewise.
1332 * ft32-dis.c: Likewise.
1333 * moxie-opc.c: Likewise.
1334 * tic54x-dis.c: Likewise.
1335 * s12z-opc.c: Remove useless comment.
1336 * xgate-dis.c: Likewise.
1338 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1340 * i386-opc.tbl: Add a blank line.
1342 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1344 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1345 (VecSIB128): Renamed to ...
1347 (VecSIB256): Renamed to ...
1349 (VecSIB512): Renamed to ...
1351 (VecSIB): Renamed to ...
1353 (i386_opcode_modifier): Replace vecsib with sib.
1354 * i386-opc.tbl (VecSIB128): New.
1355 (VecSIB256): Likewise.
1356 (VecSIB512): Likewise.
1357 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1358 and VecSIB512, respectively.
1360 2020-06-26 Jan Beulich <jbeulich@suse.com>
1362 * i386-dis.c: Adjust description of I macro.
1363 (x86_64_table): Drop use of I.
1364 (float_mem): Replace use of I.
1365 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1367 2020-06-26 Jan Beulich <jbeulich@suse.com>
1369 * i386-dis.c: (print_insn): Avoid straight assignment to
1370 priv.orig_sizeflag when processing -M sub-options.
1372 2020-06-25 Jan Beulich <jbeulich@suse.com>
1374 * i386-dis.c: Adjust description of J macro.
1375 (dis386, x86_64_table, mod_table): Replace J.
1376 (putop): Remove handling of J.
1378 2020-06-25 Jan Beulich <jbeulich@suse.com>
1380 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1382 2020-06-25 Jan Beulich <jbeulich@suse.com>
1384 * i386-dis.c: Adjust description of "LQ" macro.
1385 (dis386_twobyte): Use LQ for sysret.
1386 (putop): Adjust handling of LQ.
1388 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1390 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1391 * riscv-dis.c: Include elfxx-riscv.h.
1393 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1395 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1397 2020-06-17 Lili Cui <lili.cui@intel.com>
1399 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1401 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1404 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1405 * i386-opc.tbl: Likewise.
1406 * i386-tbl.h: Regenerated.
1408 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1410 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1412 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1414 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1415 (SR_CORE): Likewise.
1416 (SR_FEAT): Likewise.
1418 (SR_V8_1): Likewise.
1419 (SR_V8_2): Likewise.
1420 (SR_V8_3): Likewise.
1421 (SR_V8_4): Likewise.
1424 (SR_SSBS): Likewise.
1426 (SR_ID_PFR2): Likewise.
1427 (SR_PROFILE): Likewise.
1428 (SR_MEMTAG): Likewise.
1429 (SR_SCXTNUM): Likewise.
1430 (aarch64_sys_regs): Refactor to store feature information in the table.
1431 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1432 that now describe their own features.
1433 (aarch64_pstatefield_supported_p): Likewise.
1435 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1437 * i386-dis.c (prefix_table): Fix a typo in comments.
1439 2020-06-09 Jan Beulich <jbeulich@suse.com>
1441 * i386-dis.c (rex_ignored): Delete.
1442 (ckprefix): Drop rex_ignored initialization.
1443 (get_valid_dis386): Drop setting of rex_ignored.
1444 (print_insn): Drop checking of rex_ignored. Don't record data
1445 size prefix as used with VEX-and-alike encodings.
1447 2020-06-09 Jan Beulich <jbeulich@suse.com>
1449 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1450 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1451 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1452 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1453 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1454 VEX_0F12, and VEX_0F16.
1455 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1456 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1457 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1458 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1459 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1460 MOD_VEX_0F16_PREFIX_2 entries.
1462 2020-06-09 Jan Beulich <jbeulich@suse.com>
1464 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1465 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1466 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1467 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1468 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1469 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1470 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1471 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1472 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1473 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1474 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1475 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1476 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1477 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1478 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1479 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1480 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1481 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1482 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1483 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1484 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1485 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1486 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1487 EVEX_W_0FC6_P_2): Delete.
1488 (print_insn): Add EVEX.W vs embedded prefix consistency check
1489 to prefix validation.
1490 * i386-dis-evex.h (evex_table): Don't further descend for
1491 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1492 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1494 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1495 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1496 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1497 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1498 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1499 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1500 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1501 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1502 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1503 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1504 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1505 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1506 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1507 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1508 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1509 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1510 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1511 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1512 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1513 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1514 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1515 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1516 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1517 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1518 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1519 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1520 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1522 2020-06-09 Jan Beulich <jbeulich@suse.com>
1524 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1525 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1526 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1528 (print_insn): Drop pointless check against bad_opcode. Split
1529 prefix validation into legacy and VEX-and-alike parts.
1530 (putop): Re-work 'X' macro handling.
1532 2020-06-09 Jan Beulich <jbeulich@suse.com>
1534 * i386-dis.c (MOD_0F51): Rename to ...
1535 (MOD_0F50): ... this.
1537 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1539 * arm-dis.c (arm_opcodes): Add dfb.
1540 (thumb32_opcodes): Add dfb.
1542 2020-06-08 Jan Beulich <jbeulich@suse.com>
1544 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1546 2020-06-06 Alan Modra <amodra@gmail.com>
1548 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1550 2020-06-05 Alan Modra <amodra@gmail.com>
1552 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1553 size is large enough.
1555 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1557 * disassemble.c (disassemble_init_for_target): Set endian_code for
1559 * bpf-desc.c: Regenerate.
1560 * bpf-opc.c: Likewise.
1561 * bpf-dis.c: Likewise.
1563 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1565 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1566 (cgen_put_insn_value): Likewise.
1567 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1568 * cgen-dis.in (print_insn): Likewise.
1569 * cgen-ibld.in (insert_1): Likewise.
1570 (insert_1): Likewise.
1571 (insert_insn_normal): Likewise.
1572 (extract_1): Likewise.
1573 * bpf-dis.c: Regenerate.
1574 * bpf-ibld.c: Likewise.
1575 * bpf-ibld.c: Likewise.
1576 * cgen-dis.in: Likewise.
1577 * cgen-ibld.in: Likewise.
1578 * cgen-opc.c: Likewise.
1579 * epiphany-dis.c: Likewise.
1580 * epiphany-ibld.c: Likewise.
1581 * fr30-dis.c: Likewise.
1582 * fr30-ibld.c: Likewise.
1583 * frv-dis.c: Likewise.
1584 * frv-ibld.c: Likewise.
1585 * ip2k-dis.c: Likewise.
1586 * ip2k-ibld.c: Likewise.
1587 * iq2000-dis.c: Likewise.
1588 * iq2000-ibld.c: Likewise.
1589 * lm32-dis.c: Likewise.
1590 * lm32-ibld.c: Likewise.
1591 * m32c-dis.c: Likewise.
1592 * m32c-ibld.c: Likewise.
1593 * m32r-dis.c: Likewise.
1594 * m32r-ibld.c: Likewise.
1595 * mep-dis.c: Likewise.
1596 * mep-ibld.c: Likewise.
1597 * mt-dis.c: Likewise.
1598 * mt-ibld.c: Likewise.
1599 * or1k-dis.c: Likewise.
1600 * or1k-ibld.c: Likewise.
1601 * xc16x-dis.c: Likewise.
1602 * xc16x-ibld.c: Likewise.
1603 * xstormy16-dis.c: Likewise.
1604 * xstormy16-ibld.c: Likewise.
1606 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1608 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1609 (print_insn_): Handle instruction endian.
1610 * bpf-dis.c: Regenerate.
1611 * bpf-desc.c: Regenerate.
1612 * epiphany-dis.c: Likewise.
1613 * epiphany-desc.c: Likewise.
1614 * fr30-dis.c: Likewise.
1615 * fr30-desc.c: Likewise.
1616 * frv-dis.c: Likewise.
1617 * frv-desc.c: Likewise.
1618 * ip2k-dis.c: Likewise.
1619 * ip2k-desc.c: Likewise.
1620 * iq2000-dis.c: Likewise.
1621 * iq2000-desc.c: Likewise.
1622 * lm32-dis.c: Likewise.
1623 * lm32-desc.c: Likewise.
1624 * m32c-dis.c: Likewise.
1625 * m32c-desc.c: Likewise.
1626 * m32r-dis.c: Likewise.
1627 * m32r-desc.c: Likewise.
1628 * mep-dis.c: Likewise.
1629 * mep-desc.c: Likewise.
1630 * mt-dis.c: Likewise.
1631 * mt-desc.c: Likewise.
1632 * or1k-dis.c: Likewise.
1633 * or1k-desc.c: Likewise.
1634 * xc16x-dis.c: Likewise.
1635 * xc16x-desc.c: Likewise.
1636 * xstormy16-dis.c: Likewise.
1637 * xstormy16-desc.c: Likewise.
1639 2020-06-03 Nick Clifton <nickc@redhat.com>
1641 * po/sr.po: Updated Serbian translation.
1643 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1645 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1646 (riscv_get_priv_spec_class): Likewise.
1648 2020-06-01 Alan Modra <amodra@gmail.com>
1650 * bpf-desc.c: Regenerate.
1652 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1653 David Faust <david.faust@oracle.com>
1655 * bpf-desc.c: Regenerate.
1656 * bpf-opc.h: Likewise.
1657 * bpf-opc.c: Likewise.
1658 * bpf-dis.c: Likewise.
1660 2020-05-28 Alan Modra <amodra@gmail.com>
1662 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1665 2020-05-28 Alan Modra <amodra@gmail.com>
1667 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1669 (print_insn_ns32k): Revert last change.
1671 2020-05-28 Nick Clifton <nickc@redhat.com>
1673 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1676 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1678 Fix extraction of signed constants in nios2 disassembler (again).
1680 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1681 extractions of signed fields.
1683 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1685 * s390-opc.txt: Relocate vector load/store instructions with
1686 additional alignment parameter and change architecture level
1687 constraint from z14 to z13.
1689 2020-05-21 Alan Modra <amodra@gmail.com>
1691 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1692 * sparc-dis.c: Likewise.
1693 * tic4x-dis.c: Likewise.
1694 * xtensa-dis.c: Likewise.
1695 * bpf-desc.c: Regenerate.
1696 * epiphany-desc.c: Regenerate.
1697 * fr30-desc.c: Regenerate.
1698 * frv-desc.c: Regenerate.
1699 * ip2k-desc.c: Regenerate.
1700 * iq2000-desc.c: Regenerate.
1701 * lm32-desc.c: Regenerate.
1702 * m32c-desc.c: Regenerate.
1703 * m32r-desc.c: Regenerate.
1704 * mep-asm.c: Regenerate.
1705 * mep-desc.c: Regenerate.
1706 * mt-desc.c: Regenerate.
1707 * or1k-desc.c: Regenerate.
1708 * xc16x-desc.c: Regenerate.
1709 * xstormy16-desc.c: Regenerate.
1711 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
1713 * riscv-opc.c (riscv_ext_version_table): The table used to store
1714 all information about the supported spec and the corresponding ISA
1715 versions. Currently, only Zicsr is supported to verify the
1716 correctness of Z sub extension settings. Others will be supported
1717 in the future patches.
1718 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1719 classes and the corresponding strings.
1720 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1721 spec class by giving a ISA spec string.
1722 * riscv-opc.c (struct priv_spec_t): New structure.
1723 (struct priv_spec_t priv_specs): List for all supported privilege spec
1724 classes and the corresponding strings.
1725 (riscv_get_priv_spec_class): New function. Get the corresponding
1726 privilege spec class by giving a spec string.
1727 (riscv_get_priv_spec_name): New function. Get the corresponding
1728 privilege spec string by giving a CSR version class.
1729 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1730 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1731 according to the chosen version. Build a hash table riscv_csr_hash to
1732 store the valid CSR for the chosen pirv verison. Dump the direct
1733 CSR address rather than it's name if it is invalid.
1734 (parse_riscv_dis_option_without_args): New function. Parse the options
1736 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1737 parse the options without arguments first, and then handle the options
1738 with arguments. Add the new option -Mpriv-spec, which has argument.
1739 * riscv-dis.c (print_riscv_disassembler_options): Add description
1740 about the new OBJDUMP option.
1742 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
1744 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1745 WC values on POWER10 sync, dcbf and wait instructions.
1746 (insert_pl, extract_pl): New functions.
1747 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1748 (LS3): New , 3-bit L for sync.
1749 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1750 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1751 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1752 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1753 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1754 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1755 <wait>: Enable PL operand on POWER10.
1756 <dcbf>: Enable L3OPT operand on POWER10.
1757 <sync>: Enable SC2 operand on POWER10.
1759 2020-05-19 Stafford Horne <shorne@gmail.com>
1762 * or1k-asm.c: Regenerate.
1763 * or1k-desc.c: Regenerate.
1764 * or1k-desc.h: Regenerate.
1765 * or1k-dis.c: Regenerate.
1766 * or1k-ibld.c: Regenerate.
1767 * or1k-opc.c: Regenerate.
1768 * or1k-opc.h: Regenerate.
1769 * or1k-opinst.c: Regenerate.
1771 2020-05-11 Alan Modra <amodra@gmail.com>
1773 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1776 2020-05-11 Alan Modra <amodra@gmail.com>
1778 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1779 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1781 2020-05-11 Alan Modra <amodra@gmail.com>
1783 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1785 2020-05-11 Alan Modra <amodra@gmail.com>
1787 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1788 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1790 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1792 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1795 2020-05-11 Alan Modra <amodra@gmail.com>
1797 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1798 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1799 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1800 (prefix_opcodes): Add xxeval.
1802 2020-05-11 Alan Modra <amodra@gmail.com>
1804 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1805 xxgenpcvwm, xxgenpcvdm.
1807 2020-05-11 Alan Modra <amodra@gmail.com>
1809 * ppc-opc.c (MP, VXVAM_MASK): Define.
1810 (VXVAPS_MASK): Use VXVA_MASK.
1811 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1812 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1813 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1814 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1816 2020-05-11 Alan Modra <amodra@gmail.com>
1817 Peter Bergner <bergner@linux.ibm.com>
1819 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1821 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1822 YMSK2, XA6a, XA6ap, XB6a entries.
1823 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1824 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1826 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1827 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1828 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1829 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1830 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1831 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1832 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1833 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1834 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1835 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1836 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1837 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1838 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1839 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1841 2020-05-11 Alan Modra <amodra@gmail.com>
1843 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1844 (insert_xts, extract_xts): New functions.
1845 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1846 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1847 (VXRC_MASK, VXSH_MASK): Define.
1848 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1849 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1850 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1851 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1852 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1853 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1854 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1856 2020-05-11 Alan Modra <amodra@gmail.com>
1858 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1859 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1860 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1861 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1862 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1864 2020-05-11 Alan Modra <amodra@gmail.com>
1866 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1867 (XTP, DQXP, DQXP_MASK): Define.
1868 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1869 (prefix_opcodes): Add plxvp and pstxvp.
1871 2020-05-11 Alan Modra <amodra@gmail.com>
1873 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1874 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1875 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1877 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1879 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1881 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1883 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1885 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1887 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1889 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1891 2020-05-11 Alan Modra <amodra@gmail.com>
1893 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1895 2020-05-11 Alan Modra <amodra@gmail.com>
1897 * ppc-dis.c (ppc_opts): Add "power10" entry.
1898 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1899 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1901 2020-05-11 Nick Clifton <nickc@redhat.com>
1903 * po/fr.po: Updated French translation.
1905 2020-04-30 Alex Coplan <alex.coplan@arm.com>
1907 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1908 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1909 (operand_general_constraint_met_p): validate
1910 AARCH64_OPND_UNDEFINED.
1911 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1913 * aarch64-asm-2.c: Regenerated.
1914 * aarch64-dis-2.c: Regenerated.
1915 * aarch64-opc-2.c: Regenerated.
1917 2020-04-29 Nick Clifton <nickc@redhat.com>
1920 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1923 2020-04-29 Nick Clifton <nickc@redhat.com>
1925 * po/sv.po: Updated Swedish translation.
1927 2020-04-29 Nick Clifton <nickc@redhat.com>
1930 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1931 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1932 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1935 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1938 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1939 cmpi only on m68020up and cpu32.
1941 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1943 * aarch64-asm.c (aarch64_ins_none): New.
1944 * aarch64-asm.h (ins_none): New declaration.
1945 * aarch64-dis.c (aarch64_ext_none): New.
1946 * aarch64-dis.h (ext_none): New declaration.
1947 * aarch64-opc.c (aarch64_print_operand): Update case for
1948 AARCH64_OPND_BARRIER_PSB.
1949 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1950 (AARCH64_OPERANDS): Update inserter/extracter for
1951 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1952 * aarch64-asm-2.c: Regenerated.
1953 * aarch64-dis-2.c: Regenerated.
1954 * aarch64-opc-2.c: Regenerated.
1956 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1958 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1959 (aarch64_feature_ras, RAS): Likewise.
1960 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1961 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1962 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1963 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1964 * aarch64-asm-2.c: Regenerated.
1965 * aarch64-dis-2.c: Regenerated.
1966 * aarch64-opc-2.c: Regenerated.
1968 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
1970 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1971 (print_insn_neon): Support disassembly of conditional
1974 2020-02-16 David Faust <david.faust@oracle.com>
1976 * bpf-desc.c: Regenerate.
1977 * bpf-desc.h: Likewise.
1978 * bpf-opc.c: Regenerate.
1979 * bpf-opc.h: Likewise.
1981 2020-04-07 Lili Cui <lili.cui@intel.com>
1983 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1984 (prefix_table): New instructions (see prefixes above).
1985 (rm_table): Likewise
1986 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1987 CPU_ANY_TSXLDTRK_FLAGS.
1988 (cpu_flags): Add CpuTSXLDTRK.
1989 * i386-opc.h (enum): Add CpuTSXLDTRK.
1990 (i386_cpu_flags): Add cputsxldtrk.
1991 * i386-opc.tbl: Add XSUSPLDTRK insns.
1992 * i386-init.h: Regenerate.
1993 * i386-tbl.h: Likewise.
1995 2020-04-02 Lili Cui <lili.cui@intel.com>
1997 * i386-dis.c (prefix_table): New instructions serialize.
1998 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1999 CPU_ANY_SERIALIZE_FLAGS.
2000 (cpu_flags): Add CpuSERIALIZE.
2001 * i386-opc.h (enum): Add CpuSERIALIZE.
2002 (i386_cpu_flags): Add cpuserialize.
2003 * i386-opc.tbl: Add SERIALIZE insns.
2004 * i386-init.h: Regenerate.
2005 * i386-tbl.h: Likewise.
2007 2020-03-26 Alan Modra <amodra@gmail.com>
2009 * disassemble.h (opcodes_assert): Declare.
2010 (OPCODES_ASSERT): Define.
2011 * disassemble.c: Don't include assert.h. Include opintl.h.
2012 (opcodes_assert): New function.
2013 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2014 (bfd_h8_disassemble): Reduce size of data array. Correctly
2015 calculate maxlen. Omit insn decoding when insn length exceeds
2016 maxlen. Exit from nibble loop when looking for E, before
2017 accessing next data byte. Move processing of E outside loop.
2018 Replace tests of maxlen in loop with assertions.
2020 2020-03-26 Alan Modra <amodra@gmail.com>
2022 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
2024 2020-03-25 Alan Modra <amodra@gmail.com>
2026 * z80-dis.c (suffix): Init mybuf.
2028 2020-03-22 Alan Modra <amodra@gmail.com>
2030 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2031 successflly read from section.
2033 2020-03-22 Alan Modra <amodra@gmail.com>
2035 * arc-dis.c (find_format): Use ISO C string concatenation rather
2036 than line continuation within a string. Don't access needs_limm
2037 before testing opcode != NULL.
2039 2020-03-22 Alan Modra <amodra@gmail.com>
2041 * ns32k-dis.c (print_insn_arg): Update comment.
2042 (print_insn_ns32k): Reduce size of index_offset array, and
2043 initialize, passing -1 to print_insn_arg for args that are not
2044 an index. Don't exit arg loop early. Abort on bad arg number.
2046 2020-03-22 Alan Modra <amodra@gmail.com>
2048 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2049 * s12z-opc.c: Formatting.
2050 (operands_f): Return an int.
2051 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2052 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2053 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2054 (exg_sex_discrim): Likewise.
2055 (create_immediate_operand, create_bitfield_operand),
2056 (create_register_operand_with_size, create_register_all_operand),
2057 (create_register_all16_operand, create_simple_memory_operand),
2058 (create_memory_operand, create_memory_auto_operand): Don't
2059 segfault on malloc failure.
2060 (z_ext24_decode): Return an int status, negative on fail, zero
2062 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2063 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2064 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2065 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2066 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2067 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2068 (loop_primitive_decode, shift_decode, psh_pul_decode),
2069 (bit_field_decode): Similarly.
2070 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
2071 to return value, update callers.
2072 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2073 Don't segfault on NULL operand.
2074 (decode_operation): Return OP_INVALID on first fail.
2075 (decode_s12z): Check all reads, returning -1 on fail.
2077 2020-03-20 Alan Modra <amodra@gmail.com>
2079 * metag-dis.c (print_insn_metag): Don't ignore status from
2082 2020-03-20 Alan Modra <amodra@gmail.com>
2084 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2085 Initialize parts of buffer not written when handling a possible
2086 2-byte insn at end of section. Don't attempt decoding of such
2087 an insn by the 4-byte machinery.
2089 2020-03-20 Alan Modra <amodra@gmail.com>
2091 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2092 partially filled buffer. Prevent lookup of 4-byte insns when
2093 only VLE 2-byte insns are possible due to section size. Print
2094 ".word" rather than ".long" for 2-byte leftovers.
2096 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2099 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2101 2020-03-13 Jan Beulich <jbeulich@suse.com>
2103 * i386-dis.c (X86_64_0D): Rename to ...
2104 (X86_64_0E): ... this.
2106 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2108 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2109 * Makefile.in: Regenerated.
2111 2020-03-09 Jan Beulich <jbeulich@suse.com>
2113 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2115 * i386-tbl.h: Re-generate.
2117 2020-03-09 Jan Beulich <jbeulich@suse.com>
2119 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2120 vprot*, vpsha*, and vpshl*.
2121 * i386-tbl.h: Re-generate.
2123 2020-03-09 Jan Beulich <jbeulich@suse.com>
2125 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2126 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2127 * i386-tbl.h: Re-generate.
2129 2020-03-09 Jan Beulich <jbeulich@suse.com>
2131 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2132 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2133 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2134 * i386-tbl.h: Re-generate.
2136 2020-03-09 Jan Beulich <jbeulich@suse.com>
2138 * i386-gen.c (struct template_arg, struct template_instance,
2139 struct template_param, struct template, templates,
2140 parse_template, expand_templates): New.
2141 (process_i386_opcodes): Various local variables moved to
2142 expand_templates. Call parse_template and expand_templates.
2143 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2144 * i386-tbl.h: Re-generate.
2146 2020-03-06 Jan Beulich <jbeulich@suse.com>
2148 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2149 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2150 register and memory source templates. Replace VexW= by VexW*
2152 * i386-tbl.h: Re-generate.
2154 2020-03-06 Jan Beulich <jbeulich@suse.com>
2156 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2157 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2158 * i386-tbl.h: Re-generate.
2160 2020-03-06 Jan Beulich <jbeulich@suse.com>
2162 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2163 * i386-tbl.h: Re-generate.
2165 2020-03-06 Jan Beulich <jbeulich@suse.com>
2167 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2168 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2169 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2170 VexW0 on SSE2AVX variants.
2171 (vmovq): Drop NoRex64 from XMM/XMM variants.
2172 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2173 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2174 applicable use VexW0.
2175 * i386-tbl.h: Re-generate.
2177 2020-03-06 Jan Beulich <jbeulich@suse.com>
2179 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2180 * i386-opc.h (Rex64): Delete.
2181 (struct i386_opcode_modifier): Remove rex64 field.
2182 * i386-opc.tbl (crc32): Drop Rex64.
2183 Replace Rex64 with Size64 everywhere else.
2184 * i386-tbl.h: Re-generate.
2186 2020-03-06 Jan Beulich <jbeulich@suse.com>
2188 * i386-dis.c (OP_E_memory): Exclude recording of used address
2189 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2190 addressed memory operands for MPX insns.
2192 2020-03-06 Jan Beulich <jbeulich@suse.com>
2194 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2195 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2196 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2197 (ptwrite): Split into non-64-bit and 64-bit forms.
2198 * i386-tbl.h: Re-generate.
2200 2020-03-06 Jan Beulich <jbeulich@suse.com>
2202 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2204 * i386-tbl.h: Re-generate.
2206 2020-03-04 Jan Beulich <jbeulich@suse.com>
2208 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2209 (prefix_table): Move vmmcall here. Add vmgexit.
2210 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2211 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2212 (cpu_flags): Add CpuSEV_ES entry.
2213 * i386-opc.h (CpuSEV_ES): New.
2214 (union i386_cpu_flags): Add cpusev_es field.
2215 * i386-opc.tbl (vmgexit): New.
2216 * i386-init.h, i386-tbl.h: Re-generate.
2218 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2220 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2222 * i386-opc.h (IGNORESIZE): New.
2223 (DEFAULTSIZE): Likewise.
2224 (IgnoreSize): Removed.
2225 (DefaultSize): Likewise.
2226 (MnemonicSize): New.
2227 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2229 * i386-opc.tbl (IgnoreSize): New.
2230 (DefaultSize): Likewise.
2231 * i386-tbl.h: Regenerated.
2233 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2236 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2239 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2242 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2243 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2244 * i386-tbl.h: Regenerated.
2246 2020-02-26 Alan Modra <amodra@gmail.com>
2248 * aarch64-asm.c: Indent labels correctly.
2249 * aarch64-dis.c: Likewise.
2250 * aarch64-gen.c: Likewise.
2251 * aarch64-opc.c: Likewise.
2252 * alpha-dis.c: Likewise.
2253 * i386-dis.c: Likewise.
2254 * nds32-asm.c: Likewise.
2255 * nfp-dis.c: Likewise.
2256 * visium-dis.c: Likewise.
2258 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2260 * arc-regs.h (int_vector_base): Make it available for all ARC
2263 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2265 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2268 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2270 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2271 c.mv/c.li if rs1 is zero.
2273 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2275 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2276 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2278 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2279 * i386-opc.h (CpuABM): Removed.
2281 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2282 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2283 popcnt. Remove CpuABM from lzcnt.
2284 * i386-init.h: Regenerated.
2285 * i386-tbl.h: Likewise.
2287 2020-02-17 Jan Beulich <jbeulich@suse.com>
2289 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2290 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2291 VexW1 instead of open-coding them.
2292 * i386-tbl.h: Re-generate.
2294 2020-02-17 Jan Beulich <jbeulich@suse.com>
2296 * i386-opc.tbl (AddrPrefixOpReg): Define.
2297 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2298 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2299 templates. Drop NoRex64.
2300 * i386-tbl.h: Re-generate.
2302 2020-02-17 Jan Beulich <jbeulich@suse.com>
2305 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2306 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2307 into Intel syntax instance (with Unpsecified) and AT&T one
2309 (vcvtneps2bf16): Likewise, along with folding the two so far
2311 * i386-tbl.h: Re-generate.
2313 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2315 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2316 CPU_ANY_SSE4A_FLAGS.
2318 2020-02-17 Alan Modra <amodra@gmail.com>
2320 * i386-gen.c (cpu_flag_init): Correct last change.
2322 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2324 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2327 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2329 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2332 2020-02-14 Jan Beulich <jbeulich@suse.com>
2335 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2336 destination for Cpu64-only variant.
2337 (movzx): Fold patterns.
2338 * i386-tbl.h: Re-generate.
2340 2020-02-13 Jan Beulich <jbeulich@suse.com>
2342 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2343 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2344 CPU_ANY_SSE4_FLAGS entry.
2345 * i386-init.h: Re-generate.
2347 2020-02-12 Jan Beulich <jbeulich@suse.com>
2349 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2350 with Unspecified, making the present one AT&T syntax only.
2351 * i386-tbl.h: Re-generate.
2353 2020-02-12 Jan Beulich <jbeulich@suse.com>
2355 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2356 * i386-tbl.h: Re-generate.
2358 2020-02-12 Jan Beulich <jbeulich@suse.com>
2361 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2362 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2363 Amd64 and Intel64 templates.
2364 (call, jmp): Likewise for far indirect variants. Dro
2366 * i386-tbl.h: Re-generate.
2368 2020-02-11 Jan Beulich <jbeulich@suse.com>
2370 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2371 * i386-opc.h (ShortForm): Delete.
2372 (struct i386_opcode_modifier): Remove shortform field.
2373 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2374 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2375 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2376 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2378 * i386-tbl.h: Re-generate.
2380 2020-02-11 Jan Beulich <jbeulich@suse.com>
2382 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2383 fucompi): Drop ShortForm from operand-less templates.
2384 * i386-tbl.h: Re-generate.
2386 2020-02-11 Alan Modra <amodra@gmail.com>
2388 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2389 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2390 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2391 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2392 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2394 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2396 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2397 (cde_opcodes): Add VCX* instructions.
2399 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2400 Matthew Malcomson <matthew.malcomson@arm.com>
2402 * arm-dis.c (struct cdeopcode32): New.
2403 (CDE_OPCODE): New macro.
2404 (cde_opcodes): New disassembly table.
2405 (regnames): New option to table.
2406 (cde_coprocs): New global variable.
2407 (print_insn_cde): New
2408 (print_insn_thumb32): Use print_insn_cde.
2409 (parse_arm_disassembler_options): Parse coprocN args.
2411 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2414 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2416 * i386-opc.h (AMD64): Removed.
2417 (Intel64): Likewose.
2419 (INTEL64): Likewise.
2420 (INTEL64ONLY): Likewise.
2421 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2422 * i386-opc.tbl (Amd64): New.
2423 (Intel64): Likewise.
2424 (Intel64Only): Likewise.
2425 Replace AMD64 with Amd64. Update sysenter/sysenter with
2426 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2427 * i386-tbl.h: Regenerated.
2429 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2432 * z80-dis.c: Add support for GBZ80 opcodes.
2434 2020-02-04 Alan Modra <amodra@gmail.com>
2436 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2438 2020-02-03 Alan Modra <amodra@gmail.com>
2440 * m32c-ibld.c: Regenerate.
2442 2020-02-01 Alan Modra <amodra@gmail.com>
2444 * frv-ibld.c: Regenerate.
2446 2020-01-31 Jan Beulich <jbeulich@suse.com>
2448 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2449 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2450 (OP_E_memory): Replace xmm_mdq_mode case label by
2451 vex_scalar_w_dq_mode one.
2452 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2454 2020-01-31 Jan Beulich <jbeulich@suse.com>
2456 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2457 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2458 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2459 (intel_operand_size): Drop vex_w_dq_mode case label.
2461 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2463 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2464 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2466 2020-01-30 Alan Modra <amodra@gmail.com>
2468 * m32c-ibld.c: Regenerate.
2470 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2472 * bpf-opc.c: Regenerate.
2474 2020-01-30 Jan Beulich <jbeulich@suse.com>
2476 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2477 (dis386): Use them to replace C2/C3 table entries.
2478 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2479 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2480 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2481 * i386-tbl.h: Re-generate.
2483 2020-01-30 Jan Beulich <jbeulich@suse.com>
2485 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2487 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2489 * i386-tbl.h: Re-generate.
2491 2020-01-30 Alan Modra <amodra@gmail.com>
2493 * tic4x-dis.c (tic4x_dp): Make unsigned.
2495 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2496 Jan Beulich <jbeulich@suse.com>
2499 * i386-dis.c (MOVSXD_Fixup): New function.
2500 (movsxd_mode): New enum.
2501 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2502 (intel_operand_size): Handle movsxd_mode.
2503 (OP_E_register): Likewise.
2505 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2506 register on movsxd. Add movsxd with 16-bit destination register
2507 for AMD64 and Intel64 ISAs.
2508 * i386-tbl.h: Regenerated.
2510 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2513 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2514 * aarch64-asm-2.c: Regenerate
2515 * aarch64-dis-2.c: Likewise.
2516 * aarch64-opc-2.c: Likewise.
2518 2020-01-21 Jan Beulich <jbeulich@suse.com>
2520 * i386-opc.tbl (sysret): Drop DefaultSize.
2521 * i386-tbl.h: Re-generate.
2523 2020-01-21 Jan Beulich <jbeulich@suse.com>
2525 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2527 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2528 * i386-tbl.h: Re-generate.
2530 2020-01-20 Nick Clifton <nickc@redhat.com>
2532 * po/de.po: Updated German translation.
2533 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2534 * po/uk.po: Updated Ukranian translation.
2536 2020-01-20 Alan Modra <amodra@gmail.com>
2538 * hppa-dis.c (fput_const): Remove useless cast.
2540 2020-01-20 Alan Modra <amodra@gmail.com>
2542 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2544 2020-01-18 Nick Clifton <nickc@redhat.com>
2546 * configure: Regenerate.
2547 * po/opcodes.pot: Regenerate.
2549 2020-01-18 Nick Clifton <nickc@redhat.com>
2551 Binutils 2.34 branch created.
2553 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2555 * opintl.h: Fix spelling error (seperate).
2557 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2559 * i386-opc.tbl: Add {vex} pseudo prefix.
2560 * i386-tbl.h: Regenerated.
2562 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2565 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2566 (neon_opcodes): Likewise.
2567 (select_arm_features): Make sure we enable MVE bits when selecting
2568 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2571 2020-01-16 Jan Beulich <jbeulich@suse.com>
2573 * i386-opc.tbl: Drop stale comment from XOP section.
2575 2020-01-16 Jan Beulich <jbeulich@suse.com>
2577 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2578 (extractps): Add VexWIG to SSE2AVX forms.
2579 * i386-tbl.h: Re-generate.
2581 2020-01-16 Jan Beulich <jbeulich@suse.com>
2583 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2584 Size64 from and use VexW1 on SSE2AVX forms.
2585 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2586 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2587 * i386-tbl.h: Re-generate.
2589 2020-01-15 Alan Modra <amodra@gmail.com>
2591 * tic4x-dis.c (tic4x_version): Make unsigned long.
2592 (optab, optab_special, registernames): New file scope vars.
2593 (tic4x_print_register): Set up registernames rather than
2594 malloc'd registertable.
2595 (tic4x_disassemble): Delete optable and optable_special. Use
2596 optab and optab_special instead. Throw away old optab,
2597 optab_special and registernames when info->mach changes.
2599 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2602 * z80-dis.c (suffix): Use .db instruction to generate double
2605 2020-01-14 Alan Modra <amodra@gmail.com>
2607 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2608 values to unsigned before shifting.
2610 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2612 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2614 (print_insn_thumb16, print_insn_thumb32): Likewise.
2615 (print_insn): Initialize the insn info.
2616 * i386-dis.c (print_insn): Initialize the insn info fields, and
2619 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2621 * arc-opc.c (C_NE): Make it required.
2623 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2625 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2626 reserved register name.
2628 2020-01-13 Alan Modra <amodra@gmail.com>
2630 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2631 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2633 2020-01-13 Alan Modra <amodra@gmail.com>
2635 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2636 result of wasm_read_leb128 in a uint64_t and check that bits
2637 are not lost when copying to other locals. Use uint32_t for
2638 most locals. Use PRId64 when printing int64_t.
2640 2020-01-13 Alan Modra <amodra@gmail.com>
2642 * score-dis.c: Formatting.
2643 * score7-dis.c: Formatting.
2645 2020-01-13 Alan Modra <amodra@gmail.com>
2647 * score-dis.c (print_insn_score48): Use unsigned variables for
2648 unsigned values. Don't left shift negative values.
2649 (print_insn_score32): Likewise.
2650 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2652 2020-01-13 Alan Modra <amodra@gmail.com>
2654 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2656 2020-01-13 Alan Modra <amodra@gmail.com>
2658 * fr30-ibld.c: Regenerate.
2660 2020-01-13 Alan Modra <amodra@gmail.com>
2662 * xgate-dis.c (print_insn): Don't left shift signed value.
2663 (ripBits): Formatting, use 1u.
2665 2020-01-10 Alan Modra <amodra@gmail.com>
2667 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2668 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2670 2020-01-10 Alan Modra <amodra@gmail.com>
2672 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2673 and XRREG value earlier to avoid a shift with negative exponent.
2674 * m10200-dis.c (disassemble): Similarly.
2676 2020-01-09 Nick Clifton <nickc@redhat.com>
2679 * z80-dis.c (ld_ii_ii): Use correct cast.
2681 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2684 * z80-dis.c (ld_ii_ii): Use character constant when checking
2687 2020-01-09 Jan Beulich <jbeulich@suse.com>
2689 * i386-dis.c (SEP_Fixup): New.
2691 (dis386_twobyte): Use it for sysenter/sysexit.
2692 (enum x86_64_isa): Change amd64 enumerator to value 1.
2693 (OP_J): Compare isa64 against intel64 instead of amd64.
2694 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2696 * i386-tbl.h: Re-generate.
2698 2020-01-08 Alan Modra <amodra@gmail.com>
2700 * z8k-dis.c: Include libiberty.h
2701 (instr_data_s): Make max_fetched unsigned.
2702 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2703 Don't exceed byte_info bounds.
2704 (output_instr): Make num_bytes unsigned.
2705 (unpack_instr): Likewise for nibl_count and loop.
2706 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2708 * z8k-opc.h: Regenerate.
2710 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
2712 * arc-tbl.h (llock): Use 'LLOCK' as class.
2714 (scond): Use 'SCOND' as class.
2716 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2719 2020-01-06 Alan Modra <amodra@gmail.com>
2721 * m32c-ibld.c: Regenerate.
2723 2020-01-06 Alan Modra <amodra@gmail.com>
2726 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2727 Peek at next byte to prevent recursion on repeated prefix bytes.
2728 Ensure uninitialised "mybuf" is not accessed.
2729 (print_insn_z80): Don't zero n_fetch and n_used here,..
2730 (print_insn_z80_buf): ..do it here instead.
2732 2020-01-04 Alan Modra <amodra@gmail.com>
2734 * m32r-ibld.c: Regenerate.
2736 2020-01-04 Alan Modra <amodra@gmail.com>
2738 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2740 2020-01-04 Alan Modra <amodra@gmail.com>
2742 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2744 2020-01-04 Alan Modra <amodra@gmail.com>
2746 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2748 2020-01-03 Jan Beulich <jbeulich@suse.com>
2750 * aarch64-tbl.h (aarch64_opcode_table): Use
2751 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2753 2020-01-03 Jan Beulich <jbeulich@suse.com>
2755 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
2756 forms of SUDOT and USDOT.
2758 2020-01-03 Jan Beulich <jbeulich@suse.com>
2760 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
2762 * opcodes/aarch64-dis-2.c: Re-generate.
2764 2020-01-03 Jan Beulich <jbeulich@suse.com>
2766 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
2768 * opcodes/aarch64-dis-2.c: Re-generate.
2770 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2772 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2774 2020-01-01 Alan Modra <amodra@gmail.com>
2776 Update year range in copyright notice of all files.
2778 For older changes see ChangeLog-2019
2780 Copyright (C) 2020 Free Software Foundation, Inc.
2782 Copying and distribution of this file, with or without modification,
2783 are permitted in any medium without royalty provided the copyright
2784 notice and this notice are preserved.
2790 version-control: never
projects / thirdparty / binutils-gdb.git / blob