opcodes/ChangeLog

   1 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
   2
   3         * mips-dis.c (mips_cp1_names_mips): New variable.
   4         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
   5         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
   6         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
   7         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
   8         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
   9         "loongson2f".
  10
  11 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  12
  13         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
  14         handling code over to...
  15         <OP_REG_CONTROL>: ... this new case.
  16         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
  17         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
  18         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
  19         replacing the `G' operand code with `g'.  Update "cftc1" and
  20         "cftc2" entries replacing the `E' operand code with `y'.
  21         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
  22         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
  23         entries replacing the `G' operand code with `g'.
  24
  25 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  26
  27         * mips-dis.c (mips_cp0_names_r3900): New variable.
  28         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
  29         for "r3900".
  30
  31 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  32
  33         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
  34         and "mtthc2" to using the `G' rather than `g' operand code for
  35         the coprocessor control register referred.
  36
  37 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  38
  39         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
  40         entries with each other.
  41
  42 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
  43
  44         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
  45
  46 2021-05-25  Alan Modra  <amodra@gmail.com>
  47
  48         * cris-desc.c: Regenerate.
  49         * cris-desc.h: Regenerate.
  50         * cris-opc.h: Regenerate.
  51         * po/POTFILES.in: Regenerate.
  52
  53 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
  54
  55         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
  56         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
  57         (CGEN_CPUS): Add cris.
  58         (CRIS_DEPS): Define.
  59         (stamp-cris): New rule.
  60         * cgen.sh: Handle desc action.
  61         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
  62         * Makefile.in, configure: Regenerate.
  63
  64 2021-05-18  Job Noorman  <mtvec@pm.me>
  65
  66         PR 27814
  67         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
  68         the elf objects.
  69
  70 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
  71
  72         * arm-dis.c (mve_opcodes): Fix disassembly of
  73         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
  74         (is_mve_encoding_conflict): MVE vector loads should not match
  75         when P = W = 0.
  76         (is_mve_unpredictable): It's not unpredictable to use the same
  77         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
  78
  79 2021-05-11  Nick Clifton  <nickc@redhat.com>
  80
  81         PR 27840
  82         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
  83         the end of the code buffer.
  84
  85 2021-05-06  Stafford Horne  <shorne@gmail.com>
  86
  87         PR 21464
  88         * or1k-asm.c: Regenerate.
  89
  90 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
  91
  92         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
  93         info->insn_info_valid.
  94
  95 2021-04-26  Jan Beulich  <jbeulich@suse.com>
  96
  97         * i386-opc.tbl (lea): Add Optimize.
  98         * opcodes/i386-tbl.h: Re-generate.
  99
 100 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 101
 102         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 103         of l32r fetch and display referenced literal value.
 104
 105 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 106
 107         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 108         to 4 for literal disassembly.
 109
 110 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 111
 112         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 113         for TLBI instruction.
 114
 115 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 116
 117         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 118         DC instruction.
 119
 120 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 121
 122         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 123         "qualifier".
 124         (convert_mov_to_movewide): Add initializer for "value".
 125
 126 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 127
 128         * aarch64-opc.c: Add RME system registers.
 129
 130 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 131
 132         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 133         "addi d,CV,z" to "c.mv d,CV".
 134
 135 2021-04-12  Alan Modra  <amodra@gmail.com>
 136
 137         * configure.ac (--enable-checking): Add support.
 138         * config.in: Regenerate.
 139         * configure: Regenerate.
 140
 141 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 142
 143         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 144         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 145
 146 2021-04-09  Alan Modra  <amodra@gmail.com>
 147
 148         * ppc-dis.c (struct dis_private): Add "special".
 149         (POWERPC_DIALECT): Delete.  Replace uses with..
 150         (private_data): ..this.  New inline function.
 151         (disassemble_init_powerpc): Init "special" names.
 152         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 153         field of prefix instructions.
 154         (bsearch_reloc, print_got_plt): New functions.
 155         (print_insn_powerpc): For pcrel instructions, print target address
 156         and symbol if known, and decode plt and got loads too.
 157
 158 2021-04-08  Alan Modra  <amodra@gmail.com>
 159
 160         PR 27684
 161         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 162
 163 2021-04-08  Alan Modra  <amodra@gmail.com>
 164
 165         PR 27676
 166         * ppc-opc.c (DCBT_EO): Move earlier.
 167         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 168         (powerpc_operands): Add THCT and THDS entries.
 169         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 170
 171 2021-04-06  Alan Modra  <amodra@gmail.com>
 172
 173         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 174         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 175         symbol_at_address_func.
 176
 177 2021-04-05  Alan Modra  <amodra@gmail.com>
 178
 179         * configure.ac: Don't check for limits.h, string.h, strings.h or
 180         stdlib.h.
 181         (AC_ISC_POSIX): Don't invoke.
 182         * sysdep.h: Include stdlib.h and string.h unconditionally.
 183         * i386-opc.h: Include limits.h unconditionally.
 184         * wasm32-dis.c: Likewise.
 185         * cgen-opc.c: Don't include alloca-conf.h.
 186         * config.in: Regenerate.
 187         * configure: Regenerate.
 188
 189 2021-04-01  Martin Liska  <mliska@suse.cz>
 190
 191         * arm-dis.c (strneq): Remove strneq and use startswith.
 192         * cr16-dis.c (print_insn_cr16): Likewise.
 193         * score-dis.c (streq): Likewise.
 194         (strneq): Likewise.
 195         * score7-dis.c (strneq): Likewise.
 196
 197 2021-04-01  Alan Modra  <amodra@gmail.com>
 198
 199         PR 27675
 200         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 201
 202 2021-03-31  Alan Modra  <amodra@gmail.com>
 203
 204         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 205         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 206         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 207         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 208         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 209         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 210         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 211         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 212         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 213         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 214         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 215         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 216         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 217         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 218         and TRUE with true throughout.
 219
 220 2021-03-31  Alan Modra  <amodra@gmail.com>
 221
 222         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 223         * aarch64-dis.h: Likewise.
 224         * aarch64-opc.c: Likewise.
 225         * avr-dis.c: Likewise.
 226         * csky-dis.c: Likewise.
 227         * nds32-asm.c: Likewise.
 228         * nds32-dis.c: Likewise.
 229         * nfp-dis.c: Likewise.
 230         * riscv-dis.c: Likewise.
 231         * s12z-dis.c: Likewise.
 232         * wasm32-dis.c: Likewise.
 233
 234 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 235
 236         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 237         (i386_seg_prefixes): New.
 238         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 239         (i386_seg_prefixes): Declare.
 240
 241 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 242
 243         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 244
 245 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 246
 247         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 248         * i386-reg.tbl (st): Move down.
 249         (st(0)): Delete. Extend comment.
 250         * i386-tbl.h: Re-generate.
 251
 252 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 253
 254         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 255         (cmpsd): Move next to cmps.
 256         (movsd): Move next to movs.
 257         (cmpxchg16b): Move to separate section.
 258         (fisttp, fisttpll): Likewise.
 259         (monitor, mwait): Likewise.
 260         * i386-tbl.h: Re-generate.
 261
 262 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 263
 264         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 265         (vpsadbw): Add C.
 266         * i386-tbl.h: Re-generate.
 267
 268 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 269
 270         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 271         pclmul, gfni): New templates. Use them wherever possible. Move
 272         SSE4.1 pextrw into respective section.
 273         * i386-tbl.h: Re-generate.
 274
 275 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 276
 277         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 278         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 279         "length".
 280         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 281         Convert all of their uses to representation in opcode.
 282
 283 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 284
 285         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 286         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 287         value of None. Shrink operands to 3 bits.
 288
 289 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 290
 291         * i386-gen.c (process_i386_opcode_modifier): New parameter
 292         "space".
 293         (output_i386_opcode): New local variable "space". Adjust
 294         process_i386_opcode_modifier() invocation.
 295         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 296         invocation.
 297         * i386-tbl.h: Re-generate.
 298
 299 2021-03-29  Alan Modra  <amodra@gmail.com>
 300
 301         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 302         (fp_qualifier_p, get_data_pattern): Likewise.
 303         (aarch64_get_operand_modifier_from_value): Likewise.
 304         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 305         (operand_variant_qualifier_p): Likewise.
 306         (qualifier_value_in_range_constraint_p): Likewise.
 307         (aarch64_get_qualifier_esize): Likewise.
 308         (aarch64_get_qualifier_nelem): Likewise.
 309         (aarch64_get_qualifier_standard_value): Likewise.
 310         (get_lower_bound, get_upper_bound): Likewise.
 311         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 312         (aarch64_print_operand): Likewise.
 313         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 314         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 315         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 316         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 317         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 318         (print_insn_tic6x): Likewise.
 319
 320 2021-03-29  Alan Modra  <amodra@gmail.com>
 321
 322         * arc-dis.c (extract_operand_value): Correct NULL cast.
 323         * frv-opc.h: Regenerate.
 324
 325 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 326
 327         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 328         MMX form.
 329         * i386-tbl.h: Re-generate.
 330
 331 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 332
 333         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 334         immediate in br.n instruction.
 335
 336 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 337
 338         * i386-dis.c (XMGatherD, VexGatherD): New.
 339         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 340         (print_insn): Check masking for S/G insns.
 341         (OP_E_memory): New local variable check_gather. Extend mandatory
 342         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 343         Extend check for disallowed 16-bit addressing.
 344         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 345         if()s to switch(). Check register conflicts for (VEX-encoded)
 346         gathers. Drop no longer reachable cases.
 347         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 348         vgatherdp*.
 349
 350 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 351
 352         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 353         zeroing-masking without masking.
 354
 355 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 356
 357         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 358         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 359         single-operand forms as deprecated.
 360         * i386-tbl.h: Re-generate.
 361
 362 2021-03-25  Alan Modra  <amodra@gmail.com>
 363
 364         PR 27647
 365         * ppc-opc.c (XLOCB_MASK): Delete.
 366         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 367         XLBH_MASK.
 368         (powerpc_opcodes): Accept a BH field on all extended forms of
 369         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 370
 371 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 372
 373         * i386-gen.c (output_i386_opcode): Drop processing of
 374         opcode_length. Calculate length from base_opcode. Adjust prefix
 375         encoding determination.
 376         (process_i386_opcodes): Drop output of fake opcode_length.
 377         * i386-opc.h (struct insn_template): Drop opcode_length field.
 378         * i386-opc.tbl: Drop opcode length field from all templates.
 379         * i386-tbl.h: Re-generate.
 380
 381 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 382
 383         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 384         parameter "prefix". Drop local variable "regular_encoding".
 385         Record prefix setting / check for consistency.
 386         (output_i386_opcode): Parse opcode_length and base_opcode
 387         earlier. Derive prefix encoding. Drop no longer applicable
 388         consistency checking. Adjust process_i386_opcode_modifier()
 389         invocation.
 390         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 391         invocation.
 392         * i386-tbl.h: Re-generate.
 393
 394 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 395
 396         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 397         check.
 398         * i386-opc.h (Prefix_*): Move #define-s.
 399         * i386-opc.tbl: Move pseudo prefix enumerator values to
 400         extension opcode field. Introduce pseudopfx template.
 401         * i386-tbl.h: Re-generate.
 402
 403 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 404
 405         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 406         comment.
 407         * i386-tbl.h: Re-generate.
 408
 409 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 410
 411         * i386-opc.h (struct insn_template): Move cpu_flags field past
 412         opcode_modifier one.
 413         * i386-tbl.h: Re-generate.
 414
 415 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 416
 417         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 418         * i386-opc.h (OpcodeSpace): New enumerator.
 419         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 420         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 421         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 422         (struct i386_opcode_modifier): New field opcodespace. Shrink
 423         opcodeprefix field.
 424         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 425         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 426         OpcodePrefix uses.
 427         * i386-tbl.h: Re-generate.
 428
 429 2021-03-22  Martin Liska  <mliska@suse.cz>
 430
 431         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 432         * arc-dis.c (parse_option): Likewise.
 433         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 434         * cris-dis.c (print_with_operands): Likewise.
 435         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 436         * i386-dis.c (print_insn): Likewise.
 437         * ia64-gen.c (fetch_insn_class): Likewise.
 438         (parse_resource_users): Likewise.
 439         (in_iclass): Likewise.
 440         (lookup_specifier): Likewise.
 441         (insert_opcode_dependencies): Likewise.
 442         * mips-dis.c (parse_mips_ase_option): Likewise.
 443         (parse_mips_dis_option): Likewise.
 444         * s390-dis.c (disassemble_init_s390): Likewise.
 445         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 446
 447 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 448
 449         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 450
 451 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 452
 453         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 454         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 455
 456 2021-03-12  Alan Modra  <amodra@gmail.com>
 457
 458         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 459
 460 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 461
 462         * i386-dis.c (OP_XMM): Re-order checks.
 463
 464 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 465
 466         * i386-dis.c (putop): Drop need_vex check when also checking
 467         vex.evex.
 468         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 469         checking vex.b.
 470
 471 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 472
 473         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 474         checks. Move case label past broadcast check.
 475
 476 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 477
 478         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 479         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 480         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 481         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 482         EVEX_W_0F38C7_M_0_L_2): Delete.
 483         (REG_EVEX_0F38C7_M_0_L_2): New.
 484         (intel_operand_size): Handle VEX and EVEX the same for
 485         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 486         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 487         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 488         vex_vsib_q_w_d_mode uses.
 489         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 490         0F38A1, and 0F38A3 entries.
 491         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 492         entry.
 493         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 494         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 495         0F38A3 entries.
 496
 497 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 498
 499         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 500         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 501         MOD_VEX_0FXOP_09_12): Rename to ...
 502         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 503         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 504         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 505         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 506         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 507         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 508         (reg_table): Adjust comments.
 509         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 510         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 511         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 512         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 513         (vex_len_table): Adjust opcode 0A_12 entry.
 514         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 515         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 516         (rm_table): Move hreset entry.
 517
 518 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 519
 520         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 521         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 522         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 523         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 524         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 525         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 526         (get_valid_dis386): Also handle 512-bit vector length when
 527         vectoring into vex_len_table[].
 528         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 529         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 530         entries.
 531         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 532         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 533         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 534         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 535         entries.
 536
 537 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 538
 539         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 540         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 541         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 542         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 543         entries.
 544         * i386-dis-evex-len.h (evex_len_table): Likewise.
 545         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 546
 547 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 548
 549         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 550         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 551         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 552         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 553         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 554         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 555         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 556         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 557         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 558         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 559         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 560         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 561         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 562         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 563         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 564         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 565         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 566         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 567         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 568         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 569         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 570         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 571         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 572         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 573         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 574         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 575         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 576         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 577         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 578         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 579         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 580         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 581         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 582         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 583         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 584         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 585         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 586         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 587         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 588         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 589         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 590         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 591         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 592         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 593         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 594         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 595         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 596         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 597         EVEX_W_0F3A43_L_n): New.
 598         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 599         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 600         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 601         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 602         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 603         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 604         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 605         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 606         0F385B, 0F38C6, and 0F38C7 entries.
 607         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 608         0F38C6 and 0F38C7.
 609         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 610         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 611         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 612         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 613
 614 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 615
 616         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 617         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 618         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 619         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 620         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 621         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 622         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 623         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 624         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 625         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 626         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 627         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 628         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 629         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 630         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 631         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 632         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 633         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 634         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 635         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 636         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 637         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 638         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 639         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 640         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 641         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 642         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 643         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 644         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 645         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 646         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 647         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 648         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 649         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 650         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 651         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 652         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 653         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 654         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 655         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 656         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 657         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 658         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 659         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 660         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 661         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 662         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 663         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 664         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 665         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 666         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 667         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 668         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 669         VEX_W_0F99_P_2_LEN_0): Delete.
 670         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 671         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 672         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 673         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 674         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 675         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 676         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 677         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 678         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 679         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 680         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 681         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 682         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 683         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 684         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 685         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 686         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 687         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 688         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 689         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 690         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 691         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 692         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 693         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 694         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 695         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 696         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 697         (prefix_table): No longer link to vex_len_table[] for opcodes
 698         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 699         0F92, 0F93, 0F98, and 0F99.
 700         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 701         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 702         0F98, and 0F99.
 703         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 704         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 705         0F98, and 0F99.
 706         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 707         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 708         0F98, and 0F99.
 709         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 710         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 711         0F98, and 0F99.
 712
 713 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 714
 715         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 716         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 717         REG_VEX_0F73_M_0 respectively.
 718         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 719         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 720         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 721         MOD_VEX_0F73_REG_7): Delete.
 722         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 723         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 724         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 725         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 726         PREFIX_VEX_0F3AF0_L_0 respectively.
 727         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 728         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 729         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 730         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 731         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 732         VEX_LEN_0F38F7): New.
 733         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 734         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 735         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 736         0F38F3.
 737         (prefix_table): No longer link to vex_len_table[] for opcodes
 738         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 739         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 740         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 741         0F38F6, 0F38F7, and 0F3AF0.
 742         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 743         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 744         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 745         0F73.
 746
 747 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 748
 749         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 750         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 751         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 752         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 753         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 754         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 755         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 756         73.
 757         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 758         0F72, and 0F73.
 759         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 760         0F73.
 761
 762 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 763
 764         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 765         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 766         (reg_table): Don't link to mod_table[] where not needed. Add
 767         PREFIX_IGNORED to nop entries.
 768         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 769         (mod_table): Add nop entries next to prefetch ones. Drop
 770         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 771         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 772         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 773         PREFIX_OPCODE from endbr* entries.
 774         (get_valid_dis386): Also consider entry's name when zapping
 775         vindex.
 776         (print_insn): Handle PREFIX_IGNORED.
 777
 778 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 779
 780         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 781         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 782         element.
 783         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 784         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 785         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 786         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 787         (struct i386_opcode_modifier): Delete notrackprefixok,
 788         islockable, hleprefixok, and repprefixok fields. Add prefixok
 789         field.
 790         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 791         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 792         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 793         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 794         Replace HLEPrefixOk.
 795         * opcodes/i386-tbl.h: Re-generate.
 796
 797 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 798
 799         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 800         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 801         64-bit form.
 802         * opcodes/i386-tbl.h: Re-generate.
 803
 804 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 805
 806         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 807         for {} instead of {0}. Don't look for '0'.
 808         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 809         size specifiers.
 810
 811 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 812
 813         PR 27158
 814         * riscv-dis.c (print_insn_args): Updated encoding macros.
 815         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 816         (match_c_addi16sp): Updated encoding macros.
 817         (match_c_lui): Likewise.
 818         (match_c_lui_with_hint): Likewise.
 819         (match_c_addi4spn): Likewise.
 820         (match_c_slli): Likewise.
 821         (match_slli_as_c_slli): Likewise.
 822         (match_c_slli64): Likewise.
 823         (match_srxi_as_c_srxi): Likewise.
 824         (riscv_insn_types): Added .insn css/cl/cs.
 825
 826 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 827
 828         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 829         (default_priv_spec): Updated type to riscv_spec_class.
 830         (parse_riscv_dis_option): Updated.
 831         * riscv-opc.c: Moved stuff and make the file tidy.
 832
 833 2021-02-17  Alan Modra  <amodra@gmail.com>
 834
 835         * wasm32-dis.c: Include limits.h.
 836         (CHAR_BIT): Provide backup define.
 837         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 838         Correct signed overflow checking.
 839
 840 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 841
 842         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 843         * i386-tbl.h: Re-generate.
 844
 845 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 846
 847         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 848         Oword.
 849         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 850
 851 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 852
 853         * s390-mkopc.c (main): Accept arch14 as cpu string.
 854         * s390-opc.txt: Add new arch14 instructions.
 855
 856 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 857
 858         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 859         favour of LIBINTL.
 860         * configure: Regenerated.
 861
 862 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 863
 864         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 865         * tic54x-opc.c (regs): Rename to ...
 866         (tic54x_regs): ... this.
 867         (mmregs): Rename to ...
 868         (tic54x_mmregs): ... this.
 869         (condition_codes): Rename to ...
 870         (tic54x_condition_codes): ... this.
 871         (cc2_codes): Rename to ...
 872         (tic54x_cc2_codes): ... this.
 873         (cc3_codes): Rename to ...
 874         (tic54x_cc3_codes): ... this.
 875         (status_bits): Rename to ...
 876         (tic54x_status_bits): ... this.
 877         (misc_symbols): Rename to ...
 878         (tic54x_misc_symbols): ... this.
 879
 880 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 881
 882         * riscv-opc.c (MASK_RVB_IMM): Removed.
 883         (riscv_opcodes): Removed zb* instructions.
 884         (riscv_ext_version_table): Removed versions for zb*.
 885
 886 2021-01-26  Alan Modra  <amodra@gmail.com>
 887
 888         * i386-gen.c (parse_template): Ensure entire template_instance
 889         is initialised.
 890
 891 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 892
 893         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 894         (riscv_fpr_names_abi): Likewise.
 895         (riscv_opcodes): Likewise.
 896         (riscv_insn_types): Likewise.
 897
 898 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 899
 900         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 901
 902 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 903
 904         * riscv-dis.c: Comments tidy and improvement.
 905         * riscv-opc.c: Likewise.
 906
 907 2021-01-13  Alan Modra  <amodra@gmail.com>
 908
 909         * Makefile.in: Regenerate.
 910
 911 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 912
 913         PR binutils/26792
 914         * configure.ac: Use GNU_MAKE_JOBSERVER.
 915         * aclocal.m4: Regenerated.
 916         * configure: Likewise.
 917
 918 2021-01-12  Nick Clifton  <nickc@redhat.com>
 919
 920         * po/sr.po: Updated Serbian translation.
 921
 922 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 923
 924         PR ld/27173
 925         * configure: Regenerated.
 926
 927 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 928
 929         * aarch64-asm-2.c: Regenerate.
 930         * aarch64-dis-2.c: Likewise.
 931         * aarch64-opc-2.c: Likewise.
 932         * aarch64-opc.c (aarch64_print_operand):
 933         Delete handling of AARCH64_OPND_CSRE_CSR.
 934         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 935         (CSRE): Likewise.
 936         (_CSRE_INSN): Likewise.
 937         (aarch64_opcode_table): Delete csr.
 938
 939 2021-01-11  Nick Clifton  <nickc@redhat.com>
 940
 941         * po/de.po: Updated German translation.
 942         * po/fr.po: Updated French translation.
 943         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 944         * po/sv.po: Updated Swedish translation.
 945         * po/uk.po: Updated Ukranian translation.
 946
 947 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 948
 949         * configure: Regenerated.
 950
 951 2021-01-09  Nick Clifton  <nickc@redhat.com>
 952
 953         * configure: Regenerate.
 954         * po/opcodes.pot: Regenerate.
 955
 956 2021-01-09  Nick Clifton  <nickc@redhat.com>
 957
 958         * 2.36 release branch crated.
 959
 960 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 961
 962         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 963         (DW, (XRC_MASK): Define.
 964         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 965
 966 2021-01-09  Alan Modra  <amodra@gmail.com>
 967
 968         * configure: Regenerate.
 969
 970 2021-01-08  Nick Clifton  <nickc@redhat.com>
 971
 972         * po/sv.po: Updated Swedish translation.
 973
 974 2021-01-08  Nick Clifton  <nickc@redhat.com>
 975
 976         PR 27129
 977         * aarch64-dis.c (determine_disassembling_preference): Move call to
 978         aarch64_match_operands_constraint outside of the assertion.
 979         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 980         Replace with a return of FALSE.
 981
 982         PR 27139
 983         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 984         core system register.
 985
 986 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 987
 988         * configure: Regenerate.
 989
 990 2021-01-07  Nick Clifton  <nickc@redhat.com>
 991
 992         * po/fr.po: Updated French translation.
 993
 994 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 995
 996         * m68k-opc.c (chkl): Change minimum architecture requirement to
 997         m68020.
 998
 999 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1000
1001         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1002
1003 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1004             Jim Wilson  <jimw@sifive.com>
1005             Andrew Waterman  <andrew@sifive.com>
1006             Maxim Blinov  <maxim.blinov@embecosm.com>
1007             Kito Cheng  <kito.cheng@sifive.com>
1008             Nelson Chu  <nelson.chu@sifive.com>
1009
1010         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1011         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1012
1013 2021-01-01  Alan Modra  <amodra@gmail.com>
1014
1015         Update year range in copyright notice of all files.
1016
1017 For older changes see ChangeLog-2020
1018 \f
1019 Copyright (C) 2021 Free Software Foundation, Inc.
1020
1021 Copying and distribution of this file, with or without modification,
1022 are permitted in any medium without royalty provided the copyright
1023 notice and this notice are preserved.
1024
1025 Local Variables:
1026 mode: change-log
1027 left-margin: 8
1028 fill-column: 74
1029 version-control: never
1030 End: