1 2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com>
3 * csky-opc.h (csky_v2_opcodes): Change plsl.u16 to plsl.16.
5 2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com>
7 * csky-dis.c (csky_output_operand): Add handler for
8 OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
9 * csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum.
10 (OPRND_TYPE_IMM5b_VSH): New enum. (csky_v2_opcodes): Fix and add
11 some instructions for VDSPV1.
13 2020-10-26 Lili Cui <lili.cui@intel.com>
15 * i386-dis.c: Change "XV" to print "{vex}" pseudo prefix.
17 2020-10-22 H.J. Lu <hongjiu.lu@intel.com>
19 * po/es.po: Remove the duplicated entry.
21 2020-10-20 Dr. David Alan Gilbert <dgilbert@redhat.com>
23 * po/es.po: Fix printf format.
25 2020-10-20 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
27 * i386-dis.c (rm_table): Add tlbsync, snp, invlpgb.
28 * i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS,
29 CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS.
31 (cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
32 * i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
33 * i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate,
35 * i386-init.h: Re-generated.
36 * i386-tbl.h: Re-generated.
38 2020-10-16 Lili Cui <lili.cui@intel.com>
40 * i386-opc.tbl: Rename CpuVEX_PREFIX to PseudoVexPrefix
41 and move it from cpu_flags to opcode_modifiers.
42 Use VexW0 and VexVVVV in the AVX-VNNI instructions.
43 * i386-gen.c: Likewise.
44 * i386-opc.h: Likewise.
45 * i386-opc.h: Likewise.
46 * i386-init.h: Regenerated.
47 * i386-tbl.h: Likewise.
49 2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
50 Lili Cui <lili.cui@intel.com>
52 * i386-dis.c (PREFIX_VEX_0F3850): New.
53 (PREFIX_VEX_0F3851): Likewise.
54 (PREFIX_VEX_0F3852): Likewise.
55 (PREFIX_VEX_0F3853): Likewise.
56 (VEX_W_0F3850_P_2): Likewise.
57 (VEX_W_0F3851_P_2): Likewise.
58 (VEX_W_0F3852_P_2): Likewise.
59 (VEX_W_0F3853_P_2): Likewise.
60 (prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851,
61 PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853.
62 (vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2,
63 VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2.
64 (putop): Add support for "XV" to print "{vex3}" pseudo prefix.
65 * i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in
66 CPU_UNKNOWN_FLAGS. Add CPU_AVX_VNNI_FLAGS and
67 CPU_ANY_AVX_VNNI_FLAGS.
68 (cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX.
69 * i386-opc.h (CpuAVX_VNNI): New.
70 (CpuVEX_PREFIX): Likewise.
71 (i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix.
72 * i386-opc.tbl: Add Intel AVX VNNI instructions.
73 * i386-init.h: Regenerated.
74 * i386-tbl.h: Likewise.
76 2020-10-14 Lili Cui <lili.cui@intel.com>
77 H.J. Lu <hongjiu.lu@intel.com>
79 * i386-dis.c (PREFIX_0F3A0F): New.
80 (MOD_0F3A0F_PREFIX_1): Likewise.
81 (REG_0F3A0F_PREFIX_1_MOD_3): Likewise.
82 (RM_0F3A0F_P_1_MOD_3_REG_0): Likewise.
83 (prefix_table): Add PREFIX_0F3A0F.
84 (mod_table): Add MOD_0F3A0F_PREFIX_1.
85 (reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3.
86 (rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0.
87 * i386-gen.c (cpu_flag_init): Add HRESET_FLAGS,
89 (cpu_flags): Add CpuHRESET.
90 (output_i386_opcode): Allow 4 byte base_opcode.
91 * i386-opc.h (enum): Add CpuHRESET.
92 (i386_cpu_flags): Add cpuhreset.
93 * i386-opc.tbl: Add Intel HRESET instruction.
94 * i386-init.h: Regenerate.
95 * i386-tbl.h: Likewise.
97 2020-10-14 Lili Cui <lili.cui@intel.com>
99 * i386-dis.c (enum): Add
100 PREFIX_MOD_3_0F01_REG_5_RM_4,
101 PREFIX_MOD_3_0F01_REG_5_RM_5,
102 PREFIX_MOD_3_0F01_REG_5_RM_6,
103 PREFIX_MOD_3_0F01_REG_5_RM_7,
104 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
105 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
106 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
107 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
108 X86_64_0FC7_REG_6_MOD_3_PREFIX_1.
109 (prefix_table): New instructions (see prefixes above).
111 * i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS,
113 (cpu_flags): Add CpuUINTR.
114 * i386-opc.h (enum): Add CpuUINTR.
115 (i386_cpu_flags): Add cpuuintr.
116 * i386-opc.tbl: Add UINTR insns.
117 * i386-init.h: Regenerate.
118 * i386-tbl.h: Likewise.
120 2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
122 * i386-gen.c (process_i386_opcode_modifier): Return 1 for
123 non-VEX/EVEX/prefix encoding.
124 (output_i386_opcode): Fail if non-VEX/EVEX/prefix base_opcode
126 * i386-opc.tbl: Replace the prefix byte in non-VEX/EVEX
127 base_opcode with PREFIX_0X66, PREFIX_0XF2 or PREFIX_0XF3.
128 * i386-tbl.h: Regenerated.
130 2020-10-13 H.J. Lu <hongjiu.lu@intel.com>
132 * i386-gen.c (opcode_modifiers): Replace VexOpcode with
134 * i386-opc.h (VexOpcode): Renamed to ...
135 (OpcodePrefix): This.
137 (PREFIX_0X66): Likewise.
138 (PREFIX_0XF2): Likewise.
139 (PREFIX_0XF3): Likewise.
140 * i386-opc.tbl (Prefix_0X66): New.
141 (Prefix_0XF2): Likewise.
142 (Prefix_0XF3): Likewise.
143 Replace VexOpcode= with OpcodePrefix=. Use Prefix_0X66 on xorpd.
144 Use Prefix_0XF3 on cvtdq2pd. Use Prefix_0XF2 on cvtpd2dq.
145 * i386-tbl.h: Regenerated.
147 2020-10-05 Samanta Navarro <ferivoz@riseup.net>
149 * cgen-asm.c: Fix spelling mistakes.
150 * cgen-dis.c: Fix spelling mistakes.
151 * tic30-dis.c: Fix spelling mistakes.
153 2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
156 * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
158 2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
161 * i386-dis.c (print_insn): Clear modrm if not needed.
162 (putop): Check need_modrm for modrm.mod != 3. Don't check
163 need_modrm for modrm.mod == 3.
165 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
167 * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
168 TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
169 TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
170 TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
171 TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
172 TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
173 TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
174 TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
175 WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
176 TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
177 TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
178 TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVDARCCTLR,
179 TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
180 TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
182 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
184 * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
186 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
188 * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
189 TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
191 2020-09-26 Alan Modra <amodra@gmail.com>
193 * csky-opc.h: Formatting.
194 (GENERAL_REG_BANK): Correct spelling. Update use throughout file.
195 (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
197 (get_register_number): Likewise.
198 * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
200 2020-09-24 Lili Cui <lili.cui@intel.com>
203 * i386-dis.c (enum): Put MOD_VEX_0F38* together.
205 2020-09-24 Andrew Burgess <andrew.burgess@embecosm.com>
207 * csky-dis.c (csky_output_operand): Enclose body of if in curly
210 2020-09-24 Lili Cui <lili.cui@intel.com>
212 * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
213 PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
214 X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
215 X86_64_0F01_REG_1_RM_7_P_2.
216 (prefix_table): Likewise.
217 (x86_64_table): Likewise.
218 (rm_table): Likewise.
219 * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
220 and CPU_ANY_TDX_FLAGS.
221 (cpu_flags): Add CpuTDX.
222 * i386-opc.h (enum): Add CpuTDX.
223 (i386_cpu_flags): Add cputdx.
224 * i386-opc.tbl: Add TDX insns.
225 * i386-init.h: Regenerate.
226 * i386-tbl.h: Likewise.
228 2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
230 * csky-dis.c (using_abi): New.
231 (parse_csky_dis_options): New function.
232 (get_gr_name): New function.
233 (get_cr_name): New function.
234 (csky_output_operand): Use get_gr_name and get_cr_name to
235 disassemble and add handle of OPRND_TYPE_IMM5b_LS.
236 (print_insn_csky): Parse disassembler options.
237 * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
238 (GENARAL_REG_BANK): Define.
239 (REG_SUPPORT_ALL): Define.
240 (REG_SUPPORT_ALL): New.
242 (REG_SUPPORT_A): Define.
243 (REG_SUPPORT_B): Define.
244 (REG_SUPPORT_C): Define.
245 (REG_SUPPORT_D): Define.
246 (REG_SUPPORT_E): Define.
247 (csky_abiv1_general_regs): New.
248 (csky_abiv1_control_regs): New.
249 (csky_abiv2_general_regs): New.
250 (csky_abiv2_control_regs): New.
251 (get_register_name): New function.
252 (get_register_number): New function.
253 (csky_get_general_reg_name): New function.
254 (csky_get_general_regno): New function.
255 (csky_get_control_reg_name): New function.
256 (csky_get_control_regno): New function.
257 (csky_v2_opcodes): Prefer two oprerans format for bclri and
258 bseti, strengthen the operands legality check of addc, zext
261 2020-09-23 Lili Cui <lili.cui@intel.com>
263 * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
264 MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
265 MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
266 MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
267 PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
268 (reg_table): New instructions (see prefixes above).
269 (prefix_table): Likewise.
270 (three_byte_table): Likewise.
271 (mod_table): Likewise
272 * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
273 CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
274 (cpu_flags): Likewise.
275 (operand_type_init): Likewise.
276 * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
277 (i386_cpu_flags): Add cpukl and cpuwide_kl.
278 * i386-opc.tbl: Add KL and WIDE_KL insns.
279 * i386-init.h: Regenerate.
280 * i386-tbl.h: Likewise.
282 2020-09-21 Alan Modra <amodra@gmail.com>
284 * rx-dis.c (flag_names): Add missing comma.
285 (register_names, flag_names, double_register_names),
286 (double_register_high_names, double_register_low_names),
287 (double_control_register_names, double_condition_names): Remove
290 2020-09-18 David Faust <david.faust@oracle.com>
292 * bpf-desc.c: Regenerate.
293 * bpf-desc.h: Likewise.
294 * bpf-opc.c: Likewise.
295 * bpf-opc.h: Likewise.
297 2020-09-16 Andrew Burgess <andrew.burgess@embecosm.com>
299 * csky-dis.c (csky_get_disassembler): Don't return NULL when there
302 2020-09-16 Alan Modra <amodra@gmail.com>
304 * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
306 2020-09-10 Nick Clifton <nickc@redhat.com>
308 * ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
309 for hidden, local, no-type symbols.
310 (disassemble_init_powerpc): Point the symbol_is_valid field in the
311 info structure at the new function.
313 2020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
315 * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
316 * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
319 2020-09-10 Nick Clifton <nickc@redhat.com>
321 * csky-dis.c (csky_output_operand): Coerce the immediate values to
322 long before printing.
324 2020-09-10 Alan Modra <amodra@gmail.com>
326 * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
328 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
330 * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
333 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
335 * csky-dis.c (csky_output_operand): Add handlers for
336 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
337 OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
338 to support FPUV3 instructions.
339 * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
340 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
341 OPRND_TYPE_DFLOAT_FMOVI.
342 (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
343 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
344 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
345 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
346 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
347 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
348 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
349 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
350 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
351 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
352 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
353 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
354 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
355 (csky_v2_opcodes): Add FPUV3 instructions.
357 2020-09-08 Alex Coplan <alex.coplan@arm.com>
359 * aarch64-dis.c (print_operands): Pass CPU features to
360 aarch64_print_operand().
361 * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
362 preferred disassembly of system registers.
363 (SR_RNG): Refactor to use new SR_FEAT2 macro.
369 (SR_EXPAND_ELx): New.
370 (SR_EXPAND_EL12): New.
371 (aarch64_sys_regs): Specify which registers are only on
372 A-profile, add R-profile system registers.
376 (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
379 2020-09-08 Alex Coplan <alex.coplan@arm.com>
381 * aarch64-tbl.h (aarch64_feature_v8_r): New.
384 (aarch64_opcode_table): Add dfb.
385 * aarch64-opc-2.c: Regenerate.
386 * aarch64-asm-2.c: Regenerate.
387 * aarch64-dis-2.c: Regenerate.
389 2020-09-08 Alex Coplan <alex.coplan@arm.com>
391 * aarch64-dis.c (arch_variant): New.
392 (determine_disassembling_preference): Disassemble according to
394 (select_aarch64_variant): New.
395 (print_insn_aarch64): Set feature set.
397 2020-09-02 Alan Modra <amodra@gmail.com>
399 * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
400 (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
401 (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
402 (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
403 (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
404 (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
405 (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
406 for value parameter and update code to suit.
407 (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
408 (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
410 2020-09-02 Alan Modra <amodra@gmail.com>
412 * i386-dis.c (OP_E_memory): Don't cast to signed type when
414 (get32, get32s): Use unsigned types in shift expressions.
416 2020-09-02 Alan Modra <amodra@gmail.com>
418 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
420 2020-09-02 Alan Modra <amodra@gmail.com>
422 * crx-dis.c: Whitespace.
423 (print_arg): Use unsigned type for longdisp and mask variables,
424 and for left shift constant.
426 2020-09-02 Alan Modra <amodra@gmail.com>
428 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
429 * bpf-ibld.c: Regenerate.
430 * epiphany-ibld.c: Regenerate.
431 * fr30-ibld.c: Regenerate.
432 * frv-ibld.c: Regenerate.
433 * ip2k-ibld.c: Regenerate.
434 * iq2000-ibld.c: Regenerate.
435 * lm32-ibld.c: Regenerate.
436 * m32c-ibld.c: Regenerate.
437 * m32r-ibld.c: Regenerate.
438 * mep-ibld.c: Regenerate.
439 * mt-ibld.c: Regenerate.
440 * or1k-ibld.c: Regenerate.
441 * xc16x-ibld.c: Regenerate.
442 * xstormy16-ibld.c: Regenerate.
444 2020-09-02 Alan Modra <amodra@gmail.com>
446 * bfin-dis.c (MASKBITS): Use SIGNBIT.
448 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
450 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
451 to CSKYV2_ISA_3E3R3 instruction set.
453 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
455 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
457 2020-09-01 Alan Modra <amodra@gmail.com>
459 * mep-ibld.c: Regenerate.
461 2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
463 * csky-dis.c (csky_output_operand): Assign dis_info.value for
466 2020-08-30 Alan Modra <amodra@gmail.com>
468 * cr16-dis.c: Formatting.
469 (parameter): Delete struct typedef. Use dwordU instead
471 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
473 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
475 2020-08-29 Alan Modra <amodra@gmail.com>
478 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
479 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
481 2020-08-28 Alan Modra <amodra@gmail.com>
485 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
486 (extract_normal): Likewise.
487 (insert_normal): Likewise, and move past zero length test.
488 (put_insn_int_value): Handle mask for zero length, use 1UL.
489 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
490 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
491 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
492 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
494 2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
496 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
497 (csky_dis_info): Add member isa.
498 (csky_find_inst_info): Skip instructions that do not belong to
500 (csky_get_disassembler): Get infomation from attribute section.
501 (print_insn_csky): Set defualt ISA flag.
502 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
503 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
504 isa_flag32'type to unsigned 64 bits.
506 2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
508 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
510 2020-08-26 David Faust <david.faust@oracle.com>
512 * bpf-desc.c: Regenerate.
513 * bpf-desc.h: Likewise.
514 * bpf-opc.c: Likewise.
515 * bpf-opc.h: Likewise.
516 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
517 ISA when appropriate.
519 2020-08-25 Alan Modra <amodra@gmail.com>
522 * vax-dis.c (parse_disassembler_options): Always add at least one
523 to entry_addr_total_slots.
525 2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
527 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
528 in other CPUs to speed up disassembling.
529 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
530 Change plsli.u16 to plsli.16, change sync's operand format.
532 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
534 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
536 2020-08-21 Nick Clifton <nickc@redhat.com>
538 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
541 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
543 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
545 2020-08-19 Alan Modra <amodra@gmail.com>
547 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
550 2020-08-18 Peter Bergner <bergner@linux.ibm.com>
552 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
553 <xvcvbf16spn>: ...to this.
555 2020-08-12 Alex Coplan <alex.coplan@arm.com>
557 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
559 2020-08-12 Nick Clifton <nickc@redhat.com>
561 * po/sr.po: Updated Serbian translation.
563 2020-08-11 Alan Modra <amodra@gmail.com>
565 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
567 2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
569 * aarch64-opc.c (aarch64_print_operand):
570 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
571 (aarch64_sys_reg_supported_p): Function removed.
572 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
573 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
576 2020-08-10 Alan Modra <amodra@gmail.com>
578 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
581 2020-08-10 Alan Modra <amodra@gmail.com>
583 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
584 Enable icbt for power5, miso for power8.
586 2020-08-10 Alan Modra <amodra@gmail.com>
588 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
589 mtvsrd, and similarly for mfvsrd.
591 2020-08-04 Christian Groessler <chris@groessler.org>
592 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
594 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
595 opcodes (special "out" to absolute address).
596 * z8k-opc.h: Regenerate.
598 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
601 * i386-opc.h (Prefix_Disp8): New.
602 (Prefix_Disp16): Likewise.
603 (Prefix_Disp32): Likewise.
604 (Prefix_Load): Likewise.
605 (Prefix_Store): Likewise.
606 (Prefix_VEX): Likewise.
607 (Prefix_VEX3): Likewise.
608 (Prefix_EVEX): Likewise.
609 (Prefix_REX): Likewise.
610 (Prefix_NoOptimize): Likewise.
611 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
612 * i386-tbl.h: Regenerated.
614 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
616 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
617 default case with abort() instead of printing an error message and
618 continuing, to avoid a maybe-uninitialized warning.
620 2020-07-24 Nick Clifton <nickc@redhat.com>
622 * po/de.po: Updated German translation.
624 2020-07-21 Jan Beulich <jbeulich@suse.com>
626 * i386-dis.c (OP_E_memory): Revert previous change.
628 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
631 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
632 without base nor index registers.
634 2020-07-15 Jan Beulich <jbeulich@suse.com>
636 * i386-dis.c (putop): Move 'V' and 'W' handling.
638 2020-07-15 Jan Beulich <jbeulich@suse.com>
640 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
641 construct for push/pop of register.
642 (putop): Honor cond when handling 'P'. Drop handling of plain
645 2020-07-15 Jan Beulich <jbeulich@suse.com>
647 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
648 description. Drop '&' description. Use P for push of immediate,
649 pushf/popf, enter, and leave. Use %LP for lret/retf.
650 (dis386_twobyte): Use P for push/pop of fs/gs.
651 (reg_table): Use P for push/pop. Use @ for near call/jmp.
652 (x86_64_table): Use P for far call/jmp.
653 (putop): Drop handling of 'U' and '&'. Move and adjust handling
654 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
656 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
657 and dqw_mode (unconditional).
659 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
662 * i386-dis.c (OP_E_memory): Without base nor index registers,
663 32-bit displacement to 64 bits.
665 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
667 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
668 faulty double register pair is detected.
670 2020-07-14 Jan Beulich <jbeulich@suse.com>
672 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
674 2020-07-14 Jan Beulich <jbeulich@suse.com>
676 * i386-dis.c (OP_R, Rm): Delete.
677 (MOD_0F24, MOD_0F26): Rename to ...
678 (X86_64_0F24, X86_64_0F26): ... respectively.
679 (dis386): Update 'L' and 'Z' comments.
680 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
682 (mod_table): Move opcode 0F24 and 0F26 entries ...
683 (x86_64_table): ... here.
684 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
687 2020-07-14 Jan Beulich <jbeulich@suse.com>
689 * i386-dis.c (Rd, Rdq, MaskR): Delete.
690 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
691 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
692 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
693 MOD_EVEX_0F387C): New enumerators.
694 (reg_table): Use Edq for rdssp.
695 (prefix_table): Use Edq for incssp.
696 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
697 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
698 ktest*, and kshift*. Use Edq / MaskE for kmov*.
699 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
700 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
701 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
702 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
703 0F3828_P_1 and 0F3838_P_1.
704 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
705 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
707 2020-07-14 Jan Beulich <jbeulich@suse.com>
709 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
710 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
711 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
712 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
713 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
714 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
715 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
716 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
717 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
718 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
719 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
720 (reg_table, prefix_table, three_byte_table, vex_table,
721 vex_len_table, mod_table, rm_table): Replace / remove respective
723 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
724 of PREFIX_DATA in used_prefixes.
726 2020-07-14 Jan Beulich <jbeulich@suse.com>
728 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
729 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
730 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
731 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
732 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
733 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
734 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
735 VEX_W_0F3A33_L_0): Delete.
736 (dis386): Adjust "BW" description.
737 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
738 0F3A31, 0F3A32, and 0F3A33.
739 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
741 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
744 2020-07-14 Jan Beulich <jbeulich@suse.com>
746 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
747 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
748 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
749 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
750 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
751 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
752 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
753 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
754 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
755 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
756 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
757 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
758 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
759 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
760 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
761 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
762 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
763 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
764 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
765 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
766 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
767 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
768 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
769 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
770 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
771 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
772 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
773 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
774 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
775 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
776 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
777 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
778 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
779 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
780 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
781 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
782 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
783 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
784 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
785 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
786 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
787 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
788 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
789 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
790 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
791 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
792 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
793 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
794 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
795 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
796 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
797 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
798 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
799 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
800 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
801 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
802 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
803 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
804 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
805 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
806 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
807 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
808 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
809 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
810 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
811 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
812 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
813 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
814 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
815 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
816 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
817 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
818 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
819 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
820 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
821 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
822 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
823 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
824 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
825 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
826 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
827 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
828 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
829 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
830 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
831 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
832 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
833 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
834 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
835 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
836 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
837 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
838 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
839 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
840 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
841 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
842 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
843 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
844 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
845 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
846 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
847 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
848 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
849 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
850 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
851 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
852 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
853 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
854 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
855 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
856 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
857 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
858 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
859 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
860 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
861 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
862 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
863 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
864 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
865 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
866 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
867 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
868 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
869 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
870 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
871 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
872 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
873 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
874 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
875 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
876 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
877 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
878 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
879 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
880 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
881 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
882 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
883 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
884 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
885 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
886 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
887 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
888 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
889 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
890 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
891 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
892 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
893 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
894 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
895 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
896 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
897 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
898 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
899 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
900 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
901 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
902 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
903 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
904 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
905 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
906 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
907 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
908 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
909 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
910 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
911 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
912 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
913 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
914 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
915 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
916 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
917 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
918 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
919 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
920 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
921 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
922 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
923 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
924 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
925 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
926 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
927 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
928 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
929 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
930 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
931 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
932 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
933 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
934 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
935 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
936 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
937 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
938 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
939 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
940 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
941 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
942 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
943 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
944 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
945 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
946 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
947 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
948 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
949 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
950 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
951 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
952 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
953 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
954 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
955 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
956 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
957 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
958 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
959 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
960 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
961 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
962 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
963 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
964 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
965 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
966 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
967 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
968 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
969 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
970 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
971 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
972 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
973 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
974 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
975 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
976 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
977 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
978 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
979 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
980 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
981 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
982 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
983 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
984 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
985 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
986 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
987 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
988 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
989 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
990 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
991 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
992 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
993 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
994 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
995 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
996 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
997 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
998 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
999 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
1000 EVEX_W_0F3A72_P_2): Rename to ...
1001 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
1002 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
1003 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
1004 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
1005 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
1006 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
1007 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
1008 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
1009 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
1010 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
1011 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
1012 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
1013 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
1014 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
1015 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
1016 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
1017 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
1018 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
1019 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
1020 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
1021 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
1022 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
1023 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
1024 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
1025 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
1026 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
1027 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
1028 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
1029 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
1030 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
1031 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
1032 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
1033 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
1034 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
1035 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
1036 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
1037 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
1038 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
1039 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
1040 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
1041 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
1042 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
1043 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
1044 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
1045 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
1046 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
1047 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
1048 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
1049 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
1050 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
1051 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
1052 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
1053 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
1054 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
1055 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
1056 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
1057 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
1058 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
1059 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
1060 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
1061 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
1062 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
1063 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
1064 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
1065 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
1066 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
1067 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
1068 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
1069 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
1070 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
1071 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
1072 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
1074 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
1075 vex_w_table, mod_table): Replace / remove respective entries.
1076 (print_insn): Move up dp->prefix_requirement handling. Handle
1078 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
1079 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
1080 Replace / remove respective entries.
1082 2020-07-14 Jan Beulich <jbeulich@suse.com>
1084 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
1085 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
1086 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
1087 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
1088 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
1090 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1091 0F2C, 0F2D, 0F2E, and 0F2F.
1092 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
1095 2020-07-14 Jan Beulich <jbeulich@suse.com>
1097 * i386-dis.c (OP_VexR, VexScalarR): New.
1098 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
1099 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
1100 need_vex_reg): Delete.
1101 (prefix_table): Replace VexScalar by VexScalarR and
1102 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1103 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1104 (vex_len_table): Replace EXqVexScalarS by EXqS.
1105 (get_valid_dis386): Don't set need_vex_reg.
1106 (print_insn): Don't initialize need_vex_reg.
1107 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
1108 q_scalar_swap_mode cases.
1109 (OP_EX): Don't check for d_scalar_swap_mode and
1111 (OP_VEX): Done check need_vex_reg.
1112 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
1113 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1114 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1116 2020-07-14 Jan Beulich <jbeulich@suse.com>
1118 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
1119 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
1120 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
1121 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
1122 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
1123 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
1124 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
1125 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
1126 (vex_table): Replace Vex128 by Vex.
1127 (vex_len_table): Likewise. Adjust referenced enum names.
1128 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
1129 referenced enum names.
1130 (OP_VEX): Drop vex128_mode and vex256_mode cases.
1131 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
1133 2020-07-14 Jan Beulich <jbeulich@suse.com>
1135 * i386-dis.c (dis386): "LW" description now applies to "DQ".
1136 (putop): Handle "DQ". Don't handle "LW" anymore.
1137 (prefix_table, mod_table): Replace %LW by %DQ.
1138 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
1140 2020-07-14 Jan Beulich <jbeulich@suse.com>
1142 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
1143 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
1144 d_scalar_swap_mode case handling. Move shift adjsutment into
1145 the case its applicable to.
1147 2020-07-14 Jan Beulich <jbeulich@suse.com>
1149 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
1150 (EXbScalar, EXwScalar): Fold to ...
1151 (EXbwUnit): ... this.
1152 (b_scalar_mode, w_scalar_mode): Fold to ...
1153 (bw_unit_mode): ... this.
1154 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
1155 w_scalar_mode handling by bw_unit_mode one.
1156 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
1158 * i386-dis-evex-prefix.h: ... here.
1160 2020-07-14 Jan Beulich <jbeulich@suse.com>
1162 * i386-dis.c (PCMPESTR_Fixup): Delete.
1163 (dis386): Adjust "LQ" description.
1164 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
1165 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
1166 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
1167 vpcmpestrm, and vpcmpestri.
1168 (putop): Honor "cond" when handling LQ.
1169 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
1170 vcvtsi2ss and vcvtusi2ss.
1171 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
1172 vcvtsi2sd and vcvtusi2sd.
1174 2020-07-14 Jan Beulich <jbeulich@suse.com>
1176 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
1177 (simd_cmp_op): Add const.
1178 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
1179 (CMP_Fixup): Handle VEX case.
1180 (prefix_table): Replace VCMP by CMP.
1181 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
1183 2020-07-14 Jan Beulich <jbeulich@suse.com>
1185 * i386-dis.c (MOVBE_Fixup): Delete.
1187 (prefix_table): Use Mv for movbe entries.
1189 2020-07-14 Jan Beulich <jbeulich@suse.com>
1191 * i386-dis.c (CRC32_Fixup): Delete.
1192 (prefix_table): Use Eb/Ev for crc32 entries.
1194 2020-07-14 Jan Beulich <jbeulich@suse.com>
1196 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
1197 Conditionalize invocations of "USED_REX (0)".
1199 2020-07-14 Jan Beulich <jbeulich@suse.com>
1201 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
1202 CH, DH, BH, AX, DX): Delete.
1203 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
1204 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
1205 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
1207 2020-07-10 Lili Cui <lili.cui@intel.com>
1209 * i386-dis.c (TMM): New.
1212 (MVexSIBMEM): Likewise.
1213 (tmm_mode): Likewise.
1214 (vex_sibmem_mode): Likewise.
1215 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
1216 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
1217 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
1218 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
1219 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
1220 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
1221 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
1222 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
1223 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
1224 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
1225 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
1226 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
1227 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
1228 (PREFIX_VEX_0F3849_X86_64): Likewise.
1229 (PREFIX_VEX_0F384B_X86_64): Likewise.
1230 (PREFIX_VEX_0F385C_X86_64): Likewise.
1231 (PREFIX_VEX_0F385E_X86_64): Likewise.
1232 (X86_64_VEX_0F3849): Likewise.
1233 (X86_64_VEX_0F384B): Likewise.
1234 (X86_64_VEX_0F385C): Likewise.
1235 (X86_64_VEX_0F385E): Likewise.
1236 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
1237 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
1238 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
1239 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
1240 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
1241 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
1242 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
1243 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
1244 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
1245 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
1246 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
1247 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
1248 (VEX_W_0F3849_X86_64_P_0): Likewise.
1249 (VEX_W_0F3849_X86_64_P_2): Likewise.
1250 (VEX_W_0F3849_X86_64_P_3): Likewise.
1251 (VEX_W_0F384B_X86_64_P_1): Likewise.
1252 (VEX_W_0F384B_X86_64_P_2): Likewise.
1253 (VEX_W_0F384B_X86_64_P_3): Likewise.
1254 (VEX_W_0F385C_X86_64_P_1): Likewise.
1255 (VEX_W_0F385E_X86_64_P_0): Likewise.
1256 (VEX_W_0F385E_X86_64_P_1): Likewise.
1257 (VEX_W_0F385E_X86_64_P_2): Likewise.
1258 (VEX_W_0F385E_X86_64_P_3): Likewise.
1259 (names_tmm): Likewise.
1260 (att_names_tmm): Likewise.
1261 (intel_operand_size): Handle void_mode.
1262 (OP_XMM): Handle tmm_mode.
1265 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
1266 CpuAMX_BF16 and CpuAMX_TILE.
1267 (operand_type_shorthands): Add RegTMM.
1268 (operand_type_init): Likewise.
1269 (operand_types): Add Tmmword.
1270 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1271 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1272 * i386-opc.h (CpuAMX_INT8): New.
1273 (CpuAMX_BF16): Likewise.
1274 (CpuAMX_TILE): Likewise.
1276 (Tmmword): Likewise.
1277 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
1278 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
1279 (i386_operand_type): Add tmmword.
1280 * i386-opc.tbl: Add AMX instructions.
1281 * i386-reg.tbl: Add AMX registers.
1282 * i386-init.h: Regenerated.
1283 * i386-tbl.h: Likewise.
1285 2020-07-08 Jan Beulich <jbeulich@suse.com>
1287 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1288 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1290 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1291 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1293 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1294 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1295 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1296 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1297 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1298 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1299 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1300 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1301 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1302 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1303 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1304 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1305 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1306 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1307 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1308 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1309 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1310 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1311 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1312 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1313 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1314 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1315 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1316 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1317 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1318 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1319 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1320 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1321 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1322 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1323 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1324 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1325 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1326 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1327 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1328 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1329 (reg_table): Re-order XOP entries. Adjust their operands.
1330 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1331 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1332 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1333 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1334 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1335 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1336 entries by references ...
1337 (vex_len_table): ... to resepctive new entries here. For several
1338 new and existing entries reference ...
1339 (vex_w_table): ... new entries here.
1340 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1342 2020-07-08 Jan Beulich <jbeulich@suse.com>
1344 * i386-dis.c (XMVexScalarI4): Define.
1345 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1346 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1347 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1348 (vex_len_table): Move scalar FMA4 entries ...
1349 (prefix_table): ... here.
1350 (OP_REG_VexI4): Handle scalar_mode.
1351 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1352 * i386-tbl.h: Re-generate.
1354 2020-07-08 Jan Beulich <jbeulich@suse.com>
1356 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1357 Vex_2src_2): Delete.
1358 (OP_VexW, VexW): New.
1359 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1360 for shifts and rotates by register.
1362 2020-07-08 Jan Beulich <jbeulich@suse.com>
1364 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1365 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1366 OP_EX_VexReg): Delete.
1367 (OP_VexI4, VexI4): New.
1368 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1369 (prefix_table): ... here.
1370 (print_insn): Drop setting of vex_w_done.
1372 2020-07-08 Jan Beulich <jbeulich@suse.com>
1374 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1375 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1376 (xop_table): Replace operands of 4-operand insns.
1377 (OP_REG_VexI4): Move VEX.W based operand swaping here.
1379 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
1381 * arc-opc.c (insert_rbd): New function.
1384 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1387 2020-07-07 Jan Beulich <jbeulich@suse.com>
1389 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1390 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1391 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1392 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1394 (putop): Handle "BW".
1395 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1396 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1398 * i386-dis-evex-prefix.h: ... here.
1400 2020-07-06 Jan Beulich <jbeulich@suse.com>
1402 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1403 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1404 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1405 VEX_W_0FXOP_09_83): New enumerators.
1406 (xop_table): Reference the above.
1407 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1408 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1409 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1410 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1412 2020-07-06 Jan Beulich <jbeulich@suse.com>
1414 * i386-dis.c (EVEX_W_0F3838_P_1,
1415 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1416 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1417 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1418 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1419 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1420 (putop): Centralize management of last[]. Delete SAVE_LAST.
1421 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1422 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1423 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1424 * i386-dis-evex-prefix.h: here.
1426 2020-07-06 Jan Beulich <jbeulich@suse.com>
1428 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1429 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1430 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1431 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1433 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1434 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1435 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1436 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1437 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1438 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1439 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1440 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1441 these, respectively.
1442 * i386-dis-evex-len.h: Adjust comments.
1443 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1444 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1445 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1446 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1447 MOD_EVEX_0F385B_P_2_W_1 table entries.
1448 * i386-dis-evex-w.h: Reference mod_table[] for
1449 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1452 2020-07-06 Jan Beulich <jbeulich@suse.com>
1454 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1455 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1457 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1458 Likewise. Mark 256-bit entries invalid.
1460 2020-07-06 Jan Beulich <jbeulich@suse.com>
1462 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1463 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1464 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1465 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1466 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1467 PREFIX_EVEX_0F382B): Delete.
1468 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1469 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1470 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1471 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1472 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1474 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1475 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1476 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1477 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1479 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1480 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1481 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1482 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1483 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1484 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1485 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1486 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1487 PREFIX_EVEX_0F382B): Remove table entries.
1488 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1489 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1490 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1492 2020-07-06 Jan Beulich <jbeulich@suse.com>
1494 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1495 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1497 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1498 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1499 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1500 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1503 2020-07-06 Jan Beulich <jbeulich@suse.com>
1505 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1506 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1507 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1508 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1509 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1510 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1511 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1512 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1513 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1516 2020-07-06 Jan Beulich <jbeulich@suse.com>
1518 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1519 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1520 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1522 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1524 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1526 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1528 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1530 2020-07-06 Jan Beulich <jbeulich@suse.com>
1532 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1533 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1534 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1535 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1536 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1537 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1538 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1539 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1540 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1541 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1542 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1543 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1544 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1545 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1546 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1547 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1548 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1549 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1550 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1551 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1552 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1553 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1554 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1555 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1556 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1557 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1558 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1559 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1560 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1561 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1562 (prefix_table): Add EXxEVexR to FMA table entries.
1563 (OP_Rounding): Move abort() invocation.
1564 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1565 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1566 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1567 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1568 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1569 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1570 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1571 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1572 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1573 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1575 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1576 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1577 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1578 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1579 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1580 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1581 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1582 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1583 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1584 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1585 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1586 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1587 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1588 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1589 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1590 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1591 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1592 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1593 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1594 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1595 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1596 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1597 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1598 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1599 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1600 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1601 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1602 Delete table entries.
1603 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1604 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1605 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1608 2020-07-06 Jan Beulich <jbeulich@suse.com>
1610 * i386-dis.c (EXqScalarS): Delete.
1611 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1612 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1614 2020-07-06 Jan Beulich <jbeulich@suse.com>
1616 * i386-dis.c (safe-ctype.h): Include.
1617 (EXdScalar, EXqScalar): Delete.
1618 (d_scalar_mode, q_scalar_mode): Delete.
1619 (prefix_table, vex_len_table): Use EXxmm_md in place of
1620 EXdScalar and EXxmm_mq in place of EXqScalar.
1621 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1622 d_scalar_mode and q_scalar_mode.
1623 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1624 (vmovsd): Use EXxmm_mq.
1626 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1629 * arc-dis.c: Fix spelling mistake.
1630 * po/opcodes.pot: Regenerate.
1632 2020-07-06 Nick Clifton <nickc@redhat.com>
1634 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1635 * po/uk.po: Updated Ukranian translation.
1637 2020-07-04 Nick Clifton <nickc@redhat.com>
1639 * configure: Regenerate.
1640 * po/opcodes.pot: Regenerate.
1642 2020-07-04 Nick Clifton <nickc@redhat.com>
1644 Binutils 2.35 branch created.
1646 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1648 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1649 * i386-opc.h (VexSwapSources): New.
1650 (i386_opcode_modifier): Add vexswapsources.
1651 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1652 with two source operands swapped.
1653 * i386-tbl.h: Regenerated.
1655 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1657 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1658 unprivileged CSR can also be initialized.
1660 2020-06-29 Alan Modra <amodra@gmail.com>
1662 * arm-dis.c: Use C style comments.
1663 * cr16-opc.c: Likewise.
1664 * ft32-dis.c: Likewise.
1665 * moxie-opc.c: Likewise.
1666 * tic54x-dis.c: Likewise.
1667 * s12z-opc.c: Remove useless comment.
1668 * xgate-dis.c: Likewise.
1670 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1672 * i386-opc.tbl: Add a blank line.
1674 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1676 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1677 (VecSIB128): Renamed to ...
1679 (VecSIB256): Renamed to ...
1681 (VecSIB512): Renamed to ...
1683 (VecSIB): Renamed to ...
1685 (i386_opcode_modifier): Replace vecsib with sib.
1686 * i386-opc.tbl (VecSIB128): New.
1687 (VecSIB256): Likewise.
1688 (VecSIB512): Likewise.
1689 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1690 and VecSIB512, respectively.
1692 2020-06-26 Jan Beulich <jbeulich@suse.com>
1694 * i386-dis.c: Adjust description of I macro.
1695 (x86_64_table): Drop use of I.
1696 (float_mem): Replace use of I.
1697 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1699 2020-06-26 Jan Beulich <jbeulich@suse.com>
1701 * i386-dis.c: (print_insn): Avoid straight assignment to
1702 priv.orig_sizeflag when processing -M sub-options.
1704 2020-06-25 Jan Beulich <jbeulich@suse.com>
1706 * i386-dis.c: Adjust description of J macro.
1707 (dis386, x86_64_table, mod_table): Replace J.
1708 (putop): Remove handling of J.
1710 2020-06-25 Jan Beulich <jbeulich@suse.com>
1712 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1714 2020-06-25 Jan Beulich <jbeulich@suse.com>
1716 * i386-dis.c: Adjust description of "LQ" macro.
1717 (dis386_twobyte): Use LQ for sysret.
1718 (putop): Adjust handling of LQ.
1720 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1722 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1723 * riscv-dis.c: Include elfxx-riscv.h.
1725 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1727 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1729 2020-06-17 Lili Cui <lili.cui@intel.com>
1731 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1733 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1736 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1737 * i386-opc.tbl: Likewise.
1738 * i386-tbl.h: Regenerated.
1740 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1742 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1744 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1746 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1747 (SR_CORE): Likewise.
1748 (SR_FEAT): Likewise.
1750 (SR_V8_1): Likewise.
1751 (SR_V8_2): Likewise.
1752 (SR_V8_3): Likewise.
1753 (SR_V8_4): Likewise.
1756 (SR_SSBS): Likewise.
1758 (SR_ID_PFR2): Likewise.
1759 (SR_PROFILE): Likewise.
1760 (SR_MEMTAG): Likewise.
1761 (SR_SCXTNUM): Likewise.
1762 (aarch64_sys_regs): Refactor to store feature information in the table.
1763 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1764 that now describe their own features.
1765 (aarch64_pstatefield_supported_p): Likewise.
1767 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1769 * i386-dis.c (prefix_table): Fix a typo in comments.
1771 2020-06-09 Jan Beulich <jbeulich@suse.com>
1773 * i386-dis.c (rex_ignored): Delete.
1774 (ckprefix): Drop rex_ignored initialization.
1775 (get_valid_dis386): Drop setting of rex_ignored.
1776 (print_insn): Drop checking of rex_ignored. Don't record data
1777 size prefix as used with VEX-and-alike encodings.
1779 2020-06-09 Jan Beulich <jbeulich@suse.com>
1781 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1782 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1783 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1784 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1785 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1786 VEX_0F12, and VEX_0F16.
1787 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1788 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1789 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1790 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1791 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1792 MOD_VEX_0F16_PREFIX_2 entries.
1794 2020-06-09 Jan Beulich <jbeulich@suse.com>
1796 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1797 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1798 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1799 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1800 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1801 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1802 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1803 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1804 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1805 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1806 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1807 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1808 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1809 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1810 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1811 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1812 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1813 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1814 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1815 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1816 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1817 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1818 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1819 EVEX_W_0FC6_P_2): Delete.
1820 (print_insn): Add EVEX.W vs embedded prefix consistency check
1821 to prefix validation.
1822 * i386-dis-evex.h (evex_table): Don't further descend for
1823 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1824 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1826 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1827 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1828 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1829 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1830 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1831 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1832 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1833 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1834 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1835 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1836 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1837 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1838 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1839 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1840 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1841 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1842 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1843 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1844 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1845 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1846 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1847 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1848 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1849 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1850 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1851 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1852 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1854 2020-06-09 Jan Beulich <jbeulich@suse.com>
1856 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1857 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1858 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1860 (print_insn): Drop pointless check against bad_opcode. Split
1861 prefix validation into legacy and VEX-and-alike parts.
1862 (putop): Re-work 'X' macro handling.
1864 2020-06-09 Jan Beulich <jbeulich@suse.com>
1866 * i386-dis.c (MOD_0F51): Rename to ...
1867 (MOD_0F50): ... this.
1869 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1871 * arm-dis.c (arm_opcodes): Add dfb.
1872 (thumb32_opcodes): Add dfb.
1874 2020-06-08 Jan Beulich <jbeulich@suse.com>
1876 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1878 2020-06-06 Alan Modra <amodra@gmail.com>
1880 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1882 2020-06-05 Alan Modra <amodra@gmail.com>
1884 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1885 size is large enough.
1887 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1889 * disassemble.c (disassemble_init_for_target): Set endian_code for
1891 * bpf-desc.c: Regenerate.
1892 * bpf-opc.c: Likewise.
1893 * bpf-dis.c: Likewise.
1895 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1897 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1898 (cgen_put_insn_value): Likewise.
1899 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1900 * cgen-dis.in (print_insn): Likewise.
1901 * cgen-ibld.in (insert_1): Likewise.
1902 (insert_1): Likewise.
1903 (insert_insn_normal): Likewise.
1904 (extract_1): Likewise.
1905 * bpf-dis.c: Regenerate.
1906 * bpf-ibld.c: Likewise.
1907 * bpf-ibld.c: Likewise.
1908 * cgen-dis.in: Likewise.
1909 * cgen-ibld.in: Likewise.
1910 * cgen-opc.c: Likewise.
1911 * epiphany-dis.c: Likewise.
1912 * epiphany-ibld.c: Likewise.
1913 * fr30-dis.c: Likewise.
1914 * fr30-ibld.c: Likewise.
1915 * frv-dis.c: Likewise.
1916 * frv-ibld.c: Likewise.
1917 * ip2k-dis.c: Likewise.
1918 * ip2k-ibld.c: Likewise.
1919 * iq2000-dis.c: Likewise.
1920 * iq2000-ibld.c: Likewise.
1921 * lm32-dis.c: Likewise.
1922 * lm32-ibld.c: Likewise.
1923 * m32c-dis.c: Likewise.
1924 * m32c-ibld.c: Likewise.
1925 * m32r-dis.c: Likewise.
1926 * m32r-ibld.c: Likewise.
1927 * mep-dis.c: Likewise.
1928 * mep-ibld.c: Likewise.
1929 * mt-dis.c: Likewise.
1930 * mt-ibld.c: Likewise.
1931 * or1k-dis.c: Likewise.
1932 * or1k-ibld.c: Likewise.
1933 * xc16x-dis.c: Likewise.
1934 * xc16x-ibld.c: Likewise.
1935 * xstormy16-dis.c: Likewise.
1936 * xstormy16-ibld.c: Likewise.
1938 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1940 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1941 (print_insn_): Handle instruction endian.
1942 * bpf-dis.c: Regenerate.
1943 * bpf-desc.c: Regenerate.
1944 * epiphany-dis.c: Likewise.
1945 * epiphany-desc.c: Likewise.
1946 * fr30-dis.c: Likewise.
1947 * fr30-desc.c: Likewise.
1948 * frv-dis.c: Likewise.
1949 * frv-desc.c: Likewise.
1950 * ip2k-dis.c: Likewise.
1951 * ip2k-desc.c: Likewise.
1952 * iq2000-dis.c: Likewise.
1953 * iq2000-desc.c: Likewise.
1954 * lm32-dis.c: Likewise.
1955 * lm32-desc.c: Likewise.
1956 * m32c-dis.c: Likewise.
1957 * m32c-desc.c: Likewise.
1958 * m32r-dis.c: Likewise.
1959 * m32r-desc.c: Likewise.
1960 * mep-dis.c: Likewise.
1961 * mep-desc.c: Likewise.
1962 * mt-dis.c: Likewise.
1963 * mt-desc.c: Likewise.
1964 * or1k-dis.c: Likewise.
1965 * or1k-desc.c: Likewise.
1966 * xc16x-dis.c: Likewise.
1967 * xc16x-desc.c: Likewise.
1968 * xstormy16-dis.c: Likewise.
1969 * xstormy16-desc.c: Likewise.
1971 2020-06-03 Nick Clifton <nickc@redhat.com>
1973 * po/sr.po: Updated Serbian translation.
1975 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1977 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1978 (riscv_get_priv_spec_class): Likewise.
1980 2020-06-01 Alan Modra <amodra@gmail.com>
1982 * bpf-desc.c: Regenerate.
1984 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1985 David Faust <david.faust@oracle.com>
1987 * bpf-desc.c: Regenerate.
1988 * bpf-opc.h: Likewise.
1989 * bpf-opc.c: Likewise.
1990 * bpf-dis.c: Likewise.
1992 2020-05-28 Alan Modra <amodra@gmail.com>
1994 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1997 2020-05-28 Alan Modra <amodra@gmail.com>
1999 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
2001 (print_insn_ns32k): Revert last change.
2003 2020-05-28 Nick Clifton <nickc@redhat.com>
2005 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
2008 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
2010 Fix extraction of signed constants in nios2 disassembler (again).
2012 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
2013 extractions of signed fields.
2015 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2017 * s390-opc.txt: Relocate vector load/store instructions with
2018 additional alignment parameter and change architecture level
2019 constraint from z14 to z13.
2021 2020-05-21 Alan Modra <amodra@gmail.com>
2023 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
2024 * sparc-dis.c: Likewise.
2025 * tic4x-dis.c: Likewise.
2026 * xtensa-dis.c: Likewise.
2027 * bpf-desc.c: Regenerate.
2028 * epiphany-desc.c: Regenerate.
2029 * fr30-desc.c: Regenerate.
2030 * frv-desc.c: Regenerate.
2031 * ip2k-desc.c: Regenerate.
2032 * iq2000-desc.c: Regenerate.
2033 * lm32-desc.c: Regenerate.
2034 * m32c-desc.c: Regenerate.
2035 * m32r-desc.c: Regenerate.
2036 * mep-asm.c: Regenerate.
2037 * mep-desc.c: Regenerate.
2038 * mt-desc.c: Regenerate.
2039 * or1k-desc.c: Regenerate.
2040 * xc16x-desc.c: Regenerate.
2041 * xstormy16-desc.c: Regenerate.
2043 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
2045 * riscv-opc.c (riscv_ext_version_table): The table used to store
2046 all information about the supported spec and the corresponding ISA
2047 versions. Currently, only Zicsr is supported to verify the
2048 correctness of Z sub extension settings. Others will be supported
2049 in the future patches.
2050 (struct isa_spec_t, isa_specs): List for all supported ISA spec
2051 classes and the corresponding strings.
2052 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
2053 spec class by giving a ISA spec string.
2054 * riscv-opc.c (struct priv_spec_t): New structure.
2055 (struct priv_spec_t priv_specs): List for all supported privilege spec
2056 classes and the corresponding strings.
2057 (riscv_get_priv_spec_class): New function. Get the corresponding
2058 privilege spec class by giving a spec string.
2059 (riscv_get_priv_spec_name): New function. Get the corresponding
2060 privilege spec string by giving a CSR version class.
2061 * riscv-dis.c: Updated since DECLARE_CSR is changed.
2062 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
2063 according to the chosen version. Build a hash table riscv_csr_hash to
2064 store the valid CSR for the chosen pirv verison. Dump the direct
2065 CSR address rather than it's name if it is invalid.
2066 (parse_riscv_dis_option_without_args): New function. Parse the options
2068 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
2069 parse the options without arguments first, and then handle the options
2070 with arguments. Add the new option -Mpriv-spec, which has argument.
2071 * riscv-dis.c (print_riscv_disassembler_options): Add description
2072 about the new OBJDUMP option.
2074 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
2076 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
2077 WC values on POWER10 sync, dcbf and wait instructions.
2078 (insert_pl, extract_pl): New functions.
2079 (L2OPT, LS, WC): Use insert_ls and extract_ls.
2080 (LS3): New , 3-bit L for sync.
2081 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
2082 (SC2, PL): New, 2-bit SC and PL for sync and wait.
2083 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
2084 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
2085 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
2086 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
2087 <wait>: Enable PL operand on POWER10.
2088 <dcbf>: Enable L3OPT operand on POWER10.
2089 <sync>: Enable SC2 operand on POWER10.
2091 2020-05-19 Stafford Horne <shorne@gmail.com>
2094 * or1k-asm.c: Regenerate.
2095 * or1k-desc.c: Regenerate.
2096 * or1k-desc.h: Regenerate.
2097 * or1k-dis.c: Regenerate.
2098 * or1k-ibld.c: Regenerate.
2099 * or1k-opc.c: Regenerate.
2100 * or1k-opc.h: Regenerate.
2101 * or1k-opinst.c: Regenerate.
2103 2020-05-11 Alan Modra <amodra@gmail.com>
2105 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
2108 2020-05-11 Alan Modra <amodra@gmail.com>
2110 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
2111 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
2113 2020-05-11 Alan Modra <amodra@gmail.com>
2115 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
2117 2020-05-11 Alan Modra <amodra@gmail.com>
2119 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
2120 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
2122 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2124 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
2127 2020-05-11 Alan Modra <amodra@gmail.com>
2129 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
2130 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
2131 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
2132 (prefix_opcodes): Add xxeval.
2134 2020-05-11 Alan Modra <amodra@gmail.com>
2136 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
2137 xxgenpcvwm, xxgenpcvdm.
2139 2020-05-11 Alan Modra <amodra@gmail.com>
2141 * ppc-opc.c (MP, VXVAM_MASK): Define.
2142 (VXVAPS_MASK): Use VXVA_MASK.
2143 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
2144 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
2145 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
2146 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
2148 2020-05-11 Alan Modra <amodra@gmail.com>
2149 Peter Bergner <bergner@linux.ibm.com>
2151 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
2153 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
2154 YMSK2, XA6a, XA6ap, XB6a entries.
2155 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
2156 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
2158 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
2159 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
2160 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
2161 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
2162 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
2163 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
2164 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
2165 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
2166 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
2167 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
2168 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
2169 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
2170 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
2171 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
2173 2020-05-11 Alan Modra <amodra@gmail.com>
2175 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
2176 (insert_xts, extract_xts): New functions.
2177 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
2178 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
2179 (VXRC_MASK, VXSH_MASK): Define.
2180 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
2181 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
2182 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
2183 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
2184 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
2185 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
2186 xxblendvh, xxblendvw, xxblendvd, xxpermx.
2188 2020-05-11 Alan Modra <amodra@gmail.com>
2190 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
2191 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
2192 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
2193 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
2194 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
2196 2020-05-11 Alan Modra <amodra@gmail.com>
2198 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
2199 (XTP, DQXP, DQXP_MASK): Define.
2200 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
2201 (prefix_opcodes): Add plxvp and pstxvp.
2203 2020-05-11 Alan Modra <amodra@gmail.com>
2205 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
2206 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
2207 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
2209 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2211 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
2213 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2215 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
2217 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
2219 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2221 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
2223 2020-05-11 Alan Modra <amodra@gmail.com>
2225 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
2227 2020-05-11 Alan Modra <amodra@gmail.com>
2229 * ppc-dis.c (ppc_opts): Add "power10" entry.
2230 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
2231 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
2233 2020-05-11 Nick Clifton <nickc@redhat.com>
2235 * po/fr.po: Updated French translation.
2237 2020-04-30 Alex Coplan <alex.coplan@arm.com>
2239 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
2240 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
2241 (operand_general_constraint_met_p): validate
2242 AARCH64_OPND_UNDEFINED.
2243 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
2245 * aarch64-asm-2.c: Regenerated.
2246 * aarch64-dis-2.c: Regenerated.
2247 * aarch64-opc-2.c: Regenerated.
2249 2020-04-29 Nick Clifton <nickc@redhat.com>
2252 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
2255 2020-04-29 Nick Clifton <nickc@redhat.com>
2257 * po/sv.po: Updated Swedish translation.
2259 2020-04-29 Nick Clifton <nickc@redhat.com>
2262 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
2263 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
2264 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
2267 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
2270 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
2271 cmpi only on m68020up and cpu32.
2273 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2275 * aarch64-asm.c (aarch64_ins_none): New.
2276 * aarch64-asm.h (ins_none): New declaration.
2277 * aarch64-dis.c (aarch64_ext_none): New.
2278 * aarch64-dis.h (ext_none): New declaration.
2279 * aarch64-opc.c (aarch64_print_operand): Update case for
2280 AARCH64_OPND_BARRIER_PSB.
2281 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2282 (AARCH64_OPERANDS): Update inserter/extracter for
2283 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2284 * aarch64-asm-2.c: Regenerated.
2285 * aarch64-dis-2.c: Regenerated.
2286 * aarch64-opc-2.c: Regenerated.
2288 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2290 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2291 (aarch64_feature_ras, RAS): Likewise.
2292 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2293 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2294 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2295 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2296 * aarch64-asm-2.c: Regenerated.
2297 * aarch64-dis-2.c: Regenerated.
2298 * aarch64-opc-2.c: Regenerated.
2300 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
2302 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2303 (print_insn_neon): Support disassembly of conditional
2306 2020-02-16 David Faust <david.faust@oracle.com>
2308 * bpf-desc.c: Regenerate.
2309 * bpf-desc.h: Likewise.
2310 * bpf-opc.c: Regenerate.
2311 * bpf-opc.h: Likewise.
2313 2020-04-07 Lili Cui <lili.cui@intel.com>
2315 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2316 (prefix_table): New instructions (see prefixes above).
2317 (rm_table): Likewise
2318 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2319 CPU_ANY_TSXLDTRK_FLAGS.
2320 (cpu_flags): Add CpuTSXLDTRK.
2321 * i386-opc.h (enum): Add CpuTSXLDTRK.
2322 (i386_cpu_flags): Add cputsxldtrk.
2323 * i386-opc.tbl: Add XSUSPLDTRK insns.
2324 * i386-init.h: Regenerate.
2325 * i386-tbl.h: Likewise.
2327 2020-04-02 Lili Cui <lili.cui@intel.com>
2329 * i386-dis.c (prefix_table): New instructions serialize.
2330 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2331 CPU_ANY_SERIALIZE_FLAGS.
2332 (cpu_flags): Add CpuSERIALIZE.
2333 * i386-opc.h (enum): Add CpuSERIALIZE.
2334 (i386_cpu_flags): Add cpuserialize.
2335 * i386-opc.tbl: Add SERIALIZE insns.
2336 * i386-init.h: Regenerate.
2337 * i386-tbl.h: Likewise.
2339 2020-03-26 Alan Modra <amodra@gmail.com>
2341 * disassemble.h (opcodes_assert): Declare.
2342 (OPCODES_ASSERT): Define.
2343 * disassemble.c: Don't include assert.h. Include opintl.h.
2344 (opcodes_assert): New function.
2345 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2346 (bfd_h8_disassemble): Reduce size of data array. Correctly
2347 calculate maxlen. Omit insn decoding when insn length exceeds
2348 maxlen. Exit from nibble loop when looking for E, before
2349 accessing next data byte. Move processing of E outside loop.
2350 Replace tests of maxlen in loop with assertions.
2352 2020-03-26 Alan Modra <amodra@gmail.com>
2354 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
2356 2020-03-25 Alan Modra <amodra@gmail.com>
2358 * z80-dis.c (suffix): Init mybuf.
2360 2020-03-22 Alan Modra <amodra@gmail.com>
2362 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2363 successflly read from section.
2365 2020-03-22 Alan Modra <amodra@gmail.com>
2367 * arc-dis.c (find_format): Use ISO C string concatenation rather
2368 than line continuation within a string. Don't access needs_limm
2369 before testing opcode != NULL.
2371 2020-03-22 Alan Modra <amodra@gmail.com>
2373 * ns32k-dis.c (print_insn_arg): Update comment.
2374 (print_insn_ns32k): Reduce size of index_offset array, and
2375 initialize, passing -1 to print_insn_arg for args that are not
2376 an index. Don't exit arg loop early. Abort on bad arg number.
2378 2020-03-22 Alan Modra <amodra@gmail.com>
2380 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2381 * s12z-opc.c: Formatting.
2382 (operands_f): Return an int.
2383 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2384 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2385 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2386 (exg_sex_discrim): Likewise.
2387 (create_immediate_operand, create_bitfield_operand),
2388 (create_register_operand_with_size, create_register_all_operand),
2389 (create_register_all16_operand, create_simple_memory_operand),
2390 (create_memory_operand, create_memory_auto_operand): Don't
2391 segfault on malloc failure.
2392 (z_ext24_decode): Return an int status, negative on fail, zero
2394 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2395 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2396 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2397 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2398 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2399 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2400 (loop_primitive_decode, shift_decode, psh_pul_decode),
2401 (bit_field_decode): Similarly.
2402 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
2403 to return value, update callers.
2404 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2405 Don't segfault on NULL operand.
2406 (decode_operation): Return OP_INVALID on first fail.
2407 (decode_s12z): Check all reads, returning -1 on fail.
2409 2020-03-20 Alan Modra <amodra@gmail.com>
2411 * metag-dis.c (print_insn_metag): Don't ignore status from
2414 2020-03-20 Alan Modra <amodra@gmail.com>
2416 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2417 Initialize parts of buffer not written when handling a possible
2418 2-byte insn at end of section. Don't attempt decoding of such
2419 an insn by the 4-byte machinery.
2421 2020-03-20 Alan Modra <amodra@gmail.com>
2423 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2424 partially filled buffer. Prevent lookup of 4-byte insns when
2425 only VLE 2-byte insns are possible due to section size. Print
2426 ".word" rather than ".long" for 2-byte leftovers.
2428 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2431 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2433 2020-03-13 Jan Beulich <jbeulich@suse.com>
2435 * i386-dis.c (X86_64_0D): Rename to ...
2436 (X86_64_0E): ... this.
2438 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2440 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2441 * Makefile.in: Regenerated.
2443 2020-03-09 Jan Beulich <jbeulich@suse.com>
2445 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2447 * i386-tbl.h: Re-generate.
2449 2020-03-09 Jan Beulich <jbeulich@suse.com>
2451 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2452 vprot*, vpsha*, and vpshl*.
2453 * i386-tbl.h: Re-generate.
2455 2020-03-09 Jan Beulich <jbeulich@suse.com>
2457 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2458 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2459 * i386-tbl.h: Re-generate.
2461 2020-03-09 Jan Beulich <jbeulich@suse.com>
2463 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2464 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2465 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2466 * i386-tbl.h: Re-generate.
2468 2020-03-09 Jan Beulich <jbeulich@suse.com>
2470 * i386-gen.c (struct template_arg, struct template_instance,
2471 struct template_param, struct template, templates,
2472 parse_template, expand_templates): New.
2473 (process_i386_opcodes): Various local variables moved to
2474 expand_templates. Call parse_template and expand_templates.
2475 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2476 * i386-tbl.h: Re-generate.
2478 2020-03-06 Jan Beulich <jbeulich@suse.com>
2480 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2481 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2482 register and memory source templates. Replace VexW= by VexW*
2484 * i386-tbl.h: Re-generate.
2486 2020-03-06 Jan Beulich <jbeulich@suse.com>
2488 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2489 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2490 * i386-tbl.h: Re-generate.
2492 2020-03-06 Jan Beulich <jbeulich@suse.com>
2494 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2495 * i386-tbl.h: Re-generate.
2497 2020-03-06 Jan Beulich <jbeulich@suse.com>
2499 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2500 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2501 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2502 VexW0 on SSE2AVX variants.
2503 (vmovq): Drop NoRex64 from XMM/XMM variants.
2504 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2505 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2506 applicable use VexW0.
2507 * i386-tbl.h: Re-generate.
2509 2020-03-06 Jan Beulich <jbeulich@suse.com>
2511 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2512 * i386-opc.h (Rex64): Delete.
2513 (struct i386_opcode_modifier): Remove rex64 field.
2514 * i386-opc.tbl (crc32): Drop Rex64.
2515 Replace Rex64 with Size64 everywhere else.
2516 * i386-tbl.h: Re-generate.
2518 2020-03-06 Jan Beulich <jbeulich@suse.com>
2520 * i386-dis.c (OP_E_memory): Exclude recording of used address
2521 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2522 addressed memory operands for MPX insns.
2524 2020-03-06 Jan Beulich <jbeulich@suse.com>
2526 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2527 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2528 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2529 (ptwrite): Split into non-64-bit and 64-bit forms.
2530 * i386-tbl.h: Re-generate.
2532 2020-03-06 Jan Beulich <jbeulich@suse.com>
2534 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2536 * i386-tbl.h: Re-generate.
2538 2020-03-04 Jan Beulich <jbeulich@suse.com>
2540 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2541 (prefix_table): Move vmmcall here. Add vmgexit.
2542 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2543 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2544 (cpu_flags): Add CpuSEV_ES entry.
2545 * i386-opc.h (CpuSEV_ES): New.
2546 (union i386_cpu_flags): Add cpusev_es field.
2547 * i386-opc.tbl (vmgexit): New.
2548 * i386-init.h, i386-tbl.h: Re-generate.
2550 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2552 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2554 * i386-opc.h (IGNORESIZE): New.
2555 (DEFAULTSIZE): Likewise.
2556 (IgnoreSize): Removed.
2557 (DefaultSize): Likewise.
2558 (MnemonicSize): New.
2559 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2561 * i386-opc.tbl (IgnoreSize): New.
2562 (DefaultSize): Likewise.
2563 * i386-tbl.h: Regenerated.
2565 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2568 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2571 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2574 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2575 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2576 * i386-tbl.h: Regenerated.
2578 2020-02-26 Alan Modra <amodra@gmail.com>
2580 * aarch64-asm.c: Indent labels correctly.
2581 * aarch64-dis.c: Likewise.
2582 * aarch64-gen.c: Likewise.
2583 * aarch64-opc.c: Likewise.
2584 * alpha-dis.c: Likewise.
2585 * i386-dis.c: Likewise.
2586 * nds32-asm.c: Likewise.
2587 * nfp-dis.c: Likewise.
2588 * visium-dis.c: Likewise.
2590 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2592 * arc-regs.h (int_vector_base): Make it available for all ARC
2595 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2597 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2600 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2602 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2603 c.mv/c.li if rs1 is zero.
2605 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2607 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2608 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2610 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2611 * i386-opc.h (CpuABM): Removed.
2613 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2614 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2615 popcnt. Remove CpuABM from lzcnt.
2616 * i386-init.h: Regenerated.
2617 * i386-tbl.h: Likewise.
2619 2020-02-17 Jan Beulich <jbeulich@suse.com>
2621 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2622 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2623 VexW1 instead of open-coding them.
2624 * i386-tbl.h: Re-generate.
2626 2020-02-17 Jan Beulich <jbeulich@suse.com>
2628 * i386-opc.tbl (AddrPrefixOpReg): Define.
2629 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2630 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2631 templates. Drop NoRex64.
2632 * i386-tbl.h: Re-generate.
2634 2020-02-17 Jan Beulich <jbeulich@suse.com>
2637 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2638 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2639 into Intel syntax instance (with Unpsecified) and AT&T one
2641 (vcvtneps2bf16): Likewise, along with folding the two so far
2643 * i386-tbl.h: Re-generate.
2645 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2647 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2648 CPU_ANY_SSE4A_FLAGS.
2650 2020-02-17 Alan Modra <amodra@gmail.com>
2652 * i386-gen.c (cpu_flag_init): Correct last change.
2654 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2656 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2659 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2661 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2664 2020-02-14 Jan Beulich <jbeulich@suse.com>
2667 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2668 destination for Cpu64-only variant.
2669 (movzx): Fold patterns.
2670 * i386-tbl.h: Re-generate.
2672 2020-02-13 Jan Beulich <jbeulich@suse.com>
2674 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2675 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2676 CPU_ANY_SSE4_FLAGS entry.
2677 * i386-init.h: Re-generate.
2679 2020-02-12 Jan Beulich <jbeulich@suse.com>
2681 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2682 with Unspecified, making the present one AT&T syntax only.
2683 * i386-tbl.h: Re-generate.
2685 2020-02-12 Jan Beulich <jbeulich@suse.com>
2687 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2688 * i386-tbl.h: Re-generate.
2690 2020-02-12 Jan Beulich <jbeulich@suse.com>
2693 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2694 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2695 Amd64 and Intel64 templates.
2696 (call, jmp): Likewise for far indirect variants. Dro
2698 * i386-tbl.h: Re-generate.
2700 2020-02-11 Jan Beulich <jbeulich@suse.com>
2702 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2703 * i386-opc.h (ShortForm): Delete.
2704 (struct i386_opcode_modifier): Remove shortform field.
2705 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2706 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2707 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2708 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2710 * i386-tbl.h: Re-generate.
2712 2020-02-11 Jan Beulich <jbeulich@suse.com>
2714 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2715 fucompi): Drop ShortForm from operand-less templates.
2716 * i386-tbl.h: Re-generate.
2718 2020-02-11 Alan Modra <amodra@gmail.com>
2720 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2721 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2722 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2723 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2724 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2726 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2728 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2729 (cde_opcodes): Add VCX* instructions.
2731 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2732 Matthew Malcomson <matthew.malcomson@arm.com>
2734 * arm-dis.c (struct cdeopcode32): New.
2735 (CDE_OPCODE): New macro.
2736 (cde_opcodes): New disassembly table.
2737 (regnames): New option to table.
2738 (cde_coprocs): New global variable.
2739 (print_insn_cde): New
2740 (print_insn_thumb32): Use print_insn_cde.
2741 (parse_arm_disassembler_options): Parse coprocN args.
2743 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2746 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2748 * i386-opc.h (AMD64): Removed.
2749 (Intel64): Likewose.
2751 (INTEL64): Likewise.
2752 (INTEL64ONLY): Likewise.
2753 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2754 * i386-opc.tbl (Amd64): New.
2755 (Intel64): Likewise.
2756 (Intel64Only): Likewise.
2757 Replace AMD64 with Amd64. Update sysenter/sysenter with
2758 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2759 * i386-tbl.h: Regenerated.
2761 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2764 * z80-dis.c: Add support for GBZ80 opcodes.
2766 2020-02-04 Alan Modra <amodra@gmail.com>
2768 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2770 2020-02-03 Alan Modra <amodra@gmail.com>
2772 * m32c-ibld.c: Regenerate.
2774 2020-02-01 Alan Modra <amodra@gmail.com>
2776 * frv-ibld.c: Regenerate.
2778 2020-01-31 Jan Beulich <jbeulich@suse.com>
2780 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2781 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2782 (OP_E_memory): Replace xmm_mdq_mode case label by
2783 vex_scalar_w_dq_mode one.
2784 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2786 2020-01-31 Jan Beulich <jbeulich@suse.com>
2788 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2789 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2790 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2791 (intel_operand_size): Drop vex_w_dq_mode case label.
2793 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2795 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2796 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2798 2020-01-30 Alan Modra <amodra@gmail.com>
2800 * m32c-ibld.c: Regenerate.
2802 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2804 * bpf-opc.c: Regenerate.
2806 2020-01-30 Jan Beulich <jbeulich@suse.com>
2808 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2809 (dis386): Use them to replace C2/C3 table entries.
2810 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2811 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2812 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2813 * i386-tbl.h: Re-generate.
2815 2020-01-30 Jan Beulich <jbeulich@suse.com>
2817 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2819 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2821 * i386-tbl.h: Re-generate.
2823 2020-01-30 Alan Modra <amodra@gmail.com>
2825 * tic4x-dis.c (tic4x_dp): Make unsigned.
2827 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2828 Jan Beulich <jbeulich@suse.com>
2831 * i386-dis.c (MOVSXD_Fixup): New function.
2832 (movsxd_mode): New enum.
2833 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2834 (intel_operand_size): Handle movsxd_mode.
2835 (OP_E_register): Likewise.
2837 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2838 register on movsxd. Add movsxd with 16-bit destination register
2839 for AMD64 and Intel64 ISAs.
2840 * i386-tbl.h: Regenerated.
2842 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2845 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2846 * aarch64-asm-2.c: Regenerate
2847 * aarch64-dis-2.c: Likewise.
2848 * aarch64-opc-2.c: Likewise.
2850 2020-01-21 Jan Beulich <jbeulich@suse.com>
2852 * i386-opc.tbl (sysret): Drop DefaultSize.
2853 * i386-tbl.h: Re-generate.
2855 2020-01-21 Jan Beulich <jbeulich@suse.com>
2857 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2859 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2860 * i386-tbl.h: Re-generate.
2862 2020-01-20 Nick Clifton <nickc@redhat.com>
2864 * po/de.po: Updated German translation.
2865 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2866 * po/uk.po: Updated Ukranian translation.
2868 2020-01-20 Alan Modra <amodra@gmail.com>
2870 * hppa-dis.c (fput_const): Remove useless cast.
2872 2020-01-20 Alan Modra <amodra@gmail.com>
2874 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2876 2020-01-18 Nick Clifton <nickc@redhat.com>
2878 * configure: Regenerate.
2879 * po/opcodes.pot: Regenerate.
2881 2020-01-18 Nick Clifton <nickc@redhat.com>
2883 Binutils 2.34 branch created.
2885 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2887 * opintl.h: Fix spelling error (seperate).
2889 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2891 * i386-opc.tbl: Add {vex} pseudo prefix.
2892 * i386-tbl.h: Regenerated.
2894 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2897 * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2898 (neon_opcodes): Likewise.
2899 (select_arm_features): Make sure we enable MVE bits when selecting
2900 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2903 2020-01-16 Jan Beulich <jbeulich@suse.com>
2905 * i386-opc.tbl: Drop stale comment from XOP section.
2907 2020-01-16 Jan Beulich <jbeulich@suse.com>
2909 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2910 (extractps): Add VexWIG to SSE2AVX forms.
2911 * i386-tbl.h: Re-generate.
2913 2020-01-16 Jan Beulich <jbeulich@suse.com>
2915 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2916 Size64 from and use VexW1 on SSE2AVX forms.
2917 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2918 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2919 * i386-tbl.h: Re-generate.
2921 2020-01-15 Alan Modra <amodra@gmail.com>
2923 * tic4x-dis.c (tic4x_version): Make unsigned long.
2924 (optab, optab_special, registernames): New file scope vars.
2925 (tic4x_print_register): Set up registernames rather than
2926 malloc'd registertable.
2927 (tic4x_disassemble): Delete optable and optable_special. Use
2928 optab and optab_special instead. Throw away old optab,
2929 optab_special and registernames when info->mach changes.
2931 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2934 * z80-dis.c (suffix): Use .db instruction to generate double
2937 2020-01-14 Alan Modra <amodra@gmail.com>
2939 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2940 values to unsigned before shifting.
2942 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2944 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2946 (print_insn_thumb16, print_insn_thumb32): Likewise.
2947 (print_insn): Initialize the insn info.
2948 * i386-dis.c (print_insn): Initialize the insn info fields, and
2951 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
2953 * arc-opc.c (C_NE): Make it required.
2955 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
2957 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2958 reserved register name.
2960 2020-01-13 Alan Modra <amodra@gmail.com>
2962 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2963 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2965 2020-01-13 Alan Modra <amodra@gmail.com>
2967 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2968 result of wasm_read_leb128 in a uint64_t and check that bits
2969 are not lost when copying to other locals. Use uint32_t for
2970 most locals. Use PRId64 when printing int64_t.
2972 2020-01-13 Alan Modra <amodra@gmail.com>
2974 * score-dis.c: Formatting.
2975 * score7-dis.c: Formatting.
2977 2020-01-13 Alan Modra <amodra@gmail.com>
2979 * score-dis.c (print_insn_score48): Use unsigned variables for
2980 unsigned values. Don't left shift negative values.
2981 (print_insn_score32): Likewise.
2982 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2984 2020-01-13 Alan Modra <amodra@gmail.com>
2986 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2988 2020-01-13 Alan Modra <amodra@gmail.com>
2990 * fr30-ibld.c: Regenerate.
2992 2020-01-13 Alan Modra <amodra@gmail.com>
2994 * xgate-dis.c (print_insn): Don't left shift signed value.
2995 (ripBits): Formatting, use 1u.
2997 2020-01-10 Alan Modra <amodra@gmail.com>
2999 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
3000 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
3002 2020-01-10 Alan Modra <amodra@gmail.com>
3004 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
3005 and XRREG value earlier to avoid a shift with negative exponent.
3006 * m10200-dis.c (disassemble): Similarly.
3008 2020-01-09 Nick Clifton <nickc@redhat.com>
3011 * z80-dis.c (ld_ii_ii): Use correct cast.
3013 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
3016 * z80-dis.c (ld_ii_ii): Use character constant when checking
3019 2020-01-09 Jan Beulich <jbeulich@suse.com>
3021 * i386-dis.c (SEP_Fixup): New.
3023 (dis386_twobyte): Use it for sysenter/sysexit.
3024 (enum x86_64_isa): Change amd64 enumerator to value 1.
3025 (OP_J): Compare isa64 against intel64 instead of amd64.
3026 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
3028 * i386-tbl.h: Re-generate.
3030 2020-01-08 Alan Modra <amodra@gmail.com>
3032 * z8k-dis.c: Include libiberty.h
3033 (instr_data_s): Make max_fetched unsigned.
3034 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
3035 Don't exceed byte_info bounds.
3036 (output_instr): Make num_bytes unsigned.
3037 (unpack_instr): Likewise for nibl_count and loop.
3038 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
3040 * z8k-opc.h: Regenerate.
3042 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
3044 * arc-tbl.h (llock): Use 'LLOCK' as class.
3046 (scond): Use 'SCOND' as class.
3048 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
3051 2020-01-06 Alan Modra <amodra@gmail.com>
3053 * m32c-ibld.c: Regenerate.
3055 2020-01-06 Alan Modra <amodra@gmail.com>
3058 * z80-dis.c (suffix): Don't use a local struct buffer copy.
3059 Peek at next byte to prevent recursion on repeated prefix bytes.
3060 Ensure uninitialised "mybuf" is not accessed.
3061 (print_insn_z80): Don't zero n_fetch and n_used here,..
3062 (print_insn_z80_buf): ..do it here instead.
3064 2020-01-04 Alan Modra <amodra@gmail.com>
3066 * m32r-ibld.c: Regenerate.
3068 2020-01-04 Alan Modra <amodra@gmail.com>
3070 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
3072 2020-01-04 Alan Modra <amodra@gmail.com>
3074 * crx-dis.c (match_opcode): Avoid shift left of signed value.
3076 2020-01-04 Alan Modra <amodra@gmail.com>
3078 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
3080 2020-01-03 Jan Beulich <jbeulich@suse.com>
3082 * aarch64-tbl.h (aarch64_opcode_table): Use
3083 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
3085 2020-01-03 Jan Beulich <jbeulich@suse.com>
3087 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
3088 forms of SUDOT and USDOT.
3090 2020-01-03 Jan Beulich <jbeulich@suse.com>
3092 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
3094 * aarch64-dis-2.c: Re-generate.
3096 2020-01-03 Jan Beulich <jbeulich@suse.com>
3098 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
3100 * aarch64-dis-2.c: Re-generate.
3102 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
3104 * z80-dis.c: Add support for eZ80 and Z80 instructions.
3106 2020-01-01 Alan Modra <amodra@gmail.com>
3108 Update year range in copyright notice of all files.
3110 For older changes see ChangeLog-2019
3112 Copyright (C) 2020 Free Software Foundation, Inc.
3114 Copying and distribution of this file, with or without modification,
3115 are permitted in any medium without royalty provided the copyright
3116 notice and this notice are preserved.
3122 version-control: never