1 2020-04-29 Nick Clifton <nickc@redhat.com>
4 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
5 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
6 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
9 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
12 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
13 cmpi only on m68020up and cpu32.
15 2020-04-20 Sudakshina Das <sudi.das@arm.com>
17 * aarch64-asm.c (aarch64_ins_none): New.
18 * aarch64-asm.h (ins_none): New declaration.
19 * aarch64-dis.c (aarch64_ext_none): New.
20 * aarch64-dis.h (ext_none): New declaration.
21 * aarch64-opc.c (aarch64_print_operand): Update case for
22 AARCH64_OPND_BARRIER_PSB.
23 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
24 (AARCH64_OPERANDS): Update inserter/extracter for
25 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
26 * aarch64-asm-2.c: Regenerated.
27 * aarch64-dis-2.c: Regenerated.
28 * aarch64-opc-2.c: Regenerated.
30 2020-04-20 Sudakshina Das <sudi.das@arm.com>
32 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
33 (aarch64_feature_ras, RAS): Likewise.
34 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
35 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
36 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
37 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
38 * aarch64-asm-2.c: Regenerated.
39 * aarch64-dis-2.c: Regenerated.
40 * aarch64-opc-2.c: Regenerated.
42 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
44 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
45 (print_insn_neon): Support disassembly of conditional
48 2020-02-16 David Faust <david.faust@oracle.com>
50 * bpf-desc.c: Regenerate.
51 * bpf-desc.h: Likewise.
52 * bpf-opc.c: Regenerate.
53 * bpf-opc.h: Likewise.
55 2020-04-07 Lili Cui <lili.cui@intel.com>
57 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
58 (prefix_table): New instructions (see prefixes above).
60 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
61 CPU_ANY_TSXLDTRK_FLAGS.
62 (cpu_flags): Add CpuTSXLDTRK.
63 * i386-opc.h (enum): Add CpuTSXLDTRK.
64 (i386_cpu_flags): Add cputsxldtrk.
65 * i386-opc.tbl: Add XSUSPLDTRK insns.
66 * i386-init.h: Regenerate.
67 * i386-tbl.h: Likewise.
69 2020-04-02 Lili Cui <lili.cui@intel.com>
71 * i386-dis.c (prefix_table): New instructions serialize.
72 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
73 CPU_ANY_SERIALIZE_FLAGS.
74 (cpu_flags): Add CpuSERIALIZE.
75 * i386-opc.h (enum): Add CpuSERIALIZE.
76 (i386_cpu_flags): Add cpuserialize.
77 * i386-opc.tbl: Add SERIALIZE insns.
78 * i386-init.h: Regenerate.
79 * i386-tbl.h: Likewise.
81 2020-03-26 Alan Modra <amodra@gmail.com>
83 * disassemble.h (opcodes_assert): Declare.
84 (OPCODES_ASSERT): Define.
85 * disassemble.c: Don't include assert.h. Include opintl.h.
86 (opcodes_assert): New function.
87 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
88 (bfd_h8_disassemble): Reduce size of data array. Correctly
89 calculate maxlen. Omit insn decoding when insn length exceeds
90 maxlen. Exit from nibble loop when looking for E, before
91 accessing next data byte. Move processing of E outside loop.
92 Replace tests of maxlen in loop with assertions.
94 2020-03-26 Alan Modra <amodra@gmail.com>
96 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
98 2020-03-25 Alan Modra <amodra@gmail.com>
100 * z80-dis.c (suffix): Init mybuf.
102 2020-03-22 Alan Modra <amodra@gmail.com>
104 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
105 successflly read from section.
107 2020-03-22 Alan Modra <amodra@gmail.com>
109 * arc-dis.c (find_format): Use ISO C string concatenation rather
110 than line continuation within a string. Don't access needs_limm
111 before testing opcode != NULL.
113 2020-03-22 Alan Modra <amodra@gmail.com>
115 * ns32k-dis.c (print_insn_arg): Update comment.
116 (print_insn_ns32k): Reduce size of index_offset array, and
117 initialize, passing -1 to print_insn_arg for args that are not
118 an index. Don't exit arg loop early. Abort on bad arg number.
120 2020-03-22 Alan Modra <amodra@gmail.com>
122 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
123 * s12z-opc.c: Formatting.
124 (operands_f): Return an int.
125 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
126 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
127 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
128 (exg_sex_discrim): Likewise.
129 (create_immediate_operand, create_bitfield_operand),
130 (create_register_operand_with_size, create_register_all_operand),
131 (create_register_all16_operand, create_simple_memory_operand),
132 (create_memory_operand, create_memory_auto_operand): Don't
133 segfault on malloc failure.
134 (z_ext24_decode): Return an int status, negative on fail, zero
136 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
137 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
138 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
139 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
140 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
141 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
142 (loop_primitive_decode, shift_decode, psh_pul_decode),
143 (bit_field_decode): Similarly.
144 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
145 to return value, update callers.
146 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
147 Don't segfault on NULL operand.
148 (decode_operation): Return OP_INVALID on first fail.
149 (decode_s12z): Check all reads, returning -1 on fail.
151 2020-03-20 Alan Modra <amodra@gmail.com>
153 * metag-dis.c (print_insn_metag): Don't ignore status from
156 2020-03-20 Alan Modra <amodra@gmail.com>
158 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
159 Initialize parts of buffer not written when handling a possible
160 2-byte insn at end of section. Don't attempt decoding of such
161 an insn by the 4-byte machinery.
163 2020-03-20 Alan Modra <amodra@gmail.com>
165 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
166 partially filled buffer. Prevent lookup of 4-byte insns when
167 only VLE 2-byte insns are possible due to section size. Print
168 ".word" rather than ".long" for 2-byte leftovers.
170 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
173 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
175 2020-03-13 Jan Beulich <jbeulich@suse.com>
177 * i386-dis.c (X86_64_0D): Rename to ...
178 (X86_64_0E): ... this.
180 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
182 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
183 * Makefile.in: Regenerated.
185 2020-03-09 Jan Beulich <jbeulich@suse.com>
187 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
189 * i386-tbl.h: Re-generate.
191 2020-03-09 Jan Beulich <jbeulich@suse.com>
193 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
194 vprot*, vpsha*, and vpshl*.
195 * i386-tbl.h: Re-generate.
197 2020-03-09 Jan Beulich <jbeulich@suse.com>
199 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
200 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
201 * i386-tbl.h: Re-generate.
203 2020-03-09 Jan Beulich <jbeulich@suse.com>
205 * i386-gen.c (set_bitfield): Ignore zero-length field names.
206 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
207 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
208 * i386-tbl.h: Re-generate.
210 2020-03-09 Jan Beulich <jbeulich@suse.com>
212 * i386-gen.c (struct template_arg, struct template_instance,
213 struct template_param, struct template, templates,
214 parse_template, expand_templates): New.
215 (process_i386_opcodes): Various local variables moved to
216 expand_templates. Call parse_template and expand_templates.
217 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
218 * i386-tbl.h: Re-generate.
220 2020-03-06 Jan Beulich <jbeulich@suse.com>
222 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
223 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
224 register and memory source templates. Replace VexW= by VexW*
226 * i386-tbl.h: Re-generate.
228 2020-03-06 Jan Beulich <jbeulich@suse.com>
230 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
231 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
232 * i386-tbl.h: Re-generate.
234 2020-03-06 Jan Beulich <jbeulich@suse.com>
236 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
237 * i386-tbl.h: Re-generate.
239 2020-03-06 Jan Beulich <jbeulich@suse.com>
241 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
242 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
243 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
244 VexW0 on SSE2AVX variants.
245 (vmovq): Drop NoRex64 from XMM/XMM variants.
246 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
247 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
248 applicable use VexW0.
249 * i386-tbl.h: Re-generate.
251 2020-03-06 Jan Beulich <jbeulich@suse.com>
253 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
254 * i386-opc.h (Rex64): Delete.
255 (struct i386_opcode_modifier): Remove rex64 field.
256 * i386-opc.tbl (crc32): Drop Rex64.
257 Replace Rex64 with Size64 everywhere else.
258 * i386-tbl.h: Re-generate.
260 2020-03-06 Jan Beulich <jbeulich@suse.com>
262 * i386-dis.c (OP_E_memory): Exclude recording of used address
263 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
264 addressed memory operands for MPX insns.
266 2020-03-06 Jan Beulich <jbeulich@suse.com>
268 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
269 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
270 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
271 (ptwrite): Split into non-64-bit and 64-bit forms.
272 * i386-tbl.h: Re-generate.
274 2020-03-06 Jan Beulich <jbeulich@suse.com>
276 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
278 * i386-tbl.h: Re-generate.
280 2020-03-04 Jan Beulich <jbeulich@suse.com>
282 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
283 (prefix_table): Move vmmcall here. Add vmgexit.
284 (rm_table): Replace vmmcall entry by prefix_table[] escape.
285 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
286 (cpu_flags): Add CpuSEV_ES entry.
287 * i386-opc.h (CpuSEV_ES): New.
288 (union i386_cpu_flags): Add cpusev_es field.
289 * i386-opc.tbl (vmgexit): New.
290 * i386-init.h, i386-tbl.h: Re-generate.
292 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
294 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
296 * i386-opc.h (IGNORESIZE): New.
297 (DEFAULTSIZE): Likewise.
298 (IgnoreSize): Removed.
299 (DefaultSize): Likewise.
301 (i386_opcode_modifier): Replace ignoresize/defaultsize with
303 * i386-opc.tbl (IgnoreSize): New.
304 (DefaultSize): Likewise.
305 * i386-tbl.h: Regenerated.
307 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
310 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
313 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
316 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
317 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
318 * i386-tbl.h: Regenerated.
320 2020-02-26 Alan Modra <amodra@gmail.com>
322 * aarch64-asm.c: Indent labels correctly.
323 * aarch64-dis.c: Likewise.
324 * aarch64-gen.c: Likewise.
325 * aarch64-opc.c: Likewise.
326 * alpha-dis.c: Likewise.
327 * i386-dis.c: Likewise.
328 * nds32-asm.c: Likewise.
329 * nfp-dis.c: Likewise.
330 * visium-dis.c: Likewise.
332 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
334 * arc-regs.h (int_vector_base): Make it available for all ARC
337 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
339 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
342 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
344 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
345 c.mv/c.li if rs1 is zero.
347 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
349 * i386-gen.c (cpu_flag_init): Replace CpuABM with
350 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
352 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
353 * i386-opc.h (CpuABM): Removed.
355 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
356 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
357 popcnt. Remove CpuABM from lzcnt.
358 * i386-init.h: Regenerated.
359 * i386-tbl.h: Likewise.
361 2020-02-17 Jan Beulich <jbeulich@suse.com>
363 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
364 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
365 VexW1 instead of open-coding them.
366 * i386-tbl.h: Re-generate.
368 2020-02-17 Jan Beulich <jbeulich@suse.com>
370 * i386-opc.tbl (AddrPrefixOpReg): Define.
371 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
372 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
373 templates. Drop NoRex64.
374 * i386-tbl.h: Re-generate.
376 2020-02-17 Jan Beulich <jbeulich@suse.com>
379 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
380 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
381 into Intel syntax instance (with Unpsecified) and AT&T one
383 (vcvtneps2bf16): Likewise, along with folding the two so far
385 * i386-tbl.h: Re-generate.
387 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
389 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
392 2020-02-17 Alan Modra <amodra@gmail.com>
394 * i386-gen.c (cpu_flag_init): Correct last change.
396 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
398 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
401 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
403 * i386-opc.tbl (movsx): Remove Intel syntax comments.
406 2020-02-14 Jan Beulich <jbeulich@suse.com>
409 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
410 destination for Cpu64-only variant.
411 (movzx): Fold patterns.
412 * i386-tbl.h: Re-generate.
414 2020-02-13 Jan Beulich <jbeulich@suse.com>
416 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
417 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
418 CPU_ANY_SSE4_FLAGS entry.
419 * i386-init.h: Re-generate.
421 2020-02-12 Jan Beulich <jbeulich@suse.com>
423 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
424 with Unspecified, making the present one AT&T syntax only.
425 * i386-tbl.h: Re-generate.
427 2020-02-12 Jan Beulich <jbeulich@suse.com>
429 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
430 * i386-tbl.h: Re-generate.
432 2020-02-12 Jan Beulich <jbeulich@suse.com>
435 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
436 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
437 Amd64 and Intel64 templates.
438 (call, jmp): Likewise for far indirect variants. Dro
440 * i386-tbl.h: Re-generate.
442 2020-02-11 Jan Beulich <jbeulich@suse.com>
444 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
445 * i386-opc.h (ShortForm): Delete.
446 (struct i386_opcode_modifier): Remove shortform field.
447 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
448 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
449 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
450 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
452 * i386-tbl.h: Re-generate.
454 2020-02-11 Jan Beulich <jbeulich@suse.com>
456 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
457 fucompi): Drop ShortForm from operand-less templates.
458 * i386-tbl.h: Re-generate.
460 2020-02-11 Alan Modra <amodra@gmail.com>
462 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
463 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
464 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
465 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
466 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
468 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
470 * arm-dis.c (print_insn_cde): Define 'V' parse character.
471 (cde_opcodes): Add VCX* instructions.
473 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
474 Matthew Malcomson <matthew.malcomson@arm.com>
476 * arm-dis.c (struct cdeopcode32): New.
477 (CDE_OPCODE): New macro.
478 (cde_opcodes): New disassembly table.
479 (regnames): New option to table.
480 (cde_coprocs): New global variable.
481 (print_insn_cde): New
482 (print_insn_thumb32): Use print_insn_cde.
483 (parse_arm_disassembler_options): Parse coprocN args.
485 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
488 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
490 * i386-opc.h (AMD64): Removed.
494 (INTEL64ONLY): Likewise.
495 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
496 * i386-opc.tbl (Amd64): New.
498 (Intel64Only): Likewise.
499 Replace AMD64 with Amd64. Update sysenter/sysenter with
500 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
501 * i386-tbl.h: Regenerated.
503 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
506 * z80-dis.c: Add support for GBZ80 opcodes.
508 2020-02-04 Alan Modra <amodra@gmail.com>
510 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
512 2020-02-03 Alan Modra <amodra@gmail.com>
514 * m32c-ibld.c: Regenerate.
516 2020-02-01 Alan Modra <amodra@gmail.com>
518 * frv-ibld.c: Regenerate.
520 2020-01-31 Jan Beulich <jbeulich@suse.com>
522 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
523 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
524 (OP_E_memory): Replace xmm_mdq_mode case label by
525 vex_scalar_w_dq_mode one.
526 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
528 2020-01-31 Jan Beulich <jbeulich@suse.com>
530 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
531 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
532 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
533 (intel_operand_size): Drop vex_w_dq_mode case label.
535 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
537 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
538 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
540 2020-01-30 Alan Modra <amodra@gmail.com>
542 * m32c-ibld.c: Regenerate.
544 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
546 * bpf-opc.c: Regenerate.
548 2020-01-30 Jan Beulich <jbeulich@suse.com>
550 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
551 (dis386): Use them to replace C2/C3 table entries.
552 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
553 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
554 ones. Use Size64 instead of DefaultSize on Intel64 ones.
555 * i386-tbl.h: Re-generate.
557 2020-01-30 Jan Beulich <jbeulich@suse.com>
559 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
561 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
563 * i386-tbl.h: Re-generate.
565 2020-01-30 Alan Modra <amodra@gmail.com>
567 * tic4x-dis.c (tic4x_dp): Make unsigned.
569 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
570 Jan Beulich <jbeulich@suse.com>
573 * i386-dis.c (MOVSXD_Fixup): New function.
574 (movsxd_mode): New enum.
575 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
576 (intel_operand_size): Handle movsxd_mode.
577 (OP_E_register): Likewise.
579 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
580 register on movsxd. Add movsxd with 16-bit destination register
581 for AMD64 and Intel64 ISAs.
582 * i386-tbl.h: Regenerated.
584 2020-01-27 Tamar Christina <tamar.christina@arm.com>
587 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
588 * aarch64-asm-2.c: Regenerate
589 * aarch64-dis-2.c: Likewise.
590 * aarch64-opc-2.c: Likewise.
592 2020-01-21 Jan Beulich <jbeulich@suse.com>
594 * i386-opc.tbl (sysret): Drop DefaultSize.
595 * i386-tbl.h: Re-generate.
597 2020-01-21 Jan Beulich <jbeulich@suse.com>
599 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
601 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
602 * i386-tbl.h: Re-generate.
604 2020-01-20 Nick Clifton <nickc@redhat.com>
606 * po/de.po: Updated German translation.
607 * po/pt_BR.po: Updated Brazilian Portuguese translation.
608 * po/uk.po: Updated Ukranian translation.
610 2020-01-20 Alan Modra <amodra@gmail.com>
612 * hppa-dis.c (fput_const): Remove useless cast.
614 2020-01-20 Alan Modra <amodra@gmail.com>
616 * arm-dis.c (print_insn_arm): Wrap 'T' value.
618 2020-01-18 Nick Clifton <nickc@redhat.com>
620 * configure: Regenerate.
621 * po/opcodes.pot: Regenerate.
623 2020-01-18 Nick Clifton <nickc@redhat.com>
625 Binutils 2.34 branch created.
627 2020-01-17 Christian Biesinger <cbiesinger@google.com>
629 * opintl.h: Fix spelling error (seperate).
631 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
633 * i386-opc.tbl: Add {vex} pseudo prefix.
634 * i386-tbl.h: Regenerated.
636 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
639 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
640 (neon_opcodes): Likewise.
641 (select_arm_features): Make sure we enable MVE bits when selecting
642 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
645 2020-01-16 Jan Beulich <jbeulich@suse.com>
647 * i386-opc.tbl: Drop stale comment from XOP section.
649 2020-01-16 Jan Beulich <jbeulich@suse.com>
651 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
652 (extractps): Add VexWIG to SSE2AVX forms.
653 * i386-tbl.h: Re-generate.
655 2020-01-16 Jan Beulich <jbeulich@suse.com>
657 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
658 Size64 from and use VexW1 on SSE2AVX forms.
659 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
660 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
661 * i386-tbl.h: Re-generate.
663 2020-01-15 Alan Modra <amodra@gmail.com>
665 * tic4x-dis.c (tic4x_version): Make unsigned long.
666 (optab, optab_special, registernames): New file scope vars.
667 (tic4x_print_register): Set up registernames rather than
668 malloc'd registertable.
669 (tic4x_disassemble): Delete optable and optable_special. Use
670 optab and optab_special instead. Throw away old optab,
671 optab_special and registernames when info->mach changes.
673 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
676 * z80-dis.c (suffix): Use .db instruction to generate double
679 2020-01-14 Alan Modra <amodra@gmail.com>
681 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
682 values to unsigned before shifting.
684 2020-01-13 Thomas Troeger <tstroege@gmx.de>
686 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
688 (print_insn_thumb16, print_insn_thumb32): Likewise.
689 (print_insn): Initialize the insn info.
690 * i386-dis.c (print_insn): Initialize the insn info fields, and
693 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
695 * arc-opc.c (C_NE): Make it required.
697 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
699 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
700 reserved register name.
702 2020-01-13 Alan Modra <amodra@gmail.com>
704 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
705 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
707 2020-01-13 Alan Modra <amodra@gmail.com>
709 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
710 result of wasm_read_leb128 in a uint64_t and check that bits
711 are not lost when copying to other locals. Use uint32_t for
712 most locals. Use PRId64 when printing int64_t.
714 2020-01-13 Alan Modra <amodra@gmail.com>
716 * score-dis.c: Formatting.
717 * score7-dis.c: Formatting.
719 2020-01-13 Alan Modra <amodra@gmail.com>
721 * score-dis.c (print_insn_score48): Use unsigned variables for
722 unsigned values. Don't left shift negative values.
723 (print_insn_score32): Likewise.
724 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
726 2020-01-13 Alan Modra <amodra@gmail.com>
728 * tic4x-dis.c (tic4x_print_register): Remove dead code.
730 2020-01-13 Alan Modra <amodra@gmail.com>
732 * fr30-ibld.c: Regenerate.
734 2020-01-13 Alan Modra <amodra@gmail.com>
736 * xgate-dis.c (print_insn): Don't left shift signed value.
737 (ripBits): Formatting, use 1u.
739 2020-01-10 Alan Modra <amodra@gmail.com>
741 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
742 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
744 2020-01-10 Alan Modra <amodra@gmail.com>
746 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
747 and XRREG value earlier to avoid a shift with negative exponent.
748 * m10200-dis.c (disassemble): Similarly.
750 2020-01-09 Nick Clifton <nickc@redhat.com>
753 * z80-dis.c (ld_ii_ii): Use correct cast.
755 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
758 * z80-dis.c (ld_ii_ii): Use character constant when checking
761 2020-01-09 Jan Beulich <jbeulich@suse.com>
763 * i386-dis.c (SEP_Fixup): New.
765 (dis386_twobyte): Use it for sysenter/sysexit.
766 (enum x86_64_isa): Change amd64 enumerator to value 1.
767 (OP_J): Compare isa64 against intel64 instead of amd64.
768 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
770 * i386-tbl.h: Re-generate.
772 2020-01-08 Alan Modra <amodra@gmail.com>
774 * z8k-dis.c: Include libiberty.h
775 (instr_data_s): Make max_fetched unsigned.
776 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
777 Don't exceed byte_info bounds.
778 (output_instr): Make num_bytes unsigned.
779 (unpack_instr): Likewise for nibl_count and loop.
780 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
782 * z8k-opc.h: Regenerate.
784 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
786 * arc-tbl.h (llock): Use 'LLOCK' as class.
788 (scond): Use 'SCOND' as class.
790 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
793 2020-01-06 Alan Modra <amodra@gmail.com>
795 * m32c-ibld.c: Regenerate.
797 2020-01-06 Alan Modra <amodra@gmail.com>
800 * z80-dis.c (suffix): Don't use a local struct buffer copy.
801 Peek at next byte to prevent recursion on repeated prefix bytes.
802 Ensure uninitialised "mybuf" is not accessed.
803 (print_insn_z80): Don't zero n_fetch and n_used here,..
804 (print_insn_z80_buf): ..do it here instead.
806 2020-01-04 Alan Modra <amodra@gmail.com>
808 * m32r-ibld.c: Regenerate.
810 2020-01-04 Alan Modra <amodra@gmail.com>
812 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
814 2020-01-04 Alan Modra <amodra@gmail.com>
816 * crx-dis.c (match_opcode): Avoid shift left of signed value.
818 2020-01-04 Alan Modra <amodra@gmail.com>
820 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
822 2020-01-03 Jan Beulich <jbeulich@suse.com>
824 * aarch64-tbl.h (aarch64_opcode_table): Use
825 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
827 2020-01-03 Jan Beulich <jbeulich@suse.com>
829 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
830 forms of SUDOT and USDOT.
832 2020-01-03 Jan Beulich <jbeulich@suse.com>
834 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
836 * opcodes/aarch64-dis-2.c: Re-generate.
838 2020-01-03 Jan Beulich <jbeulich@suse.com>
840 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
842 * opcodes/aarch64-dis-2.c: Re-generate.
844 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
846 * z80-dis.c: Add support for eZ80 and Z80 instructions.
848 2020-01-01 Alan Modra <amodra@gmail.com>
850 Update year range in copyright notice of all files.
852 For older changes see ChangeLog-2019
854 Copyright (C) 2020 Free Software Foundation, Inc.
856 Copying and distribution of this file, with or without modification,
857 are permitted in any medium without royalty provided the copyright
858 notice and this notice are preserved.
864 version-control: never