1 2023-02-28 Richard Ball <richard.ball@arm.com>
3 * aarch64-opc.c: Add MEC system registers.
5 2023-01-03 Nick Clifton <nickc@redhat.com>
7 * po/de.po: Updated German translation.
8 * po/ro.po: Updated Romainian translation.
9 * po/uk.po: Updated Ukrainian translation.
11 2022-12-31 Nick Clifton <nickc@redhat.com>
13 * 2.40 branch created.
15 2022-11-22 Shahab Vahedi <shahab@synopsys.com>
17 * arc-regs.h: Change isa_config address to 0xc1.
18 isa_config exists for ARC700 and ARCV2 and not ARCALL.
20 2022-10-31 Yoshinori Sato <ysato@users.sourceforge.jp>
22 * rx-decode.opc: Switch arguments of the MVTACGU insn.
23 * rx-decode.c: Regenerate.
25 2022-09-22 Yoshinori Sato <ysato@users.sourceforge.jp>
27 * sh-dis.c (print_insn_sh): Enforce bit7 of LDC Rm,Rn_BANK and STC
28 Rm_BANK,Rn is always 1.
30 2022-07-21 Peter Bergner <bergner@linux.ibm.com>
32 * ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines.
33 (P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4,
34 xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8,
35 xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp,
36 xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp,
37 xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn,
38 xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them.
40 2022-07-18 Claudiu Zissulescu <claziss@synopsys.com>
42 * disassemble.c (disassemble_init_for_target): Set
43 created_styled_output for ARC based targets.
44 * arc-dis.c (find_format_from_table): Use fprintf_styled_ftype
45 instead of fprintf_ftype throughout.
46 (find_format): Likewise.
47 (print_flags): Likewise.
48 (print_insn_arc): Likewise.
50 2022-07-08 Nick Clifton <nickc@redhat.com>
52 * 2.39 branch created.
54 2022-07-04 Marcus Nilsson <brainbomb@gmail.com>
56 * disassemble.c: (disassemble_init_for_target): Set
57 created_styled_output for AVR based targets.
58 * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype
59 instead of fprintf_ftype throughout.
60 (avr_operand): Pass in and fill disassembler_style when
63 2022-04-07 Andreas Krebbel <krebbel@linux.ibm.com>
65 * s390-mkopc.c (main): Enable z16 as CPU string in the opcode
68 2022-03-16 Simon Marchi <simon.marchi@efficios.com>
70 * configure.ac: Handle bfd_amdgcn_arch.
71 * configure: Re-generate.
73 2022-03-06 Sagar Patel <sagarmp@cs.unc.edu>
74 Maciej W. Rozycki <macro@orcam.me.uk>
76 * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
77 for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
78 * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
81 2022-02-17 Nick Clifton <nickc@redhat.com>
83 * po/sr.po: Updated Serbian translation.
85 2022-02-14 Sergei Trofimovich <siarheit@google.com>
87 * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
88 * microblaze-opc.h: Follow 'fsqrt' rename.
90 2022-01-24 Nick Clifton <nickc@redhat.com>
92 * po/ro.po: Updated Romanian translation.
93 * po/uk.po: Updated Ukranian translation.
95 2022-01-22 Nick Clifton <nickc@redhat.com>
97 * configure: Regenerate.
98 * po/opcodes.pot: Regenerate.
100 2022-01-22 Nick Clifton <nickc@redhat.com>
102 * 2.38 release branch created.
104 2022-01-17 Nick Clifton <nickc@redhat.com>
106 * Makefile.in: Regenerate.
107 * po/opcodes.pot: Regenerate.
109 2021-12-02 Marcus Nilsson <brainbomb@gmail.com>
111 * avr-dis.c (avr_operand); Pass in disassemble_info and fill
112 in insn_type on branching instructions.
114 2021-11-25 Andrew Burgess <aburgess@redhat.com>
115 Simon Cook <simon.cook@embecosm.com>
117 * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
118 (riscv_options): New static global.
119 (disassembler_options_riscv): New function.
120 (print_riscv_disassembler_options): Rewrite to use
121 disassembler_options_riscv.
123 2021-11-25 Nick Clifton <nickc@redhat.com>
126 * aarch64-asm.c: Replace assert(0) with real code.
127 * aarch64-dis.c: Likewise.
128 * aarch64-opc.c: Likewise.
130 2021-11-25 Nick Clifton <nickc@redhat.com>
132 * po/fr.po; Updated French translation.
134 2021-10-27 Maciej W. Rozycki <macro@embecosm.com>
136 * Makefile.am: Remove obsolete comment.
137 * configure.ac: Refer `libbfd.la' to link shared BFD library
139 * Makefile.in: Regenerate.
140 * configure: Regenerate.
142 2021-09-27 Nick Alcock <nick.alcock@oracle.com>
144 * configure: Regenerate.
146 2021-09-25 Peter Bergner <bergner@linux.ibm.com>
148 * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
151 2021-09-20 Andrew Burgess <andrew.burgess@embecosm.com>
153 * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
154 before an unknown instruction, '%d' is replaced with the
157 2021-09-02 Nick Clifton <nickc@redhat.com>
160 * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
163 2021-08-17 Shahab Vahedi <shahab@synopsys.com>
165 * arc-regs.h (DEF): Fix the register numbers.
167 2021-08-10 Nick Clifton <nickc@redhat.com>
169 * po/sr.po: Updated Serbian translation.
171 2021-07-26 Chenghua Xu <xuchenghua@loongson.cn>
173 * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
175 2021-06-07 Andreas Krebbel <krebbel@linux.ibm.com>
177 * s390-opc.txt: Add qpaci.
179 2021-07-03 Nick Clifton <nickc@redhat.com>
181 * configure: Regenerate.
182 * po/opcodes.pot: Regenerate.
184 2021-07-03 Nick Clifton <nickc@redhat.com>
186 * 2.37 release branch created.
188 2021-07-02 Alan Modra <amodra@gmail.com>
190 * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
191 (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
192 (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
193 (nds32_opcodes, nds32_operand_fields, nds32_keywords),
194 (nds32_keyword_gpr): Move declarations to..
195 * nds32-asm.h: ..here, constifying to match definitions.
197 2021-07-01 Mike Frysinger <vapier@gentoo.org>
199 * Makefile.am (GUILE): New variable.
200 (CGEN): Use $(GUILE).
201 * Makefile.in: Regenerate.
203 2021-07-01 Mike Frysinger <vapier@gentoo.org>
205 * mep-asm.c (macros): Mark static & const.
206 (lookup_macro): Change return & m to const.
207 (expand_macro): Change mac to const.
208 (expand_string): Change pmacro to const.
210 2021-07-01 Mike Frysinger <vapier@gentoo.org>
212 * nds32-asm.c (operand_fields): Rename to ...
213 (nds32_operand_fields): ... this.
214 (keyword_gpr): Rename to ...
215 (nds32_keyword_gpr): ... this.
216 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
217 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
218 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
219 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
220 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
222 (keywords): Rename to ...
223 (nds32_keywords): ... this.
224 * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
225 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
227 2021-07-01 Mike Frysinger <vapier@gentoo.org>
229 * z80-dis.c (opc_ed): Make const.
230 (pref_ed): Make p const.
232 2021-07-01 Mike Frysinger <vapier@gentoo.org>
234 * microblaze-dis.c (get_field_special): Make op const.
235 (read_insn_microblaze): Make opr & op const. Rename opcodes to
237 (print_insn_microblaze): Make op & pop const.
238 (get_insn_microblaze): Make op const. Rename opcodes to
240 (microblaze_get_target_address): Likewise.
241 * microblaze-opc.h (struct op_code_struct): Make const.
242 Rename opcodes to microblaze_opcodes.
244 2021-07-01 Mike Frysinger <vapier@gentoo.org>
246 * aarch64-gen.c (aarch64_opcode_table): Add const.
247 * aarch64-tbl.h (aarch64_opcode_table): Likewise.
249 2021-06-22 Andrew Burgess <andrew.burgess@embecosm.com>
251 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
254 2021-06-22 Alan Modra <amodra@gmail.com>
256 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do
257 print separator for pcrel insns.
259 2021-06-19 Alan Modra <amodra@gmail.com>
261 * vax-dis.c (print_insn_vax): Avoid pointer overflow.
263 2021-06-19 Alan Modra <amodra@gmail.com>
265 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
268 2021-06-17 Alan Modra <amodra@gmail.com>
270 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
273 2021-06-03 Alan Modra <amodra@gmail.com>
276 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
277 Use unsigned int for inst.
279 2021-06-02 Shahab Vahedi <shahab@synopsys.com>
281 * arc-dis.c (arc_option_arg_t): New enumeration.
282 (arc_options): New variable.
283 (disassembler_options_arc): New function.
284 (print_arc_disassembler_options): Reimplement in terms of
285 "disassembler_options_arc".
287 2021-05-29 Alan Modra <amodra@gmail.com>
289 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
290 Don't special case PPC_OPCODE_RAW.
291 (lookup_prefix): Likewise.
292 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
293 (print_insn_powerpc): ..update caller.
294 * ppc-opc.c (EXT): Define.
295 (powerpc_opcodes): Mark extended mnemonics with EXT.
296 (prefix_opcodes, vle_opcodes): Likewise.
297 (XISEL, XISEL_MASK): Add cr field and simplify.
298 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
299 all isel variants to where the base mnemonic belongs. Sort dstt,
302 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
304 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
305 COP3 opcode instructions.
307 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
309 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
310 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
311 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
312 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
313 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
314 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
315 "cop2", and "cop3" entries.
317 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
319 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
320 entries and associated comments.
322 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
324 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
327 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
329 * mips-dis.c (mips_cp1_names_mips): New variable.
330 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
331 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
332 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
333 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
334 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
337 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
339 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
340 handling code over to...
341 <OP_REG_CONTROL>: ... this new case.
342 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
343 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
344 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
345 replacing the `G' operand code with `g'. Update "cftc1" and
346 "cftc2" entries replacing the `E' operand code with `y'.
347 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
348 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
349 entries replacing the `G' operand code with `g'.
351 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
353 * mips-dis.c (mips_cp0_names_r3900): New variable.
354 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
357 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
359 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
360 and "mtthc2" to using the `G' rather than `g' operand code for
361 the coprocessor control register referred.
363 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
365 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
366 entries with each other.
368 2021-05-27 Peter Bergner <bergner@linux.ibm.com>
370 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
372 2021-05-25 Alan Modra <amodra@gmail.com>
374 * cris-desc.c: Regenerate.
375 * cris-desc.h: Regenerate.
376 * cris-opc.h: Regenerate.
377 * po/POTFILES.in: Regenerate.
379 2021-05-24 Mike Frysinger <vapier@gentoo.org>
381 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
382 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
383 (CGEN_CPUS): Add cris.
385 (stamp-cris): New rule.
386 * cgen.sh: Handle desc action.
387 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
388 * Makefile.in, configure: Regenerate.
390 2021-05-18 Job Noorman <mtvec@pm.me>
393 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
396 2021-05-17 Alex Coplan <alex.coplan@arm.com>
398 * arm-dis.c (mve_opcodes): Fix disassembly of
399 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
400 (is_mve_encoding_conflict): MVE vector loads should not match
402 (is_mve_unpredictable): It's not unpredictable to use the same
403 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
405 2021-05-11 Nick Clifton <nickc@redhat.com>
408 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
409 the end of the code buffer.
411 2021-05-06 Stafford Horne <shorne@gmail.com>
414 * or1k-asm.c: Regenerate.
416 2021-05-01 Max Filippov <jcmvbkbc@gmail.com>
418 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
419 info->insn_info_valid.
421 2021-04-26 Jan Beulich <jbeulich@suse.com>
423 * i386-opc.tbl (lea): Add Optimize.
424 * opcodes/i386-tbl.h: Re-generate.
426 2020-04-23 Max Filippov <jcmvbkbc@gmail.com>
428 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
429 of l32r fetch and display referenced literal value.
431 2021-04-23 Max Filippov <jcmvbkbc@gmail.com>
433 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
434 to 4 for literal disassembly.
436 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
438 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
439 for TLBI instruction.
441 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
443 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
446 2021-04-19 Jan Beulich <jbeulich@suse.com>
448 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
450 (convert_mov_to_movewide): Add initializer for "value".
452 2021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
454 * aarch64-opc.c: Add RME system registers.
456 2021-04-16 Lifang Xia <lifang_xia@c-sky.com>
458 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
459 "addi d,CV,z" to "c.mv d,CV".
461 2021-04-12 Alan Modra <amodra@gmail.com>
463 * configure.ac (--enable-checking): Add support.
464 * config.in: Regenerate.
465 * configure: Regenerate.
467 2021-04-09 Tejas Belagod <tejas.belagod@arm.com>
469 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
470 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
472 2021-04-09 Alan Modra <amodra@gmail.com>
474 * ppc-dis.c (struct dis_private): Add "special".
475 (POWERPC_DIALECT): Delete. Replace uses with..
476 (private_data): ..this. New inline function.
477 (disassemble_init_powerpc): Init "special" names.
478 (skip_optional_operands): Add is_pcrel arg, set when detecting R
479 field of prefix instructions.
480 (bsearch_reloc, print_got_plt): New functions.
481 (print_insn_powerpc): For pcrel instructions, print target address
482 and symbol if known, and decode plt and got loads too.
484 2021-04-08 Alan Modra <amodra@gmail.com>
487 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
489 2021-04-08 Alan Modra <amodra@gmail.com>
492 * ppc-opc.c (DCBT_EO): Move earlier.
493 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
494 (powerpc_operands): Add THCT and THDS entries.
495 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
497 2021-04-06 Alan Modra <amodra@gmail.com>
499 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
500 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
501 symbol_at_address_func.
503 2021-04-05 Alan Modra <amodra@gmail.com>
505 * configure.ac: Don't check for limits.h, string.h, strings.h or
507 (AC_ISC_POSIX): Don't invoke.
508 * sysdep.h: Include stdlib.h and string.h unconditionally.
509 * i386-opc.h: Include limits.h unconditionally.
510 * wasm32-dis.c: Likewise.
511 * cgen-opc.c: Don't include alloca-conf.h.
512 * config.in: Regenerate.
513 * configure: Regenerate.
515 2021-04-01 Martin Liska <mliska@suse.cz>
517 * arm-dis.c (strneq): Remove strneq and use startswith.
518 * cr16-dis.c (print_insn_cr16): Likewise.
519 * score-dis.c (streq): Likewise.
521 * score7-dis.c (strneq): Likewise.
523 2021-04-01 Alan Modra <amodra@gmail.com>
526 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
528 2021-03-31 Alan Modra <amodra@gmail.com>
530 * sysdep.h (POISON_BFD_BOOLEAN): Define.
531 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
532 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
533 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
534 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
535 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
536 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
537 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
538 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
539 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
540 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
541 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
542 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
543 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
544 and TRUE with true throughout.
546 2021-03-31 Alan Modra <amodra@gmail.com>
548 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
549 * aarch64-dis.h: Likewise.
550 * aarch64-opc.c: Likewise.
551 * avr-dis.c: Likewise.
552 * csky-dis.c: Likewise.
553 * nds32-asm.c: Likewise.
554 * nds32-dis.c: Likewise.
555 * nfp-dis.c: Likewise.
556 * riscv-dis.c: Likewise.
557 * s12z-dis.c: Likewise.
558 * wasm32-dis.c: Likewise.
560 2021-03-30 Jan Beulich <jbeulich@suse.com>
562 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
563 (i386_seg_prefixes): New.
564 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
565 (i386_seg_prefixes): Declare.
567 2021-03-30 Jan Beulich <jbeulich@suse.com>
569 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
571 2021-03-30 Jan Beulich <jbeulich@suse.com>
573 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
574 * i386-reg.tbl (st): Move down.
575 (st(0)): Delete. Extend comment.
576 * i386-tbl.h: Re-generate.
578 2021-03-29 Jan Beulich <jbeulich@suse.com>
580 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
581 (cmpsd): Move next to cmps.
582 (movsd): Move next to movs.
583 (cmpxchg16b): Move to separate section.
584 (fisttp, fisttpll): Likewise.
585 (monitor, mwait): Likewise.
586 * i386-tbl.h: Re-generate.
588 2021-03-29 Jan Beulich <jbeulich@suse.com>
590 * i386-opc.tbl (psadbw): Add <sse2:comm>.
592 * i386-tbl.h: Re-generate.
594 2021-03-29 Jan Beulich <jbeulich@suse.com>
596 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
597 pclmul, gfni): New templates. Use them wherever possible. Move
598 SSE4.1 pextrw into respective section.
599 * i386-tbl.h: Re-generate.
601 2021-03-29 Jan Beulich <jbeulich@suse.com>
603 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
604 strtoull(). Bump upper loop bound. Widen masks. Sanity check
606 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
607 Convert all of their uses to representation in opcode.
609 2021-03-29 Jan Beulich <jbeulich@suse.com>
611 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
612 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
613 value of None. Shrink operands to 3 bits.
615 2021-03-29 Jan Beulich <jbeulich@suse.com>
617 * i386-gen.c (process_i386_opcode_modifier): New parameter
619 (output_i386_opcode): New local variable "space". Adjust
620 process_i386_opcode_modifier() invocation.
621 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
623 * i386-tbl.h: Re-generate.
625 2021-03-29 Alan Modra <amodra@gmail.com>
627 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
628 (fp_qualifier_p, get_data_pattern): Likewise.
629 (aarch64_get_operand_modifier_from_value): Likewise.
630 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
631 (operand_variant_qualifier_p): Likewise.
632 (qualifier_value_in_range_constraint_p): Likewise.
633 (aarch64_get_qualifier_esize): Likewise.
634 (aarch64_get_qualifier_nelem): Likewise.
635 (aarch64_get_qualifier_standard_value): Likewise.
636 (get_lower_bound, get_upper_bound): Likewise.
637 (aarch64_find_best_match, match_operands_qualifier): Likewise.
638 (aarch64_print_operand): Likewise.
639 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
640 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
641 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
642 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
643 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
644 (print_insn_tic6x): Likewise.
646 2021-03-29 Alan Modra <amodra@gmail.com>
648 * arc-dis.c (extract_operand_value): Correct NULL cast.
649 * frv-opc.h: Regenerate.
651 2021-03-26 Jan Beulich <jbeulich@suse.com>
653 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
655 * i386-tbl.h: Re-generate.
657 2021-03-25 Abid Qadeer <abidh@codesourcery.com>
659 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
660 immediate in br.n instruction.
662 2021-03-25 Jan Beulich <jbeulich@suse.com>
664 * i386-dis.c (XMGatherD, VexGatherD): New.
665 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
666 (print_insn): Check masking for S/G insns.
667 (OP_E_memory): New local variable check_gather. Extend mandatory
668 SIB check. Check register conflicts for (EVEX-encoded) gathers.
669 Extend check for disallowed 16-bit addressing.
670 (OP_VEX): New local variables modrm_reg and sib_index. Convert
671 if()s to switch(). Check register conflicts for (VEX-encoded)
672 gathers. Drop no longer reachable cases.
673 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
676 2021-03-25 Jan Beulich <jbeulich@suse.com>
678 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
679 zeroing-masking without masking.
681 2021-03-25 Jan Beulich <jbeulich@suse.com>
683 * i386-opc.tbl (invlpgb): Fix multi-operand form.
684 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
685 single-operand forms as deprecated.
686 * i386-tbl.h: Re-generate.
688 2021-03-25 Alan Modra <amodra@gmail.com>
691 * ppc-opc.c (XLOCB_MASK): Delete.
692 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
694 (powerpc_opcodes): Accept a BH field on all extended forms of
695 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
697 2021-03-24 Jan Beulich <jbeulich@suse.com>
699 * i386-gen.c (output_i386_opcode): Drop processing of
700 opcode_length. Calculate length from base_opcode. Adjust prefix
701 encoding determination.
702 (process_i386_opcodes): Drop output of fake opcode_length.
703 * i386-opc.h (struct insn_template): Drop opcode_length field.
704 * i386-opc.tbl: Drop opcode length field from all templates.
705 * i386-tbl.h: Re-generate.
707 2021-03-24 Jan Beulich <jbeulich@suse.com>
709 * i386-gen.c (process_i386_opcode_modifier): Return void. New
710 parameter "prefix". Drop local variable "regular_encoding".
711 Record prefix setting / check for consistency.
712 (output_i386_opcode): Parse opcode_length and base_opcode
713 earlier. Derive prefix encoding. Drop no longer applicable
714 consistency checking. Adjust process_i386_opcode_modifier()
716 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
718 * i386-tbl.h: Re-generate.
720 2021-03-24 Jan Beulich <jbeulich@suse.com>
722 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
724 * i386-opc.h (Prefix_*): Move #define-s.
725 * i386-opc.tbl: Move pseudo prefix enumerator values to
726 extension opcode field. Introduce pseudopfx template.
727 * i386-tbl.h: Re-generate.
729 2021-03-23 Jan Beulich <jbeulich@suse.com>
731 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
733 * i386-tbl.h: Re-generate.
735 2021-03-23 Jan Beulich <jbeulich@suse.com>
737 * i386-opc.h (struct insn_template): Move cpu_flags field past
739 * i386-tbl.h: Re-generate.
741 2021-03-23 Jan Beulich <jbeulich@suse.com>
743 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
744 * i386-opc.h (OpcodeSpace): New enumerator.
745 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
746 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
747 SPACE_XOP09, SPACE_XOP0A): ... respectively.
748 (struct i386_opcode_modifier): New field opcodespace. Shrink
750 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
751 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
753 * i386-tbl.h: Re-generate.
755 2021-03-22 Martin Liska <mliska@suse.cz>
757 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
758 * arc-dis.c (parse_option): Likewise.
759 * arm-dis.c (parse_arm_disassembler_options): Likewise.
760 * cris-dis.c (print_with_operands): Likewise.
761 * h8300-dis.c (bfd_h8_disassemble): Likewise.
762 * i386-dis.c (print_insn): Likewise.
763 * ia64-gen.c (fetch_insn_class): Likewise.
764 (parse_resource_users): Likewise.
765 (in_iclass): Likewise.
766 (lookup_specifier): Likewise.
767 (insert_opcode_dependencies): Likewise.
768 * mips-dis.c (parse_mips_ase_option): Likewise.
769 (parse_mips_dis_option): Likewise.
770 * s390-dis.c (disassemble_init_s390): Likewise.
771 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
773 2021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
775 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
777 2021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
779 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
780 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
782 2021-03-12 Alan Modra <amodra@gmail.com>
784 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
786 2021-03-11 Jan Beulich <jbeulich@suse.com>
788 * i386-dis.c (OP_XMM): Re-order checks.
790 2021-03-11 Jan Beulich <jbeulich@suse.com>
792 * i386-dis.c (putop): Drop need_vex check when also checking
794 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
797 2021-03-11 Jan Beulich <jbeulich@suse.com>
799 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
800 checks. Move case label past broadcast check.
802 2021-03-10 Jan Beulich <jbeulich@suse.com>
804 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
805 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
806 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
807 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
808 EVEX_W_0F38C7_M_0_L_2): Delete.
809 (REG_EVEX_0F38C7_M_0_L_2): New.
810 (intel_operand_size): Handle VEX and EVEX the same for
811 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
812 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
813 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
814 vex_vsib_q_w_d_mode uses.
815 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
816 0F38A1, and 0F38A3 entries.
817 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
819 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
820 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
823 2021-03-10 Jan Beulich <jbeulich@suse.com>
825 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
826 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
827 MOD_VEX_0FXOP_09_12): Rename to ...
828 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
829 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
830 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
831 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
832 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
833 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
834 (reg_table): Adjust comments.
835 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
836 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
837 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
838 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
839 (vex_len_table): Adjust opcode 0A_12 entry.
840 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
841 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
842 (rm_table): Move hreset entry.
844 2021-03-10 Jan Beulich <jbeulich@suse.com>
846 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
847 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
848 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
849 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
850 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
851 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
852 (get_valid_dis386): Also handle 512-bit vector length when
853 vectoring into vex_len_table[].
854 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
855 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
857 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
858 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
859 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
860 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
863 2021-03-10 Jan Beulich <jbeulich@suse.com>
865 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
866 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
867 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
868 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
870 * i386-dis-evex-len.h (evex_len_table): Likewise.
871 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
873 2021-03-10 Jan Beulich <jbeulich@suse.com>
875 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
876 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
877 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
878 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
879 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
880 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
881 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
882 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
883 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
884 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
885 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
886 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
887 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
888 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
889 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
890 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
891 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
892 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
893 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
894 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
895 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
896 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
897 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
898 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
899 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
900 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
901 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
902 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
903 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
904 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
905 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
906 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
907 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
908 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
909 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
910 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
911 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
912 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
913 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
914 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
915 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
916 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
917 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
918 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
919 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
920 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
921 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
922 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
923 EVEX_W_0F3A43_L_n): New.
924 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
925 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
926 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
927 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
928 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
929 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
930 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
931 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
932 0F385B, 0F38C6, and 0F38C7 entries.
933 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
935 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
936 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
937 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
938 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
940 2021-03-10 Jan Beulich <jbeulich@suse.com>
942 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
943 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
944 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
945 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
946 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
947 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
948 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
949 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
950 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
951 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
952 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
953 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
954 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
955 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
956 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
957 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
958 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
959 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
960 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
961 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
962 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
963 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
964 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
965 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
966 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
967 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
968 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
969 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
970 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
971 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
972 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
973 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
974 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
975 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
976 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
977 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
978 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
979 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
980 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
981 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
982 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
983 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
984 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
985 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
986 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
987 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
988 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
989 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
990 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
991 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
992 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
993 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
994 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
995 VEX_W_0F99_P_2_LEN_0): Delete.
996 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
997 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
998 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
999 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
1000 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
1001 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
1002 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
1003 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
1004 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
1005 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
1006 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
1007 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
1008 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
1009 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
1010 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
1011 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
1012 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
1013 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
1014 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
1015 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
1016 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
1017 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
1018 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
1019 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
1020 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
1021 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
1022 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
1023 (prefix_table): No longer link to vex_len_table[] for opcodes
1024 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
1025 0F92, 0F93, 0F98, and 0F99.
1026 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
1027 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1029 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
1030 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1032 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
1033 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1035 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
1036 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1039 2021-03-10 Jan Beulich <jbeulich@suse.com>
1041 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
1042 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
1043 REG_VEX_0F73_M_0 respectively.
1044 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
1045 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
1046 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
1047 MOD_VEX_0F73_REG_7): Delete.
1048 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
1049 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
1050 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
1051 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
1052 PREFIX_VEX_0F3AF0_L_0 respectively.
1053 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
1054 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
1055 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
1056 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
1057 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
1058 VEX_LEN_0F38F7): New.
1059 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
1060 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
1061 0F72, and 0F73. No longer link to vex_len_table[] for opcode
1063 (prefix_table): No longer link to vex_len_table[] for opcodes
1064 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1065 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
1066 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
1067 0F38F6, 0F38F7, and 0F3AF0.
1068 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
1069 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1070 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
1073 2021-03-10 Jan Beulich <jbeulich@suse.com>
1075 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1076 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1077 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1078 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1079 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1080 (MOD_0F71, MOD_0F72, MOD_0F73): New.
1081 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1083 (reg_table): No longer link to mod_table[] for opcodes 0F71,
1085 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1088 2021-03-10 Jan Beulich <jbeulich@suse.com>
1090 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1091 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1092 (reg_table): Don't link to mod_table[] where not needed. Add
1093 PREFIX_IGNORED to nop entries.
1094 (prefix_table): Replace PREFIX_OPCODE in nop entries.
1095 (mod_table): Add nop entries next to prefetch ones. Drop
1096 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1097 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1098 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1099 PREFIX_OPCODE from endbr* entries.
1100 (get_valid_dis386): Also consider entry's name when zapping
1102 (print_insn): Handle PREFIX_IGNORED.
1104 2021-03-09 Jan Beulich <jbeulich@suse.com>
1106 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1107 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1109 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1110 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1111 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1112 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1113 (struct i386_opcode_modifier): Delete notrackprefixok,
1114 islockable, hleprefixok, and repprefixok fields. Add prefixok
1116 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1117 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1118 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1119 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1120 Replace HLEPrefixOk.
1121 * opcodes/i386-tbl.h: Re-generate.
1123 2021-03-09 Jan Beulich <jbeulich@suse.com>
1125 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1126 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1128 * opcodes/i386-tbl.h: Re-generate.
1130 2021-03-03 Jan Beulich <jbeulich@suse.com>
1132 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1133 for {} instead of {0}. Don't look for '0'.
1134 * i386-opc.tbl: Drop operand count field. Drop redundant operand
1137 2021-02-19 Nelson Chu <nelson.chu@sifive.com>
1140 * riscv-dis.c (print_insn_args): Updated encoding macros.
1141 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1142 (match_c_addi16sp): Updated encoding macros.
1143 (match_c_lui): Likewise.
1144 (match_c_lui_with_hint): Likewise.
1145 (match_c_addi4spn): Likewise.
1146 (match_c_slli): Likewise.
1147 (match_slli_as_c_slli): Likewise.
1148 (match_c_slli64): Likewise.
1149 (match_srxi_as_c_srxi): Likewise.
1150 (riscv_insn_types): Added .insn css/cl/cs.
1152 2021-02-18 Nelson Chu <nelson.chu@sifive.com>
1154 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1155 (default_priv_spec): Updated type to riscv_spec_class.
1156 (parse_riscv_dis_option): Updated.
1157 * riscv-opc.c: Moved stuff and make the file tidy.
1159 2021-02-17 Alan Modra <amodra@gmail.com>
1161 * wasm32-dis.c: Include limits.h.
1162 (CHAR_BIT): Provide backup define.
1163 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1164 Correct signed overflow checking.
1166 2021-02-16 Jan Beulich <jbeulich@suse.com>
1168 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1169 * i386-tbl.h: Re-generate.
1171 2021-02-16 Jan Beulich <jbeulich@suse.com>
1173 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1175 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1177 2021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
1179 * s390-mkopc.c (main): Accept arch14 as cpu string.
1180 * s390-opc.txt: Add new arch14 instructions.
1182 2021-02-04 Nick Alcock <nick.alcock@oracle.com>
1184 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1186 * configure: Regenerated.
1188 2021-02-08 Mike Frysinger <vapier@gentoo.org>
1190 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1191 * tic54x-opc.c (regs): Rename to ...
1192 (tic54x_regs): ... this.
1193 (mmregs): Rename to ...
1194 (tic54x_mmregs): ... this.
1195 (condition_codes): Rename to ...
1196 (tic54x_condition_codes): ... this.
1197 (cc2_codes): Rename to ...
1198 (tic54x_cc2_codes): ... this.
1199 (cc3_codes): Rename to ...
1200 (tic54x_cc3_codes): ... this.
1201 (status_bits): Rename to ...
1202 (tic54x_status_bits): ... this.
1203 (misc_symbols): Rename to ...
1204 (tic54x_misc_symbols): ... this.
1206 2021-02-04 Nelson Chu <nelson.chu@sifive.com>
1208 * riscv-opc.c (MASK_RVB_IMM): Removed.
1209 (riscv_opcodes): Removed zb* instructions.
1210 (riscv_ext_version_table): Removed versions for zb*.
1212 2021-01-26 Alan Modra <amodra@gmail.com>
1214 * i386-gen.c (parse_template): Ensure entire template_instance
1217 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1219 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1220 (riscv_fpr_names_abi): Likewise.
1221 (riscv_opcodes): Likewise.
1222 (riscv_insn_types): Likewise.
1224 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1226 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1228 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1230 * riscv-dis.c: Comments tidy and improvement.
1231 * riscv-opc.c: Likewise.
1233 2021-01-13 Alan Modra <amodra@gmail.com>
1235 * Makefile.in: Regenerate.
1237 2021-01-12 H.J. Lu <hongjiu.lu@intel.com>
1240 * configure.ac: Use GNU_MAKE_JOBSERVER.
1241 * aclocal.m4: Regenerated.
1242 * configure: Likewise.
1244 2021-01-12 Nick Clifton <nickc@redhat.com>
1246 * po/sr.po: Updated Serbian translation.
1248 2021-01-11 H.J. Lu <hongjiu.lu@intel.com>
1251 * configure: Regenerated.
1253 2021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1255 * aarch64-asm-2.c: Regenerate.
1256 * aarch64-dis-2.c: Likewise.
1257 * aarch64-opc-2.c: Likewise.
1258 * aarch64-opc.c (aarch64_print_operand):
1259 Delete handling of AARCH64_OPND_CSRE_CSR.
1260 * aarch64-tbl.h (aarch64_feature_csre): Delete.
1262 (_CSRE_INSN): Likewise.
1263 (aarch64_opcode_table): Delete csr.
1265 2021-01-11 Nick Clifton <nickc@redhat.com>
1267 * po/de.po: Updated German translation.
1268 * po/fr.po: Updated French translation.
1269 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1270 * po/sv.po: Updated Swedish translation.
1271 * po/uk.po: Updated Ukranian translation.
1273 2021-01-09 H.J. Lu <hongjiu.lu@intel.com>
1275 * configure: Regenerated.
1277 2021-01-09 Nick Clifton <nickc@redhat.com>
1279 * configure: Regenerate.
1280 * po/opcodes.pot: Regenerate.
1282 2021-01-09 Nick Clifton <nickc@redhat.com>
1284 * 2.36 release branch crated.
1286 2021-01-08 Peter Bergner <bergner@linux.ibm.com>
1288 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1289 (DW, (XRC_MASK): Define.
1290 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1292 2021-01-09 Alan Modra <amodra@gmail.com>
1294 * configure: Regenerate.
1296 2021-01-08 Nick Clifton <nickc@redhat.com>
1298 * po/sv.po: Updated Swedish translation.
1300 2021-01-08 Nick Clifton <nickc@redhat.com>
1303 * aarch64-dis.c (determine_disassembling_preference): Move call to
1304 aarch64_match_operands_constraint outside of the assertion.
1305 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1306 Replace with a return of FALSE.
1309 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1310 core system register.
1312 2021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1314 * configure: Regenerate.
1316 2021-01-07 Nick Clifton <nickc@redhat.com>
1318 * po/fr.po: Updated French translation.
1320 2021-01-07 Fredrik Noring <noring@nocrew.org>
1322 * m68k-opc.c (chkl): Change minimum architecture requirement to
1325 2021-01-07 Philipp Tomsich <prt@gnu.org>
1327 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1329 2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1330 Jim Wilson <jimw@sifive.com>
1331 Andrew Waterman <andrew@sifive.com>
1332 Maxim Blinov <maxim.blinov@embecosm.com>
1333 Kito Cheng <kito.cheng@sifive.com>
1334 Nelson Chu <nelson.chu@sifive.com>
1336 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1337 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1339 2021-01-01 Alan Modra <amodra@gmail.com>
1341 Update year range in copyright notice of all files.
1343 For older changes see ChangeLog-2020
1345 Copyright (C) 2021-2023 Free Software Foundation, Inc.
1347 Copying and distribution of this file, with or without modification,
1348 are permitted in any medium without royalty provided the copyright
1349 notice and this notice are preserved.
1355 version-control: never