opcodes/ChangeLog

   1 2021-03-29  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
   4         pclmul, gfni): New templates. Use them wherever possible. Move
   5         SSE4.1 pextrw into respective section.
   6         * i386-tbl.h: Re-generate.
   7
   8 2021-03-29  Jan Beulich  <jbeulich@suse.com>
   9
  10         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
  11         strtoull(). Bump upper loop bound. Widen masks. Sanity check
  12         "length".
  13         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
  14         Convert all of their uses to representation in opcode.
  15
  16 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  17
  18         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
  19         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
  20         value of None. Shrink operands to 3 bits.
  21
  22 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  23
  24         * i386-gen.c (process_i386_opcode_modifier): New parameter
  25         "space".
  26         (output_i386_opcode): New local variable "space". Adjust
  27         process_i386_opcode_modifier() invocation.
  28         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
  29         invocation.
  30         * i386-tbl.h: Re-generate.
  31
  32 2021-03-29  Alan Modra  <amodra@gmail.com>
  33
  34         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
  35         (fp_qualifier_p, get_data_pattern): Likewise.
  36         (aarch64_get_operand_modifier_from_value): Likewise.
  37         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
  38         (operand_variant_qualifier_p): Likewise.
  39         (qualifier_value_in_range_constraint_p): Likewise.
  40         (aarch64_get_qualifier_esize): Likewise.
  41         (aarch64_get_qualifier_nelem): Likewise.
  42         (aarch64_get_qualifier_standard_value): Likewise.
  43         (get_lower_bound, get_upper_bound): Likewise.
  44         (aarch64_find_best_match, match_operands_qualifier): Likewise.
  45         (aarch64_print_operand): Likewise.
  46         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
  47         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
  48         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
  49         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
  50         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
  51         (print_insn_tic6x): Likewise.
  52
  53 2021-03-29  Alan Modra  <amodra@gmail.com>
  54
  55         * arc-dis.c (extract_operand_value): Correct NULL cast.
  56         * frv-opc.h: Regenerate.
  57
  58 2021-03-26  Jan Beulich  <jbeulich@suse.com>
  59
  60         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
  61         MMX form.
  62         * i386-tbl.h: Re-generate.
  63
  64 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
  65
  66         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
  67         immediate in br.n instruction.
  68
  69 2021-03-25  Jan Beulich  <jbeulich@suse.com>
  70
  71         * i386-dis.c (XMGatherD, VexGatherD): New.
  72         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
  73         (print_insn): Check masking for S/G insns.
  74         (OP_E_memory): New local variable check_gather. Extend mandatory
  75         SIB check. Check register conflicts for (EVEX-encoded) gathers.
  76         Extend check for disallowed 16-bit addressing.
  77         (OP_VEX): New local variables modrm_reg and sib_index. Convert
  78         if()s to switch(). Check register conflicts for (VEX-encoded)
  79         gathers. Drop no longer reachable cases.
  80         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
  81         vgatherdp*.
  82
  83 2021-03-25  Jan Beulich  <jbeulich@suse.com>
  84
  85         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
  86         zeroing-masking without masking.
  87
  88 2021-03-25  Jan Beulich  <jbeulich@suse.com>
  89
  90         * i386-opc.tbl (invlpgb): Fix multi-operand form.
  91         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
  92         single-operand forms as deprecated.
  93         * i386-tbl.h: Re-generate.
  94
  95 2021-03-25  Alan Modra  <amodra@gmail.com>
  96
  97         PR 27647
  98         * ppc-opc.c (XLOCB_MASK): Delete.
  99         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 100         XLBH_MASK.
 101         (powerpc_opcodes): Accept a BH field on all extended forms of
 102         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 103
 104 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 105
 106         * i386-gen.c (output_i386_opcode): Drop processing of
 107         opcode_length. Calculate length from base_opcode. Adjust prefix
 108         encoding determination.
 109         (process_i386_opcodes): Drop output of fake opcode_length.
 110         * i386-opc.h (struct insn_template): Drop opcode_length field.
 111         * i386-opc.tbl: Drop opcode length field from all templates.
 112         * i386-tbl.h: Re-generate.
 113
 114 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 115
 116         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 117         parameter "prefix". Drop local variable "regular_encoding".
 118         Record prefix setting / check for consistency.
 119         (output_i386_opcode): Parse opcode_length and base_opcode
 120         earlier. Derive prefix encoding. Drop no longer applicable
 121         consistency checking. Adjust process_i386_opcode_modifier()
 122         invocation.
 123         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 124         invocation.
 125         * i386-tbl.h: Re-generate.
 126
 127 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 128
 129         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 130         check.
 131         * i386-opc.h (Prefix_*): Move #define-s.
 132         * i386-opc.tbl: Move pseudo prefix enumerator values to
 133         extension opcode field. Introduce pseudopfx template.
 134         * i386-tbl.h: Re-generate.
 135
 136 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 137
 138         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 139         comment.
 140         * i386-tbl.h: Re-generate.
 141
 142 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 143
 144         * i386-opc.h (struct insn_template): Move cpu_flags field past
 145         opcode_modifier one.
 146         * i386-tbl.h: Re-generate.
 147
 148 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 149
 150         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 151         * i386-opc.h (OpcodeSpace): New enumerator.
 152         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 153         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 154         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 155         (struct i386_opcode_modifier): New field opcodespace. Shrink
 156         opcodeprefix field.
 157         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 158         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 159         OpcodePrefix uses.
 160         * i386-tbl.h: Re-generate.
 161
 162 2021-03-22  Martin Liska  <mliska@suse.cz>
 163
 164         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 165         * arc-dis.c (parse_option): Likewise.
 166         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 167         * cris-dis.c (print_with_operands): Likewise.
 168         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 169         * i386-dis.c (print_insn): Likewise.
 170         * ia64-gen.c (fetch_insn_class): Likewise.
 171         (parse_resource_users): Likewise.
 172         (in_iclass): Likewise.
 173         (lookup_specifier): Likewise.
 174         (insert_opcode_dependencies): Likewise.
 175         * mips-dis.c (parse_mips_ase_option): Likewise.
 176         (parse_mips_dis_option): Likewise.
 177         * s390-dis.c (disassemble_init_s390): Likewise.
 178         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 179
 180 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 181
 182         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 183
 184 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 185
 186         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 187         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 188
 189 2021-03-12  Alan Modra  <amodra@gmail.com>
 190
 191         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 192
 193 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 194
 195         * i386-dis.c (OP_XMM): Re-order checks.
 196
 197 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 198
 199         * i386-dis.c (putop): Drop need_vex check when also checking
 200         vex.evex.
 201         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 202         checking vex.b.
 203
 204 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 205
 206         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 207         checks. Move case label past broadcast check.
 208
 209 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 210
 211         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 212         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 213         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 214         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 215         EVEX_W_0F38C7_M_0_L_2): Delete.
 216         (REG_EVEX_0F38C7_M_0_L_2): New.
 217         (intel_operand_size): Handle VEX and EVEX the same for
 218         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 219         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 220         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 221         vex_vsib_q_w_d_mode uses.
 222         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 223         0F38A1, and 0F38A3 entries.
 224         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 225         entry.
 226         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 227         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 228         0F38A3 entries.
 229
 230 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 231
 232         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 233         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 234         MOD_VEX_0FXOP_09_12): Rename to ...
 235         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 236         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 237         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 238         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 239         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 240         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 241         (reg_table): Adjust comments.
 242         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 243         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 244         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 245         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 246         (vex_len_table): Adjust opcode 0A_12 entry.
 247         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 248         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 249         (rm_table): Move hreset entry.
 250
 251 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 252
 253         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 254         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 255         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 256         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 257         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 258         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 259         (get_valid_dis386): Also handle 512-bit vector length when
 260         vectoring into vex_len_table[].
 261         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 262         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 263         entries.
 264         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 265         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 266         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 267         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 268         entries.
 269
 270 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 271
 272         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 273         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 274         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 275         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 276         entries.
 277         * i386-dis-evex-len.h (evex_len_table): Likewise.
 278         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 279
 280 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 281
 282         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 283         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 284         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 285         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 286         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 287         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 288         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 289         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 290         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 291         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 292         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 293         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 294         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 295         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 296         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 297         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 298         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 299         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 300         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 301         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 302         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 303         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 304         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 305         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 306         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 307         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 308         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 309         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 310         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 311         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 312         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 313         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 314         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 315         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 316         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 317         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 318         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 319         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 320         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 321         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 322         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 323         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 324         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 325         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 326         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 327         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 328         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 329         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 330         EVEX_W_0F3A43_L_n): New.
 331         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 332         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 333         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 334         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 335         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 336         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 337         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 338         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 339         0F385B, 0F38C6, and 0F38C7 entries.
 340         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 341         0F38C6 and 0F38C7.
 342         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 343         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 344         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 345         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 346
 347 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 348
 349         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 350         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 351         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 352         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 353         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 354         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 355         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 356         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 357         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 358         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 359         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 360         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 361         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 362         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 363         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 364         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 365         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 366         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 367         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 368         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 369         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 370         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 371         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 372         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 373         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 374         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 375         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 376         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 377         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 378         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 379         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 380         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 381         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 382         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 383         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 384         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 385         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 386         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 387         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 388         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 389         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 390         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 391         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 392         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 393         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 394         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 395         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 396         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 397         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 398         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 399         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 400         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 401         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 402         VEX_W_0F99_P_2_LEN_0): Delete.
 403         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 404         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 405         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 406         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 407         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 408         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 409         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 410         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 411         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 412         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 413         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 414         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 415         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 416         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 417         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 418         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 419         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 420         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 421         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 422         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 423         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 424         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 425         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 426         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 427         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 428         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 429         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 430         (prefix_table): No longer link to vex_len_table[] for opcodes
 431         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 432         0F92, 0F93, 0F98, and 0F99.
 433         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 434         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 435         0F98, and 0F99.
 436         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 437         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 438         0F98, and 0F99.
 439         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 440         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 441         0F98, and 0F99.
 442         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 443         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 444         0F98, and 0F99.
 445
 446 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 447
 448         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 449         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 450         REG_VEX_0F73_M_0 respectively.
 451         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 452         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 453         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 454         MOD_VEX_0F73_REG_7): Delete.
 455         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 456         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 457         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 458         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 459         PREFIX_VEX_0F3AF0_L_0 respectively.
 460         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 461         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 462         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 463         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 464         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 465         VEX_LEN_0F38F7): New.
 466         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 467         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 468         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 469         0F38F3.
 470         (prefix_table): No longer link to vex_len_table[] for opcodes
 471         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 472         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 473         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 474         0F38F6, 0F38F7, and 0F3AF0.
 475         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 476         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 477         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 478         0F73.
 479
 480 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 481
 482         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 483         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 484         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 485         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 486         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 487         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 488         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 489         73.
 490         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 491         0F72, and 0F73.
 492         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 493         0F73.
 494
 495 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 496
 497         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 498         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 499         (reg_table): Don't link to mod_table[] where not needed. Add
 500         PREFIX_IGNORED to nop entries.
 501         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 502         (mod_table): Add nop entries next to prefetch ones. Drop
 503         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 504         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 505         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 506         PREFIX_OPCODE from endbr* entries.
 507         (get_valid_dis386): Also consider entry's name when zapping
 508         vindex.
 509         (print_insn): Handle PREFIX_IGNORED.
 510
 511 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 512
 513         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 514         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 515         element.
 516         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 517         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 518         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 519         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 520         (struct i386_opcode_modifier): Delete notrackprefixok,
 521         islockable, hleprefixok, and repprefixok fields. Add prefixok
 522         field.
 523         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 524         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 525         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 526         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 527         Replace HLEPrefixOk.
 528         * opcodes/i386-tbl.h: Re-generate.
 529
 530 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 531
 532         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 533         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 534         64-bit form.
 535         * opcodes/i386-tbl.h: Re-generate.
 536
 537 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 538
 539         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 540         for {} instead of {0}. Don't look for '0'.
 541         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 542         size specifiers.
 543
 544 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 545
 546         PR 27158
 547         * riscv-dis.c (print_insn_args): Updated encoding macros.
 548         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 549         (match_c_addi16sp): Updated encoding macros.
 550         (match_c_lui): Likewise.
 551         (match_c_lui_with_hint): Likewise.
 552         (match_c_addi4spn): Likewise.
 553         (match_c_slli): Likewise.
 554         (match_slli_as_c_slli): Likewise.
 555         (match_c_slli64): Likewise.
 556         (match_srxi_as_c_srxi): Likewise.
 557         (riscv_insn_types): Added .insn css/cl/cs.
 558
 559 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 560
 561         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 562         (default_priv_spec): Updated type to riscv_spec_class.
 563         (parse_riscv_dis_option): Updated.
 564         * riscv-opc.c: Moved stuff and make the file tidy.
 565
 566 2021-02-17  Alan Modra  <amodra@gmail.com>
 567
 568         * wasm32-dis.c: Include limits.h.
 569         (CHAR_BIT): Provide backup define.
 570         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 571         Correct signed overflow checking.
 572
 573 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 574
 575         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 576         * i386-tbl.h: Re-generate.
 577
 578 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 579
 580         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 581         Oword.
 582         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 583
 584 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 585
 586         * s390-mkopc.c (main): Accept arch14 as cpu string.
 587         * s390-opc.txt: Add new arch14 instructions.
 588
 589 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 590
 591         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 592         favour of LIBINTL.
 593         * configure: Regenerated.
 594
 595 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 596
 597         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 598         * tic54x-opc.c (regs): Rename to ...
 599         (tic54x_regs): ... this.
 600         (mmregs): Rename to ...
 601         (tic54x_mmregs): ... this.
 602         (condition_codes): Rename to ...
 603         (tic54x_condition_codes): ... this.
 604         (cc2_codes): Rename to ...
 605         (tic54x_cc2_codes): ... this.
 606         (cc3_codes): Rename to ...
 607         (tic54x_cc3_codes): ... this.
 608         (status_bits): Rename to ...
 609         (tic54x_status_bits): ... this.
 610         (misc_symbols): Rename to ...
 611         (tic54x_misc_symbols): ... this.
 612
 613 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 614
 615         * riscv-opc.c (MASK_RVB_IMM): Removed.
 616         (riscv_opcodes): Removed zb* instructions.
 617         (riscv_ext_version_table): Removed versions for zb*.
 618
 619 2021-01-26  Alan Modra  <amodra@gmail.com>
 620
 621         * i386-gen.c (parse_template): Ensure entire template_instance
 622         is initialised.
 623
 624 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 625
 626         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 627         (riscv_fpr_names_abi): Likewise.
 628         (riscv_opcodes): Likewise.
 629         (riscv_insn_types): Likewise.
 630
 631 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 632
 633         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 634
 635 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 636
 637         * riscv-dis.c: Comments tidy and improvement.
 638         * riscv-opc.c: Likewise.
 639
 640 2021-01-13  Alan Modra  <amodra@gmail.com>
 641
 642         * Makefile.in: Regenerate.
 643
 644 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 645
 646         PR binutils/26792
 647         * configure.ac: Use GNU_MAKE_JOBSERVER.
 648         * aclocal.m4: Regenerated.
 649         * configure: Likewise.
 650
 651 2021-01-12  Nick Clifton  <nickc@redhat.com>
 652
 653         * po/sr.po: Updated Serbian translation.
 654
 655 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 656
 657         PR ld/27173
 658         * configure: Regenerated.
 659
 660 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 661
 662         * aarch64-asm-2.c: Regenerate.
 663         * aarch64-dis-2.c: Likewise.
 664         * aarch64-opc-2.c: Likewise.
 665         * aarch64-opc.c (aarch64_print_operand):
 666         Delete handling of AARCH64_OPND_CSRE_CSR.
 667         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 668         (CSRE): Likewise.
 669         (_CSRE_INSN): Likewise.
 670         (aarch64_opcode_table): Delete csr.
 671
 672 2021-01-11  Nick Clifton  <nickc@redhat.com>
 673
 674         * po/de.po: Updated German translation.
 675         * po/fr.po: Updated French translation.
 676         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 677         * po/sv.po: Updated Swedish translation.
 678         * po/uk.po: Updated Ukranian translation.
 679
 680 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 681
 682         * configure: Regenerated.
 683
 684 2021-01-09  Nick Clifton  <nickc@redhat.com>
 685
 686         * configure: Regenerate.
 687         * po/opcodes.pot: Regenerate.
 688
 689 2021-01-09  Nick Clifton  <nickc@redhat.com>
 690
 691         * 2.36 release branch crated.
 692
 693 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 694
 695         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 696         (DW, (XRC_MASK): Define.
 697         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 698
 699 2021-01-09  Alan Modra  <amodra@gmail.com>
 700
 701         * configure: Regenerate.
 702
 703 2021-01-08  Nick Clifton  <nickc@redhat.com>
 704
 705         * po/sv.po: Updated Swedish translation.
 706
 707 2021-01-08  Nick Clifton  <nickc@redhat.com>
 708
 709         PR 27129
 710         * aarch64-dis.c (determine_disassembling_preference): Move call to
 711         aarch64_match_operands_constraint outside of the assertion.
 712         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 713         Replace with a return of FALSE.
 714
 715         PR 27139
 716         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 717         core system register.
 718
 719 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 720
 721         * configure: Regenerate.
 722
 723 2021-01-07  Nick Clifton  <nickc@redhat.com>
 724
 725         * po/fr.po: Updated French translation.
 726
 727 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 728
 729         * m68k-opc.c (chkl): Change minimum architecture requirement to
 730         m68020.
 731
 732 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 733
 734         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 735
 736 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 737             Jim Wilson  <jimw@sifive.com>
 738             Andrew Waterman  <andrew@sifive.com>
 739             Maxim Blinov  <maxim.blinov@embecosm.com>
 740             Kito Cheng  <kito.cheng@sifive.com>
 741             Nelson Chu  <nelson.chu@sifive.com>
 742
 743         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 744         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 745
 746 2021-01-01  Alan Modra  <amodra@gmail.com>
 747
 748         Update year range in copyright notice of all files.
 749
 750 For older changes see ChangeLog-2020
 751 \f
 752 Copyright (C) 2021 Free Software Foundation, Inc.
 753
 754 Copying and distribution of this file, with or without modification,
 755 are permitted in any medium without royalty provided the copyright
 756 notice and this notice are preserved.
 757
 758 Local Variables:
 759 mode: change-log
 760 left-margin: 8
 761 fill-column: 74
 762 version-control: never
 763 End: