opcodes/ChangeLog

   1 2020-12-03  Andreas Krebbel  <krebbel@linux.ibm.com>
   2
   3         * s390-opc.txt: Add extended mnemonics.
   4
   5 2020-12-01  Nelson Chu  <nelson.chu@sifive.com>
   6
   7         * riscv-opc.c (riscv_ext_version_table): Remove the p, v, n
   8         and their versions.
   9
  10 2020-12-01  Nelson Chu  <nelson.chu@sifive.com>
  11
  12         * riscv-opc.c (riscv_ext_version_table): Add zifencei.
  13
  14 2020-11-28 Borislav Petkov  <bp@suse.de>
  15
  16         * i386-dis.c (print_insn): Set active_seg_prefix for branch hint insns
  17         to not dump branch hint prefixes 0x2E and 0x3E as unused prefixes.
  18
  19 2020-11-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  20
  21         * aarch64-tbl.h (FLAGM): Handle for FLAGM feature.
  22         (struct aarch64_opcode):  Move FLAGM instructions from V8_4_INSN to
  23         FLAGM_INSN.
  24         (AARCH64_FEATURE_FLAGMANIP): Update comment for FEAT_FlagM2.
  25
  26 2020-11-14  Borislav Petkov  <bp@suse.de>
  27
  28         * i386-dis.c (ckprefix): Do not assign active_seg_prefix in
  29         64-bit addressing mode.
  30         (NOTRACK_Fixup): Test prefixes for PREFIX_DS, instead of
  31         active_seg_prefix.
  32
  33 2020-11-11  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  34
  35         * aarch64-tbl.h: Enable -march=armv8.6-a+ls64.
  36
  37 2020-11-09  Spencer E. Olson  <olsonse@umich.edu>
  38
  39         * pru-opc.c: Add opcode description for LMBD (left-most bit
  40         detect).
  41
  42 2020-11-09  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  43
  44         * aarch64-opc.c: Add ACCDATA_EL1 system register
  45
  46 2020-11-09  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  47
  48         * aarch64-opc.c (aarch64_print_operand): Support operand AARCH64_OPND_Rt_LS64
  49         print.
  50         * aarch64-tbl.h (struct aarch64_opcode): Update _LS64_INSN instructions with
  51         Rt_ls64 operands.
  52         * aarch64-asm-2.c: Regenerated.
  53         * aarch64-dis-2.c: Regenerated.
  54         * aarch64-opc-2.c: Regenerated.
  55
  56 2020-11-06  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  57
  58         * aarch64-tbl.h (PAC): Handle for PAC feature.
  59         (PAC_INSN): New PAC instruction.
  60         (struct aarch64_opcode):  Move PAC instructions from V8_3_INSN to
  61         PAC_INSN.
  62
  63 2020-11-04  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  64
  65         * aarch64-opc.c: Add RAS 1.1 new system registers: ERXPFGCTL_EL1,
  66         ERXPFGCDN_EL1, ERXMISC2_EL1, ERXMISC3_EL1 and ERXPFGF_EL1.
  67
  68 2020-11-03  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  69
  70         * aarch64-tbl.h (QL_X2NIL): New qualifier for 64-byte stores.
  71         (LS64): Handler with +ls64 feature flags.
  72         (_LS64_INSN): New instruction group macro.
  73         (struct aarch64_opcode): Add LS64 instructions.
  74         * aarch64-asm-2.c: Regenerated.
  75         * aarch64-dis-2.c: Regenerated.
  76         * aarch64-opc-2.c: Regenerated.
  77
  78 2020-10-30  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  79
  80         * aarch65-tbl.h (struct aarch64_opcode): New instruction WFIT.
  81         * aarch64-asm-2.c: Regenerated.
  82         * aarch64-dis-2.c: Regenerated.
  83         * aarch64-opc-2.c: Regenerated.
  84
  85 2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  86
  87         * aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out.
  88         * aarch64-tbl.h (CSRE): New CSRE feature handler.
  89         (_CSRE_INSN): New CSRE instruction type.
  90         (struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature.
  91         * aarch64-asm-2.c: Regenerated.
  92         * aarch64-dis-2.c: Regenerated.
  93         * aarch64-opc-2.c: Regenerated.
  94
  95 2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  96
  97         * aarch64-tbl.h (struct aarch64_opcode): Add new WFET instruction encoding
  98         and operand description.
  99         * aarch64-asm-2.c: Regenerated.
 100         * aarch64-dis-2.c: Regenerated.
 101         * aarch64-opc-2.c: Regenerated.
 102
 103 2020-10-26  Cooper Qu <cooper.qu@linux.alibaba.com>
 104
 105         * csky-opc.h (csky_v2_opcodes): Change plsl.u16 to plsl.16.
 106
 107 2020-10-26  Cooper Qu <cooper.qu@linux.alibaba.com>
 108
 109         * csky-dis.c (csky_output_operand): Add handler for
 110         OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
 111         * csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum.
 112         (OPRND_TYPE_IMM5b_VSH): New enum. (csky_v2_opcodes): Fix and add
 113         some instructions for VDSPV1.
 114
 115 2020-10-26  Lili Cui  <lili.cui@intel.com>
 116
 117         * i386-dis.c: Change "XV" to print "{vex}" pseudo prefix.
 118
 119 2020-10-23  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 120
 121         * aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter.
 122         * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter
 123         ins_barrier_dsb_nx.
 124         * aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor.
 125         * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor
 126         ext_barrier_dsb_nx.
 127         * aarch64-opc.c (aarch64_print_operand): New options table
 128         aarch64_barrier_dsb_nxs_options.
 129         * aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs.
 130         * aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier
 131         Armv8.7-a instruction.
 132         * aarch64-asm-2.c: Regenerated.
 133         * aarch64-dis-2.c: Regenerated.
 134         * aarch64-opc-2.c: Regenerated.
 135
 136 2020-10-22  H.J. Lu  <hongjiu.lu@intel.com>
 137
 138         * po/es.po: Remove the duplicated entry.
 139
 140 2020-10-20  Dr. David Alan Gilbert  <dgilbert@redhat.com>
 141
 142         * po/es.po: Fix printf format.
 143
 144 2020-10-20  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 145
 146         * i386-dis.c (rm_table): Add tlbsync, snp, invlpgb.
 147         * i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS,
 148         CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS.
 149         Add CPU_ZNVER3_FLAGS.
 150         (cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
 151         * i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
 152         * i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate,
 153         rmpupdate, rmpadjust.
 154         * i386-init.h: Re-generated.
 155         * i386-tbl.h: Re-generated.
 156
 157 2020-10-16  Lili Cui  <lili.cui@intel.com>
 158
 159         * i386-opc.tbl: Rename CpuVEX_PREFIX to PseudoVexPrefix
 160         and move it from cpu_flags to opcode_modifiers.
 161         Use VexW0 and VexVVVV in the AVX-VNNI instructions.
 162         * i386-gen.c: Likewise.
 163         * i386-opc.h: Likewise.
 164         * i386-opc.h: Likewise.
 165         * i386-init.h: Regenerated.
 166         * i386-tbl.h: Likewise.
 167
 168 2020-10-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 169
 170         * aarch64-tbl.h (ARMV8_7): New macro.
 171
 172 2020-10-14  H.J. Lu  <hongjiu.lu@intel.com>
 173             Lili Cui  <lili.cui@intel.com>
 174
 175         * i386-dis.c (PREFIX_VEX_0F3850): New.
 176         (PREFIX_VEX_0F3851): Likewise.
 177         (PREFIX_VEX_0F3852): Likewise.
 178         (PREFIX_VEX_0F3853): Likewise.
 179         (VEX_W_0F3850_P_2): Likewise.
 180         (VEX_W_0F3851_P_2): Likewise.
 181         (VEX_W_0F3852_P_2): Likewise.
 182         (VEX_W_0F3853_P_2): Likewise.
 183         (prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851,
 184         PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853.
 185         (vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2,
 186         VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2.
 187         (putop): Add support for "XV" to print "{vex3}" pseudo prefix.
 188         * i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in
 189         CPU_UNKNOWN_FLAGS.  Add CPU_AVX_VNNI_FLAGS and
 190         CPU_ANY_AVX_VNNI_FLAGS.
 191         (cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX.
 192         * i386-opc.h (CpuAVX_VNNI): New.
 193         (CpuVEX_PREFIX): Likewise.
 194         (i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix.
 195         * i386-opc.tbl: Add Intel AVX VNNI instructions.
 196         * i386-init.h: Regenerated.
 197         * i386-tbl.h: Likewise.
 198
 199 2020-10-14  Lili Cui  <lili.cui@intel.com>
 200             H.J. Lu  <hongjiu.lu@intel.com>
 201
 202         * i386-dis.c (PREFIX_0F3A0F): New.
 203         (MOD_0F3A0F_PREFIX_1): Likewise.
 204         (REG_0F3A0F_PREFIX_1_MOD_3): Likewise.
 205         (RM_0F3A0F_P_1_MOD_3_REG_0): Likewise.
 206         (prefix_table): Add PREFIX_0F3A0F.
 207         (mod_table): Add MOD_0F3A0F_PREFIX_1.
 208         (reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3.
 209         (rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0.
 210         * i386-gen.c (cpu_flag_init): Add HRESET_FLAGS,
 211         CPU_ANY_HRESET_FLAGS.
 212         (cpu_flags): Add CpuHRESET.
 213         (output_i386_opcode): Allow 4 byte base_opcode.
 214         * i386-opc.h (enum): Add CpuHRESET.
 215         (i386_cpu_flags): Add cpuhreset.
 216         * i386-opc.tbl: Add Intel HRESET instruction.
 217         * i386-init.h: Regenerate.
 218         * i386-tbl.h: Likewise.
 219
 220 2020-10-14  Lili Cui  <lili.cui@intel.com>
 221
 222         * i386-dis.c (enum): Add
 223         PREFIX_MOD_3_0F01_REG_5_RM_4,
 224         PREFIX_MOD_3_0F01_REG_5_RM_5,
 225         PREFIX_MOD_3_0F01_REG_5_RM_6,
 226         PREFIX_MOD_3_0F01_REG_5_RM_7,
 227         X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
 228         X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
 229         X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
 230         X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
 231         X86_64_0FC7_REG_6_MOD_3_PREFIX_1.
 232         (prefix_table): New instructions (see prefixes above).
 233         (rm_table): Likewise
 234         * i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS,
 235         CPU_ANY_UINTR_FLAGS.
 236         (cpu_flags): Add CpuUINTR.
 237         * i386-opc.h (enum): Add CpuUINTR.
 238         (i386_cpu_flags): Add cpuuintr.
 239         * i386-opc.tbl: Add UINTR insns.
 240         * i386-init.h: Regenerate.
 241         * i386-tbl.h: Likewise.
 242
 243 2020-10-14  H.J. Lu  <hongjiu.lu@intel.com>
 244
 245         * i386-gen.c (process_i386_opcode_modifier): Return 1 for
 246         non-VEX/EVEX/prefix encoding.
 247         (output_i386_opcode): Fail if non-VEX/EVEX/prefix base_opcode
 248         has a prefix byte.
 249         * i386-opc.tbl: Replace the prefix byte in non-VEX/EVEX
 250         base_opcode with PREFIX_0X66, PREFIX_0XF2 or PREFIX_0XF3.
 251         * i386-tbl.h: Regenerated.
 252
 253 2020-10-13  H.J. Lu  <hongjiu.lu@intel.com>
 254
 255         * i386-gen.c (opcode_modifiers): Replace VexOpcode with
 256         OpcodePrefix.
 257         * i386-opc.h (VexOpcode): Renamed to ...
 258         (OpcodePrefix): This.
 259         (PREFIX_NONE): New.
 260         (PREFIX_0X66): Likewise.
 261         (PREFIX_0XF2): Likewise.
 262         (PREFIX_0XF3): Likewise.
 263         * i386-opc.tbl (Prefix_0X66): New.
 264         (Prefix_0XF2): Likewise.
 265         (Prefix_0XF3): Likewise.
 266         Replace VexOpcode= with OpcodePrefix=.  Use Prefix_0X66 on xorpd.
 267         Use Prefix_0XF3 on cvtdq2pd.  Use Prefix_0XF2 on cvtpd2dq.
 268         * i386-tbl.h: Regenerated.
 269
 270 2020-10-08  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 271
 272         * aarch64-opc.c: Add BRBE system registers.
 273
 274 2020-10-08  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 275
 276         * aarch64-opc.c: New CSRE system registers defined.
 277
 278 2020-10-05  Samanta Navarro  <ferivoz@riseup.net>
 279
 280         * cgen-asm.c: Fix spelling mistakes.
 281         * cgen-dis.c: Fix spelling mistakes.
 282         * tic30-dis.c: Fix spelling mistakes.
 283
 284 2020-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 285
 286         PR binutils/26704
 287         * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
 288
 289 2020-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 290
 291         PR binutils/26705
 292         * i386-dis.c (print_insn): Clear modrm if not needed.
 293         (putop): Check need_modrm for modrm.mod != 3.  Don't check
 294         need_modrm for modrm.mod == 3.
 295
 296 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 297
 298         * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
 299         TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
 300         TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
 301         TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
 302         TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
 303         TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
 304         TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
 305         TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
 306         WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
 307         TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
 308         TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
 309         TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR,  TRCTSCTLR, TRCVDARCCTLR,
 310         TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
 311         TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
 312
 313 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 314
 315         * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
 316
 317 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 318
 319         * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
 320         TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
 321
 322 2020-09-26  Alan Modra  <amodra@gmail.com>
 323
 324         * csky-opc.h: Formatting.
 325         (GENERAL_REG_BANK): Correct spelling.  Update use throughout file.
 326         (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
 327         and shift 1u.
 328         (get_register_number): Likewise.
 329         * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
 330
 331 2020-09-24  Lili Cui  <lili.cui@intel.com>
 332
 333         PR 26654
 334         * i386-dis.c (enum): Put MOD_VEX_0F38* together.
 335
 336 2020-09-24  Andrew Burgess <andrew.burgess@embecosm.com>
 337
 338         * csky-dis.c (csky_output_operand): Enclose body of if in curly
 339         braces.
 340
 341 2020-09-24  Lili Cui  <lili.cui@intel.com>
 342
 343         * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
 344         PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
 345         X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
 346         X86_64_0F01_REG_1_RM_7_P_2.
 347         (prefix_table): Likewise.
 348         (x86_64_table): Likewise.
 349         (rm_table): Likewise.
 350         * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
 351         and CPU_ANY_TDX_FLAGS.
 352         (cpu_flags): Add CpuTDX.
 353         * i386-opc.h (enum): Add CpuTDX.
 354         (i386_cpu_flags): Add cputdx.
 355         * i386-opc.tbl: Add TDX insns.
 356         * i386-init.h: Regenerate.
 357         * i386-tbl.h: Likewise.
 358
 359 2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
 360
 361         * csky-dis.c (using_abi): New.
 362         (parse_csky_dis_options): New function.
 363         (get_gr_name): New function.
 364         (get_cr_name): New function.
 365         (csky_output_operand): Use get_gr_name and get_cr_name to
 366         disassemble and add handle of OPRND_TYPE_IMM5b_LS.
 367         (print_insn_csky): Parse disassembler options.
 368         * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
 369         (GENARAL_REG_BANK): Define.
 370         (REG_SUPPORT_ALL): Define.
 371         (REG_SUPPORT_ALL): New.
 372         (ASH): Define.
 373         (REG_SUPPORT_A): Define.
 374         (REG_SUPPORT_B): Define.
 375         (REG_SUPPORT_C): Define.
 376         (REG_SUPPORT_D): Define.
 377         (REG_SUPPORT_E): Define.
 378         (csky_abiv1_general_regs): New.
 379         (csky_abiv1_control_regs): New.
 380         (csky_abiv2_general_regs): New.
 381         (csky_abiv2_control_regs): New.
 382         (get_register_name): New function.
 383         (get_register_number): New function.
 384         (csky_get_general_reg_name): New function.
 385         (csky_get_general_regno): New function.
 386         (csky_get_control_reg_name): New function.
 387         (csky_get_control_regno): New function.
 388         (csky_v2_opcodes): Prefer two oprerans format for bclri and
 389         bseti, strengthen the operands legality check of addc, zext
 390         and sext.
 391
 392 2020-09-23  Lili Cui  <lili.cui@intel.com>
 393
 394         * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
 395         MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
 396         MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
 397         MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
 398         PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
 399         (reg_table): New instructions (see prefixes above).
 400         (prefix_table): Likewise.
 401         (three_byte_table): Likewise.
 402         (mod_table): Likewise
 403         * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
 404         CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
 405         (cpu_flags): Likewise.
 406         (operand_type_init): Likewise.
 407         * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
 408         (i386_cpu_flags): Add cpukl and cpuwide_kl.
 409         * i386-opc.tbl: Add KL and WIDE_KL insns.
 410         * i386-init.h: Regenerate.
 411         * i386-tbl.h: Likewise.
 412
 413 2020-09-21  Alan Modra  <amodra@gmail.com>
 414
 415         * rx-dis.c (flag_names): Add missing comma.
 416         (register_names, flag_names, double_register_names),
 417         (double_register_high_names, double_register_low_names),
 418         (double_control_register_names, double_condition_names): Remove
 419         trailing commas.
 420
 421 2020-09-18  David Faust  <david.faust@oracle.com>
 422
 423         * bpf-desc.c: Regenerate.
 424         * bpf-desc.h: Likewise.
 425         * bpf-opc.c: Likewise.
 426         * bpf-opc.h: Likewise.
 427
 428 2020-09-16  Andrew Burgess <andrew.burgess@embecosm.com>
 429
 430         * csky-dis.c (csky_get_disassembler): Don't return NULL when there
 431         is no BFD.
 432
 433 2020-09-16  Alan Modra  <amodra@gmail.com>
 434
 435         * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
 436
 437 2020-09-10  Nick Clifton  <nickc@redhat.com>
 438
 439         * ppc-dis.c (ppc_symbol_is_valid): New function.  Returns false
 440         for hidden, local, no-type symbols.
 441         (disassemble_init_powerpc): Point the symbol_is_valid field in the
 442         info structure at the new function.
 443
 444 2020-09-10  Cooper Qu  <cooper.qu@linux.alibaba.com>
 445
 446         * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
 447         * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
 448         opcode fixing.
 449
 450 2020-09-10  Nick Clifton  <nickc@redhat.com>
 451
 452         * csky-dis.c (csky_output_operand): Coerce the immediate values to
 453         long before printing.
 454
 455 2020-09-10  Alan Modra  <amodra@gmail.com>
 456
 457         * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
 458
 459 2020-09-07  Cooper Qu  <cooper.qu@linux.alibaba.com>
 460
 461         * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
 462         ISA flag.
 463
 464 2020-09-07  Cooper Qu  <cooper.qu@linux.alibaba.com>
 465
 466         * csky-dis.c (csky_output_operand): Add handlers for
 467         OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
 468         OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
 469         to support FPUV3 instructions.
 470         * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
 471         OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
 472         OPRND_TYPE_DFLOAT_FMOVI.
 473         (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
 474          OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
 475          OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
 476          OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
 477          OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
 478          OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
 479          OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
 480          OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
 481          OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
 482          OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
 483          OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
 484          OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
 485          OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
 486         (csky_v2_opcodes): Add FPUV3 instructions.
 487
 488 2020-09-08  Alex Coplan  <alex.coplan@arm.com>
 489
 490         * aarch64-dis.c (print_operands): Pass CPU features to
 491         aarch64_print_operand().
 492         * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
 493         preferred disassembly of system registers.
 494         (SR_RNG): Refactor to use new SR_FEAT2 macro.
 495         (SR_FEAT2): New.
 496         (SR_V8_1_A): New.
 497         (SR_V8_4_A): New.
 498         (SR_V8_A): New.
 499         (SR_V8_R): New.
 500         (SR_EXPAND_ELx): New.
 501         (SR_EXPAND_EL12): New.
 502         (aarch64_sys_regs): Specify which registers are only on
 503         A-profile, add R-profile system registers.
 504         (ENC_BARLAR): New.
 505         (PRBARn_ELx): New.
 506         (PRLARn_ELx): New.
 507         (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
 508         Armv8-R AArch64.
 509
 510 2020-09-08  Alex Coplan  <alex.coplan@arm.com>
 511
 512         * aarch64-tbl.h (aarch64_feature_v8_r): New.
 513         (ARMV8_R): New.
 514         (V8_R_INSN): New.
 515         (aarch64_opcode_table): Add dfb.
 516         * aarch64-opc-2.c: Regenerate.
 517         * aarch64-asm-2.c: Regenerate.
 518         * aarch64-dis-2.c: Regenerate.
 519
 520 2020-09-08  Alex Coplan  <alex.coplan@arm.com>
 521
 522         * aarch64-dis.c (arch_variant): New.
 523         (determine_disassembling_preference): Disassemble according to
 524         arch variant.
 525         (select_aarch64_variant): New.
 526         (print_insn_aarch64): Set feature set.
 527
 528 2020-09-02  Alan Modra  <amodra@gmail.com>
 529
 530         * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
 531         (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
 532         (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
 533         (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
 534         (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
 535         (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
 536         (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
 537         for value parameter and update code to suit.
 538         (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
 539         (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
 540
 541 2020-09-02  Alan Modra  <amodra@gmail.com>
 542
 543         * i386-dis.c (OP_E_memory): Don't cast to signed type when
 544         negating.
 545         (get32, get32s): Use unsigned types in shift expressions.
 546
 547 2020-09-02  Alan Modra  <amodra@gmail.com>
 548
 549         * csky-dis.c (print_insn_csky): Use unsigned type for "given".
 550
 551 2020-09-02  Alan Modra  <amodra@gmail.com>
 552
 553         * crx-dis.c: Whitespace.
 554         (print_arg): Use unsigned type for longdisp and mask variables,
 555         and for left shift constant.
 556
 557 2020-09-02  Alan Modra  <amodra@gmail.com>
 558
 559         * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
 560         * bpf-ibld.c: Regenerate.
 561         * epiphany-ibld.c: Regenerate.
 562         * fr30-ibld.c: Regenerate.
 563         * frv-ibld.c: Regenerate.
 564         * ip2k-ibld.c: Regenerate.
 565         * iq2000-ibld.c: Regenerate.
 566         * lm32-ibld.c: Regenerate.
 567         * m32c-ibld.c: Regenerate.
 568         * m32r-ibld.c: Regenerate.
 569         * mep-ibld.c: Regenerate.
 570         * mt-ibld.c: Regenerate.
 571         * or1k-ibld.c: Regenerate.
 572         * xc16x-ibld.c: Regenerate.
 573         * xstormy16-ibld.c: Regenerate.
 574
 575 2020-09-02  Alan Modra  <amodra@gmail.com>
 576
 577         * bfin-dis.c (MASKBITS): Use SIGNBIT.
 578
 579 2020-09-02  Cooper Qu  <cooper.qu@linux.alibaba.com>
 580
 581         * csky-opc.h (csky_v2_opcodes): Move divul and divsl
 582         to CSKYV2_ISA_3E3R3 instruction set.
 583
 584 2020-09-02  Cooper Qu  <cooper.qu@linux.alibaba.com>
 585
 586         * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
 587
 588 2020-09-01  Alan Modra  <amodra@gmail.com>
 589
 590         * mep-ibld.c: Regenerate.
 591
 592 2020-08-31  Cooper Qu  <cooper.qu@linux.alibaba.com>
 593
 594         * csky-dis.c (csky_output_operand): Assign dis_info.value for
 595         OPRND_TYPE_VREG.
 596
 597 2020-08-30  Alan Modra  <amodra@gmail.com>
 598
 599         * cr16-dis.c: Formatting.
 600         (parameter): Delete struct typedef.  Use dwordU instead
 601         throughout file.
 602         (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
 603         and tbitb.
 604         (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
 605
 606 2020-08-29  Alan Modra  <amodra@gmail.com>
 607
 608         PR 26446
 609         * csky-opc.h (MAX_OPRND_NUM): Define to 5.
 610         (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
 611
 612 2020-08-28  Alan Modra  <amodra@gmail.com>
 613
 614         PR 26449
 615         PR 26450
 616         * cgen-ibld.in (insert_1): Use 1UL in forming mask.
 617         (extract_normal): Likewise.
 618         (insert_normal): Likewise, and move past zero length test.
 619         (put_insn_int_value): Handle mask for zero length, use 1UL.
 620         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 621         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 622         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 623         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 624
 625 2020-08-28  Cooper Qu  <cooper.qu@linux.alibaba.com>
 626
 627         * csky-dis.c (CSKY_DEFAULT_ISA): Define.
 628         (csky_dis_info): Add member isa.
 629         (csky_find_inst_info): Skip instructions that do not belong to
 630         current CPU.
 631         (csky_get_disassembler): Get infomation from attribute section.
 632         (print_insn_csky): Set defualt ISA flag.
 633         * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
 634         * csky-opc.h (struct csky_opcode): Change isa_flag16 and
 635         isa_flag32'type to unsigned 64 bits.
 636
 637 2020-08-26  Jose E. Marchesi  <jemarch@gnu.org>
 638
 639         * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
 640
 641 2020-08-26  David Faust  <david.faust@oracle.com>
 642
 643         * bpf-desc.c: Regenerate.
 644         * bpf-desc.h: Likewise.
 645         * bpf-opc.c: Likewise.
 646         * bpf-opc.h: Likewise.
 647         * disassemble.c (disassemble_init_for_target): Set bits for xBPF
 648         ISA when appropriate.
 649
 650 2020-08-25  Alan Modra  <amodra@gmail.com>
 651
 652         PR 26504
 653         * vax-dis.c (parse_disassembler_options): Always add at least one
 654         to entry_addr_total_slots.
 655
 656 2020-08-24  Cooper Qu  <cooper.qu@linux.alibaba.com>
 657
 658         * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
 659         in other CPUs to speed up disassembling.
 660         * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
 661         Change plsli.u16 to plsli.16, change sync's operand format.
 662
 663 2020-08-21  Cooper Qu  <cooper.qu@linux.alibaba.com>
 664
 665         * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
 666
 667 2020-08-21  Nick Clifton  <nickc@redhat.com>
 668
 669         * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
 670         symbols.
 671
 672 2020-08-21  Cooper Qu  <cooper.qu@linux.alibaba.com>
 673
 674         * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
 675
 676 2020-08-19  Alan Modra  <amodra@gmail.com>
 677
 678         * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
 679         vcmpuq and xvtlsbb.
 680
 681 2020-08-18  Peter Bergner  <bergner@linux.ibm.com>
 682
 683         * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
 684         <xvcvbf16spn>: ...to this.
 685
 686 2020-08-12  Alex Coplan  <alex.coplan@arm.com>
 687
 688         * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
 689
 690 2020-08-12  Nick Clifton  <nickc@redhat.com>
 691
 692         * po/sr.po: Updated Serbian translation.
 693
 694 2020-08-11  Alan Modra  <amodra@gmail.com>
 695
 696         * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
 697
 698 2020-08-10  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 699
 700         * aarch64-opc.c (aarch64_print_operand):
 701         (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
 702         (aarch64_sys_reg_supported_p): Function removed.
 703         (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
 704         (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
 705         into this function.
 706
 707 2020-08-10  Alan Modra  <amodra@gmail.com>
 708
 709         * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
 710         instructions.
 711
 712 2020-08-10  Alan Modra  <amodra@gmail.com>
 713
 714         * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
 715         Enable icbt for power5, miso for power8.
 716
 717 2020-08-10  Alan Modra  <amodra@gmail.com>
 718
 719         * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
 720         mtvsrd, and similarly for mfvsrd.
 721
 722 2020-08-04  Christian Groessler  <chris@groessler.org>
 723             Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
 724
 725         * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
 726         opcodes (special "out" to absolute address).
 727         * z8k-opc.h: Regenerate.
 728
 729 2020-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 730
 731         PR gas/26305
 732         * i386-opc.h (Prefix_Disp8): New.
 733         (Prefix_Disp16): Likewise.
 734         (Prefix_Disp32): Likewise.
 735         (Prefix_Load): Likewise.
 736         (Prefix_Store): Likewise.
 737         (Prefix_VEX): Likewise.
 738         (Prefix_VEX3): Likewise.
 739         (Prefix_EVEX): Likewise.
 740         (Prefix_REX): Likewise.
 741         (Prefix_NoOptimize): Likewise.
 742         * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes.  Add {disp16}.
 743         * i386-tbl.h: Regenerated.
 744
 745 2020-07-29  Andreas Arnez  <arnez@linux.ibm.com>
 746
 747         * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
 748         default case with abort() instead of printing an error message and
 749         continuing, to avoid a maybe-uninitialized warning.
 750
 751 2020-07-24  Nick Clifton  <nickc@redhat.com>
 752
 753         * po/de.po: Updated German translation.
 754
 755 2020-07-21  Jan Beulich  <jbeulich@suse.com>
 756
 757         * i386-dis.c (OP_E_memory): Revert previous change.
 758
 759 2020-07-15  H.J. Lu  <hongjiu.lu@intel.com>
 760
 761         PR gas/26237
 762         * i386-dis.c (OP_E_memory): Don't display eiz with no scale
 763         without base nor index registers.
 764
 765 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 766
 767         * i386-dis.c (putop): Move 'V' and 'W' handling.
 768
 769 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 770
 771         * i386-dis.c (dis386): Adjust 'V' description. Use P-based
 772         construct for push/pop of register.
 773         (putop): Honor cond when handling 'P'. Drop handling of plain
 774         'V'.
 775
 776 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 777
 778         * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
 779         description. Drop '&' description. Use P for push of immediate,
 780         pushf/popf, enter, and leave. Use %LP for lret/retf.
 781         (dis386_twobyte): Use P for push/pop of fs/gs.
 782         (reg_table): Use P for push/pop. Use @ for near call/jmp.
 783         (x86_64_table): Use P for far call/jmp.
 784         (putop): Drop handling of 'U' and '&'. Move and adjust handling
 785         of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
 786         labels.
 787         (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
 788         and dqw_mode (unconditional).
 789
 790 2020-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 791
 792         PR gas/26237
 793         * i386-dis.c (OP_E_memory): Without base nor index registers,
 794         32-bit displacement to 64 bits.
 795
 796 2020-07-14  Claudiu Zissulescu  <claziss@gmail.com>
 797
 798         * arc-dis.c (print_insn_arc): Detect and emit a warning when a
 799         faulty double register pair is detected.
 800
 801 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 802
 803         * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
 804
 805 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 806
 807         * i386-dis.c (OP_R, Rm): Delete.
 808         (MOD_0F24, MOD_0F26): Rename to ...
 809         (X86_64_0F24, X86_64_0F26): ... respectively.
 810         (dis386): Update 'L' and 'Z' comments.
 811         (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
 812         table references.
 813         (mod_table): Move opcode 0F24 and 0F26 entries ...
 814         (x86_64_table): ... here.
 815         (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
 816         'Z' case block.
 817
 818 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 819
 820         * i386-dis.c (Rd, Rdq, MaskR): Delete.
 821         (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
 822         MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
 823         MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
 824         MOD_EVEX_0F387C): New enumerators.
 825         (reg_table): Use Edq for rdssp.
 826         (prefix_table): Use Edq for incssp.
 827         (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
 828         kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
 829         ktest*, and kshift*. Use Edq / MaskE for kmov*.
 830         * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
 831         * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
 832         0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
 833         * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
 834         0F3828_P_1 and 0F3838_P_1.
 835         * i386-dis-evex-w.h: Reference mod_table[] for opcodes
 836         0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
 837
 838 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 839
 840         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
 841         PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
 842         PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
 843         PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
 844         PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
 845         PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
 846         (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
 847         VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
 848         VEX_LEN_0F38F3_R_3_P_0): Rename to ...
 849         (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
 850         VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
 851         (reg_table, prefix_table, three_byte_table, vex_table,
 852         vex_len_table, mod_table, rm_table): Replace / remove respective
 853         entries.
 854         (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
 855         of PREFIX_DATA in used_prefixes.
 856
 857 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 858
 859         * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
 860         MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
 861         MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
 862         MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
 863         (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
 864         MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
 865         (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
 866         VEX_W_0F3A33_L_0): Delete.
 867         (dis386): Adjust "BW" description.
 868         (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
 869         0F3A31, 0F3A32, and 0F3A33.
 870         (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
 871         entries.
 872         (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
 873         entries.
 874
 875 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 876
 877         * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
 878         PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
 879         PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
 880         PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
 881         PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
 882         PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
 883         PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
 884         PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
 885         PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
 886         PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
 887         PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
 888         PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
 889         PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
 890         PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
 891         PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
 892         PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
 893         PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
 894         PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
 895         PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
 896         PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
 897         PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
 898         PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
 899         PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
 900         PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
 901         PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
 902         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 903         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 904         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
 905         PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
 906         PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 907         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 908         PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
 909         PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
 910         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 911         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 912         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 913         PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
 914         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 915         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 916         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
 917         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 918         PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
 919         PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
 920         PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
 921         PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
 922         PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
 923         PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
 924         PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
 925         PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
 926         PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
 927         PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
 928         PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
 929         PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
 930         PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
 931         PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
 932         PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
 933         PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
 934         PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 935         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 936         PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
 937         PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
 938         PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
 939         PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
 940         PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
 941         PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
 942         PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
 943         PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
 944         PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
 945         PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
 946         PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
 947         PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
 948         PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
 949         PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
 950         PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
 951         PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
 952         PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
 953         PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
 954         PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
 955         PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
 956         PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
 957         PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
 958         PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
 959         PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
 960         PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
 961         PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
 962         PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
 963         PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
 964         PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
 965         PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
 966         PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
 967         PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
 968         PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
 969         PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
 970         PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
 971         PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
 972         PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
 973         PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
 974         PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
 975         PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
 976         PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
 977         PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
 978         PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
 979         PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
 980         PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
 981         PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
 982         PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 983         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 984         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 985         PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
 986         PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
 987         PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
 988         PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
 989         PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
 990         PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
 991         PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
 992         PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
 993         PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 994         PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
 995         PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
 996         PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
 997         PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
 998         PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
 999         PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
1000         PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
1001         PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
1002         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
1003         PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
1004         PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
1005         PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
1006         PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
1007         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
1008         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
1009         PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
1010         PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
1011         PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
1012         PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
1013         PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
1014         PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
1015         PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
1016         PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
1017         PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
1018         PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
1019         PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
1020         PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
1021         PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
1022         PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
1023         PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
1024         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
1025         PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
1026         PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
1027         PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
1028         PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
1029         PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
1030         PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
1031         PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
1032         PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
1033         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
1034         (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
1035         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
1036         MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
1037         MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
1038         MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
1039         MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
1040         MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
1041         MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
1042         MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
1043         MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
1044         MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
1045         MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1046         MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1047         MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
1048         MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
1049         VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
1050         VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
1051         VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
1052         VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
1053         VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
1054         VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
1055         VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
1056         VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
1057         VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
1058         VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
1059         VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
1060         VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
1061         VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
1062         EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
1063         EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
1064         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
1065         EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
1066         EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
1067         EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1068         EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
1069         EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1070         EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1071         EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
1072         EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
1073         EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
1074         EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
1075         EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
1076         EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1077         EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
1078         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1079         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1080         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1081         EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
1082         EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
1083         EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
1084         EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
1085         EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
1086         EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
1087         EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
1088         EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
1089         VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
1090         VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
1091         VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
1092         VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
1093         VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
1094         VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
1095         VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
1096         VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
1097         VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
1098         VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
1099         VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
1100         VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
1101         VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
1102         VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
1103         VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
1104         VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
1105         VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
1106         VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
1107         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
1108         EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
1109         EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
1110         EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
1111         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
1112         EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
1113         EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
1114         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
1115         EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
1116         EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
1117         EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
1118         EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
1119         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
1120         EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
1121         EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
1122         EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
1123         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
1124         EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
1125         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
1126         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
1127         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
1128         EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1129         EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
1130         EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
1131         EVEX_W_0F3A72_P_2): Rename to ...
1132         (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
1133         MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
1134         MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
1135         MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
1136         MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
1137         MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
1138         MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
1139         MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
1140         MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
1141         MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
1142         MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
1143         VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
1144         VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
1145         VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
1146         VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
1147         VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
1148         VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
1149         VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
1150         VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
1151         VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
1152         EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
1153         EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
1154         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
1155         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
1156         EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
1157         EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
1158         EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
1159         EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
1160         EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
1161         EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
1162         EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
1163         EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
1164         EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
1165         EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
1166         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
1167         EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
1168         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
1169         EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
1170         EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
1171         EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
1172         EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
1173         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
1174         EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
1175         EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
1176         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
1177         VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
1178         VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
1179         VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
1180         VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
1181         VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
1182         VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
1183         VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
1184         VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
1185         VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
1186         VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
1187         VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
1188         VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
1189         VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
1190         EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
1191         EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
1192         EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
1193         EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
1194         EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
1195         EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
1196         EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
1197         EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
1198         EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
1199         EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
1200         EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
1201         EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
1202         EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
1203         EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
1204         respectively.
1205         (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
1206         vex_w_table, mod_table): Replace / remove respective entries.
1207         (print_insn): Move up dp->prefix_requirement handling. Handle
1208         PREFIX_DATA.
1209         * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
1210         i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
1211         Replace / remove respective entries.
1212
1213 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1214
1215         * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
1216         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
1217         (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
1218         vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
1219         Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
1220         the latter two.
1221         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1222         0F2C, 0F2D, 0F2E, and 0F2F.
1223         * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
1224         0F2F table entries.
1225
1226 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1227
1228         * i386-dis.c (OP_VexR, VexScalarR): New.
1229         (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
1230         XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
1231         need_vex_reg): Delete.
1232         (prefix_table): Replace VexScalar by VexScalarR and
1233         XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1234         EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1235         (vex_len_table): Replace EXqVexScalarS by EXqS.
1236         (get_valid_dis386): Don't set need_vex_reg.
1237         (print_insn): Don't initialize need_vex_reg.
1238         (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
1239         q_scalar_swap_mode cases.
1240         (OP_EX): Don't check for d_scalar_swap_mode and
1241         q_scalar_swap_mode.
1242         (OP_VEX): Done check need_vex_reg.
1243         * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
1244         XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1245         EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1246
1247 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1248
1249         * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
1250         (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
1251         VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
1252         VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
1253         (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
1254         VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
1255         VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
1256         VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
1257         (vex_table): Replace Vex128 by Vex.
1258         (vex_len_table): Likewise. Adjust referenced enum names.
1259         (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
1260         referenced enum names.
1261         (OP_VEX): Drop vex128_mode and vex256_mode cases.
1262         * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
1263
1264 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1265
1266         * i386-dis.c (dis386): "LW" description now applies to "DQ".
1267         (putop): Handle "DQ". Don't handle "LW" anymore.
1268         (prefix_table, mod_table): Replace %LW by %DQ.
1269         * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
1270
1271 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1272
1273         * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
1274         dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
1275         d_scalar_swap_mode case handling. Move shift adjsutment into
1276         the case its applicable to.
1277
1278 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1279
1280         * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
1281         (EXbScalar, EXwScalar): Fold to ...
1282         (EXbwUnit): ... this.
1283         (b_scalar_mode, w_scalar_mode): Fold to ...
1284         (bw_unit_mode): ... this.
1285         (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
1286         w_scalar_mode handling by bw_unit_mode one.
1287         * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
1288         ...
1289         * i386-dis-evex-prefix.h: ... here.
1290
1291 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1292
1293         * i386-dis.c (PCMPESTR_Fixup): Delete.
1294         (dis386): Adjust "LQ" description.
1295         (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
1296         cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
1297         PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
1298         vpcmpestrm, and vpcmpestri.
1299         (putop): Honor "cond" when handling LQ.
1300         * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
1301         vcvtsi2ss and vcvtusi2ss.
1302         * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
1303         vcvtsi2sd and vcvtusi2sd.
1304
1305 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1306
1307         * i386-dis.c (VCMP_Fixup, VCMP): Delete.
1308         (simd_cmp_op): Add const.
1309         (vex_cmp_op): Move up and drop initial 8 entries. Add const.
1310         (CMP_Fixup): Handle VEX case.
1311         (prefix_table): Replace VCMP by CMP.
1312         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
1313
1314 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1315
1316         * i386-dis.c (MOVBE_Fixup): Delete.
1317         (Mv): Define.
1318         (prefix_table): Use Mv for movbe entries.
1319
1320 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1321
1322         * i386-dis.c (CRC32_Fixup): Delete.
1323         (prefix_table): Use Eb/Ev for crc32 entries.
1324
1325 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1326
1327         * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
1328         Conditionalize invocations of "USED_REX (0)".
1329
1330 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1331
1332         * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
1333         CH, DH, BH, AX, DX): Delete.
1334         (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
1335         eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
1336         dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
1337
1338 2020-07-10  Lili Cui  <lili.cui@intel.com>
1339
1340         * i386-dis.c (TMM): New.
1341         (EXtmm): Likewise.
1342         (VexTmm): Likewise.
1343         (MVexSIBMEM): Likewise.
1344         (tmm_mode): Likewise.
1345         (vex_sibmem_mode): Likewise.
1346         (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
1347         (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
1348         (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
1349         (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
1350         (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
1351         (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
1352         (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
1353         (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
1354         (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
1355         (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
1356         (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
1357         (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
1358         (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
1359         (PREFIX_VEX_0F3849_X86_64): Likewise.
1360         (PREFIX_VEX_0F384B_X86_64): Likewise.
1361         (PREFIX_VEX_0F385C_X86_64): Likewise.
1362         (PREFIX_VEX_0F385E_X86_64): Likewise.
1363         (X86_64_VEX_0F3849): Likewise.
1364         (X86_64_VEX_0F384B): Likewise.
1365         (X86_64_VEX_0F385C): Likewise.
1366         (X86_64_VEX_0F385E): Likewise.
1367         (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
1368         (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
1369         (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
1370         (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
1371         (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
1372         (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
1373         (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
1374         (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
1375         (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
1376         (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
1377         (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
1378         (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
1379         (VEX_W_0F3849_X86_64_P_0): Likewise.
1380         (VEX_W_0F3849_X86_64_P_2): Likewise.
1381         (VEX_W_0F3849_X86_64_P_3): Likewise.
1382         (VEX_W_0F384B_X86_64_P_1): Likewise.
1383         (VEX_W_0F384B_X86_64_P_2): Likewise.
1384         (VEX_W_0F384B_X86_64_P_3): Likewise.
1385         (VEX_W_0F385C_X86_64_P_1): Likewise.
1386         (VEX_W_0F385E_X86_64_P_0): Likewise.
1387         (VEX_W_0F385E_X86_64_P_1): Likewise.
1388         (VEX_W_0F385E_X86_64_P_2): Likewise.
1389         (VEX_W_0F385E_X86_64_P_3): Likewise.
1390         (names_tmm): Likewise.
1391         (att_names_tmm): Likewise.
1392         (intel_operand_size): Handle void_mode.
1393         (OP_XMM): Handle tmm_mode.
1394         (OP_EX): Likewise.
1395         (OP_VEX): Likewise.
1396         * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
1397         CpuAMX_BF16 and CpuAMX_TILE.
1398         (operand_type_shorthands): Add RegTMM.
1399         (operand_type_init): Likewise.
1400         (operand_types): Add Tmmword.
1401         (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1402         (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1403         * i386-opc.h (CpuAMX_INT8): New.
1404         (CpuAMX_BF16): Likewise.
1405         (CpuAMX_TILE): Likewise.
1406         (SIBMEM): Likewise.
1407         (Tmmword): Likewise.
1408         (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
1409         (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
1410         (i386_operand_type): Add tmmword.
1411         * i386-opc.tbl: Add AMX instructions.
1412         * i386-reg.tbl: Add AMX registers.
1413         * i386-init.h: Regenerated.
1414         * i386-tbl.h: Likewise.
1415
1416 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1417
1418         * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1419         (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1420         Rename to ...
1421         (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1422         REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1423         respectively.
1424         (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1425         VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1426         VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1427         VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1428         VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1429         VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1430         VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1431         VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1432         VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1433         VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1434         VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1435         VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1436         VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1437         VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1438         VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1439         VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1440         VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1441         VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1442         VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1443         VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1444         VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1445         VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1446         VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1447         VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1448         VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1449         VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1450         VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1451         VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1452         VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1453         VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1454         VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1455         VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1456         VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1457         VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1458         VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1459         VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1460         (reg_table): Re-order XOP entries. Adjust their operands.
1461         (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1462         08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1463         08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1464         09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1465         09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1466         09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1467         entries by references ...
1468         (vex_len_table): ... to resepctive new entries here. For several
1469         new and existing entries reference ...
1470         (vex_w_table): ... new entries here.
1471         (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1472
1473 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1474
1475         * i386-dis.c (XMVexScalarI4): Define.
1476         (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1477         VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1478         VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1479         (vex_len_table): Move scalar FMA4 entries ...
1480         (prefix_table): ... here.
1481         (OP_REG_VexI4): Handle scalar_mode.
1482         * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1483         * i386-tbl.h: Re-generate.
1484
1485 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1486
1487         * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1488         Vex_2src_2): Delete.
1489         (OP_VexW, VexW): New.
1490         (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1491         for shifts and rotates by register.
1492
1493 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1494
1495         * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1496         VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1497         OP_EX_VexReg): Delete.
1498         (OP_VexI4, VexI4): New.
1499         (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1500         (prefix_table): ... here.
1501         (print_insn): Drop setting of vex_w_done.
1502
1503 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1504
1505         * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1506         (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1507         (xop_table): Replace operands of 4-operand insns.
1508         (OP_REG_VexI4): Move VEX.W based operand swaping here.
1509
1510 2020-07-07  Claudiu Zissulescu  <claziss@synopsys.com>
1511
1512         * arc-opc.c (insert_rbd): New function.
1513         (RBD): Define.
1514         (RBDdup): Likewise.
1515         * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1516         instructions.
1517
1518 2020-07-07  Jan Beulich  <jbeulich@suse.com>
1519
1520         * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1521         EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1522         EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1523         EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1524         Delete.
1525         (putop): Handle "BW".
1526         * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1527         0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1528         and 0F3A3F ...
1529         * i386-dis-evex-prefix.h: ... here.
1530
1531 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1532
1533         * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1534         (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1535         VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1536         VEX_W_0FXOP_09_83): New enumerators.
1537         (xop_table): Reference the above.
1538         (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1539         (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1540         VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1541         (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1542
1543 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1544
1545         * i386-dis.c (EVEX_W_0F3838_P_1,
1546         EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1547         EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1548         EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1549         EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1550         EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1551         (putop): Centralize management of last[]. Delete SAVE_LAST.
1552         * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1553         0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1554         0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1555         * i386-dis-evex-prefix.h: here.
1556
1557 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1558
1559         * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1560         MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1561         MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1562         MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1563         enumerators.
1564         (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1565         EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1566         EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1567         EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1568         (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1569         EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1570         EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1571         EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1572         these, respectively.
1573         * i386-dis-evex-len.h: Adjust comments.
1574         * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1575         MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1576         MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1577         MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1578         MOD_EVEX_0F385B_P_2_W_1 table entries.
1579         * i386-dis-evex-w.h: Reference mod_table[] for
1580         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1581         EVEX_W_0F385B_P_2.
1582
1583 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1584
1585         * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1586         vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1587         EXymm.
1588         (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1589         Likewise. Mark 256-bit entries invalid.
1590
1591 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1592
1593         * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1594         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1595         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1596         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1597         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1598         PREFIX_EVEX_0F382B): Delete.
1599         (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1600         EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1601         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1602         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1603         EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1604         to ...
1605         (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1606         EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1607         EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1608         EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1609         respectively.
1610         * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1611         for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1612         0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1613         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1614         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1615         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1616         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1617         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1618         PREFIX_EVEX_0F382B): Remove table entries.
1619         * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1620         0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1621         0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1622
1623 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1624
1625         * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1626         EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1627         enumerators.
1628         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1629         EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1630         EVEX_LEN_0F3A01_P_2_W_1 table entries.
1631         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1632         entries.
1633
1634 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1635
1636         * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1637         EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1638         EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1639         EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1640         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1641         EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1642         EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1643         EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1644         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1645         entries.
1646
1647 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1648
1649         * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1650         (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1651         (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1652         respectively.
1653         (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1654         entries.
1655         * i386-dis-evex.h (evex_table): Reference VEX table entry for
1656         opcode 0F3A1D.
1657         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1658         entry.
1659         * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1660
1661 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1662
1663         * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1664         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1665         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1666         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1667         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1668         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1669         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1670         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1671         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1672         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1673         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1674         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1675         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1676         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1677         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1678         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1679         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1680         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1681         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1682         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1683         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1684         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1685         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1686         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1687         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1688         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1689         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1690         EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1691         EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1692         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1693         (prefix_table): Add EXxEVexR to FMA table entries.
1694         (OP_Rounding): Move abort() invocation.
1695         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1696         0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1697         0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1698         0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1699         0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1700         0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1701         0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1702         0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1703         0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1704         0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1705         0F3ACE, 0F3ACF.
1706         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1707         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1708         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1709         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1710         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1711         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1712         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1713         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1714         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1715         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1716         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1717         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1718         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1719         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1720         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1721         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1722         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1723         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1724         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1725         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1726         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1727         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1728         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1729         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1730         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1731         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1732         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1733         Delete table entries.
1734         * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1735         EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1736         EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1737         Likewise.
1738
1739 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1740
1741         * i386-dis.c (EXqScalarS): Delete.
1742         (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1743         * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1744
1745 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1746
1747         * i386-dis.c (safe-ctype.h): Include.
1748         (EXdScalar, EXqScalar): Delete.
1749         (d_scalar_mode, q_scalar_mode): Delete.
1750         (prefix_table, vex_len_table): Use EXxmm_md in place of
1751         EXdScalar and EXxmm_mq in place of EXqScalar.
1752         (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1753         d_scalar_mode and q_scalar_mode.
1754         * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1755         (vmovsd): Use EXxmm_mq.
1756
1757 2020-07-06  Yuri Chornoivan  <yurchor@ukr.net>
1758
1759         PR 26204
1760         * arc-dis.c: Fix spelling mistake.
1761         * po/opcodes.pot: Regenerate.
1762
1763 2020-07-06  Nick Clifton  <nickc@redhat.com>
1764
1765         * po/pt_BR.po: Updated Brazilian Portugugese translation.
1766         * po/uk.po: Updated Ukranian translation.
1767
1768 2020-07-04  Nick Clifton  <nickc@redhat.com>
1769
1770         * configure: Regenerate.
1771         * po/opcodes.pot: Regenerate.
1772
1773 2020-07-04  Nick Clifton  <nickc@redhat.com>
1774
1775         Binutils 2.35 branch created.
1776
1777 2020-07-02  H.J. Lu  <hongjiu.lu@intel.com>
1778
1779         * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1780         * i386-opc.h (VexSwapSources): New.
1781         (i386_opcode_modifier): Add vexswapsources.
1782         * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1783         with two source operands swapped.
1784         * i386-tbl.h: Regenerated.
1785
1786 2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
1787
1788         * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
1789         unprivileged CSR can also be initialized.
1790
1791 2020-06-29  Alan Modra  <amodra@gmail.com>
1792
1793         * arm-dis.c: Use C style comments.
1794         * cr16-opc.c: Likewise.
1795         * ft32-dis.c: Likewise.
1796         * moxie-opc.c: Likewise.
1797         * tic54x-dis.c: Likewise.
1798         * s12z-opc.c: Remove useless comment.
1799         * xgate-dis.c: Likewise.
1800
1801 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
1802
1803         * i386-opc.tbl: Add a blank line.
1804
1805 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
1806
1807         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1808         (VecSIB128): Renamed to ...
1809         (VECSIB128): This.
1810         (VecSIB256): Renamed to ...
1811         (VECSIB256): This.
1812         (VecSIB512): Renamed to ...
1813         (VECSIB512): This.
1814         (VecSIB): Renamed to ...
1815         (SIB): This.
1816         (i386_opcode_modifier): Replace vecsib with sib.
1817         * i386-opc.tbl (VecSIB128): New.
1818         (VecSIB256): Likewise.
1819         (VecSIB512): Likewise.
1820         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1821         and VecSIB512, respectively.
1822
1823 2020-06-26  Jan Beulich  <jbeulich@suse.com>
1824
1825         * i386-dis.c: Adjust description of I macro.
1826         (x86_64_table): Drop use of I.
1827         (float_mem): Replace use of I.
1828         (putop): Remove handling of I. Adjust setting/clearing of "alt".
1829
1830 2020-06-26  Jan Beulich  <jbeulich@suse.com>
1831
1832         * i386-dis.c: (print_insn): Avoid straight assignment to
1833         priv.orig_sizeflag when processing -M sub-options.
1834
1835 2020-06-25  Jan Beulich  <jbeulich@suse.com>
1836
1837         * i386-dis.c: Adjust description of J macro.
1838         (dis386, x86_64_table, mod_table): Replace J.
1839         (putop): Remove handling of J.
1840
1841 2020-06-25  Jan Beulich  <jbeulich@suse.com>
1842
1843         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1844
1845 2020-06-25  Jan Beulich  <jbeulich@suse.com>
1846
1847         * i386-dis.c: Adjust description of "LQ" macro.
1848         (dis386_twobyte): Use LQ for sysret.
1849         (putop): Adjust handling of LQ.
1850
1851 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
1852
1853         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1854         * riscv-dis.c: Include elfxx-riscv.h.
1855
1856 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
1857
1858         * i386-dis.c (prefix_table): Revert the last vmgexit change.
1859
1860 2020-06-17  Lili Cui  <lili.cui@intel.com>
1861
1862         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1863
1864 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
1865
1866         PR gas/26115
1867         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1868         * i386-opc.tbl: Likewise.
1869         * i386-tbl.h: Regenerated.
1870
1871 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
1872
1873         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1874
1875 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
1876
1877         * aarch64-opc.c (SYSREG): New macro for describing system registers.
1878         (SR_CORE): Likewise.
1879         (SR_FEAT): Likewise.
1880         (SR_RNG): Likewise.
1881         (SR_V8_1): Likewise.
1882         (SR_V8_2): Likewise.
1883         (SR_V8_3): Likewise.
1884         (SR_V8_4): Likewise.
1885         (SR_PAN): Likewise.
1886         (SR_RAS): Likewise.
1887         (SR_SSBS): Likewise.
1888         (SR_SVE): Likewise.
1889         (SR_ID_PFR2): Likewise.
1890         (SR_PROFILE): Likewise.
1891         (SR_MEMTAG): Likewise.
1892         (SR_SCXTNUM): Likewise.
1893         (aarch64_sys_regs): Refactor to store feature information in the table.
1894         (aarch64_sys_reg_supported_p): Collapse logic for system registers
1895         that now describe their own features.
1896         (aarch64_pstatefield_supported_p): Likewise.
1897
1898 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
1899
1900         * i386-dis.c (prefix_table): Fix a typo in comments.
1901
1902 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1903
1904         * i386-dis.c (rex_ignored): Delete.
1905         (ckprefix): Drop rex_ignored initialization.
1906         (get_valid_dis386): Drop setting of rex_ignored.
1907         (print_insn): Drop checking of rex_ignored. Don't record data
1908         size prefix as used with VEX-and-alike encodings.
1909
1910 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1911
1912         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1913         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1914         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1915         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1916         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1917         VEX_0F12, and VEX_0F16.
1918         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1919         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1920         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1921         from movlps and movhlps. New MOD_0F12_PREFIX_2,
1922         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1923         MOD_VEX_0F16_PREFIX_2 entries.
1924
1925 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1926
1927         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1928         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1929         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1930         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1931         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1932         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1933         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1934         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1935         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1936         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1937         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1938         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1939         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1940         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1941         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1942         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1943         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1944         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1945         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1946         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1947         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1948         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1949         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1950         EVEX_W_0FC6_P_2): Delete.
1951         (print_insn): Add EVEX.W vs embedded prefix consistency check
1952         to prefix validation.
1953         * i386-dis-evex.h (evex_table): Don't further descend for
1954         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1955         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1956         and 0F2B.
1957         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1958         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1959         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1960         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1961         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1962         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1963         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1964         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1965         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1966         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1967         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1968         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1969         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1970         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1971         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1972         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1973         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1974         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1975         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1976         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1977         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1978         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1979         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1980         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1981         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1982         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1983         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1984
1985 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1986
1987         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1988         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1989         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1990         vmovmskpX.
1991         (print_insn): Drop pointless check against bad_opcode. Split
1992         prefix validation into legacy and VEX-and-alike parts.
1993         (putop): Re-work 'X' macro handling.
1994
1995 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1996
1997         * i386-dis.c (MOD_0F51): Rename to ...
1998         (MOD_0F50): ... this.
1999
2000 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
2001
2002         * arm-dis.c (arm_opcodes): Add dfb.
2003         (thumb32_opcodes): Add dfb.
2004
2005 2020-06-08  Jan Beulich  <jbeulich@suse.com>
2006
2007         * i386-opc.h (reg_entry): Const-qualify reg_name field.
2008
2009 2020-06-06  Alan Modra  <amodra@gmail.com>
2010
2011         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
2012
2013 2020-06-05  Alan Modra  <amodra@gmail.com>
2014
2015         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
2016         size is large enough.
2017
2018 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
2019
2020         * disassemble.c (disassemble_init_for_target): Set endian_code for
2021         bpf targets.
2022         * bpf-desc.c: Regenerate.
2023         * bpf-opc.c: Likewise.
2024         * bpf-dis.c: Likewise.
2025
2026 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
2027
2028         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
2029         (cgen_put_insn_value): Likewise.
2030         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
2031         * cgen-dis.in (print_insn): Likewise.
2032         * cgen-ibld.in (insert_1): Likewise.
2033         (insert_1): Likewise.
2034         (insert_insn_normal): Likewise.
2035         (extract_1): Likewise.
2036         * bpf-dis.c: Regenerate.
2037         * bpf-ibld.c: Likewise.
2038         * bpf-ibld.c: Likewise.
2039         * cgen-dis.in: Likewise.
2040         * cgen-ibld.in: Likewise.
2041         * cgen-opc.c: Likewise.
2042         * epiphany-dis.c: Likewise.
2043         * epiphany-ibld.c: Likewise.
2044         * fr30-dis.c: Likewise.
2045         * fr30-ibld.c: Likewise.
2046         * frv-dis.c: Likewise.
2047         * frv-ibld.c: Likewise.
2048         * ip2k-dis.c: Likewise.
2049         * ip2k-ibld.c: Likewise.
2050         * iq2000-dis.c: Likewise.
2051         * iq2000-ibld.c: Likewise.
2052         * lm32-dis.c: Likewise.
2053         * lm32-ibld.c: Likewise.
2054         * m32c-dis.c: Likewise.
2055         * m32c-ibld.c: Likewise.
2056         * m32r-dis.c: Likewise.
2057         * m32r-ibld.c: Likewise.
2058         * mep-dis.c: Likewise.
2059         * mep-ibld.c: Likewise.
2060         * mt-dis.c: Likewise.
2061         * mt-ibld.c: Likewise.
2062         * or1k-dis.c: Likewise.
2063         * or1k-ibld.c: Likewise.
2064         * xc16x-dis.c: Likewise.
2065         * xc16x-ibld.c: Likewise.
2066         * xstormy16-dis.c: Likewise.
2067         * xstormy16-ibld.c: Likewise.
2068
2069 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
2070
2071         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
2072         (print_insn_): Handle instruction endian.
2073         * bpf-dis.c: Regenerate.
2074         * bpf-desc.c: Regenerate.
2075         * epiphany-dis.c: Likewise.
2076         * epiphany-desc.c: Likewise.
2077         * fr30-dis.c: Likewise.
2078         * fr30-desc.c: Likewise.
2079         * frv-dis.c: Likewise.
2080         * frv-desc.c: Likewise.
2081         * ip2k-dis.c: Likewise.
2082         * ip2k-desc.c: Likewise.
2083         * iq2000-dis.c: Likewise.
2084         * iq2000-desc.c: Likewise.
2085         * lm32-dis.c: Likewise.
2086         * lm32-desc.c: Likewise.
2087         * m32c-dis.c: Likewise.
2088         * m32c-desc.c: Likewise.
2089         * m32r-dis.c: Likewise.
2090         * m32r-desc.c: Likewise.
2091         * mep-dis.c: Likewise.
2092         * mep-desc.c: Likewise.
2093         * mt-dis.c: Likewise.
2094         * mt-desc.c: Likewise.
2095         * or1k-dis.c: Likewise.
2096         * or1k-desc.c: Likewise.
2097         * xc16x-dis.c: Likewise.
2098         * xc16x-desc.c: Likewise.
2099         * xstormy16-dis.c: Likewise.
2100         * xstormy16-desc.c: Likewise.
2101
2102 2020-06-03  Nick Clifton  <nickc@redhat.com>
2103
2104         * po/sr.po: Updated Serbian translation.
2105
2106 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
2107
2108         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
2109         (riscv_get_priv_spec_class): Likewise.
2110
2111 2020-06-01  Alan Modra  <amodra@gmail.com>
2112
2113         * bpf-desc.c: Regenerate.
2114
2115 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
2116             David Faust <david.faust@oracle.com>
2117
2118         * bpf-desc.c: Regenerate.
2119         * bpf-opc.h: Likewise.
2120         * bpf-opc.c: Likewise.
2121         * bpf-dis.c: Likewise.
2122
2123 2020-05-28  Alan Modra  <amodra@gmail.com>
2124
2125         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
2126         values.
2127
2128 2020-05-28  Alan Modra  <amodra@gmail.com>
2129
2130         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
2131         immediates.
2132         (print_insn_ns32k): Revert last change.
2133
2134 2020-05-28  Nick Clifton  <nickc@redhat.com>
2135
2136         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
2137         static.
2138
2139 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
2140
2141         Fix extraction of signed constants in nios2 disassembler (again).
2142
2143         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
2144         extractions of signed fields.
2145
2146 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
2147
2148         * s390-opc.txt: Relocate vector load/store instructions with
2149         additional alignment parameter and change architecture level
2150         constraint from z14 to z13.
2151
2152 2020-05-21  Alan Modra  <amodra@gmail.com>
2153
2154         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
2155         * sparc-dis.c: Likewise.
2156         * tic4x-dis.c: Likewise.
2157         * xtensa-dis.c: Likewise.
2158         * bpf-desc.c: Regenerate.
2159         * epiphany-desc.c: Regenerate.
2160         * fr30-desc.c: Regenerate.
2161         * frv-desc.c: Regenerate.
2162         * ip2k-desc.c: Regenerate.
2163         * iq2000-desc.c: Regenerate.
2164         * lm32-desc.c: Regenerate.
2165         * m32c-desc.c: Regenerate.
2166         * m32r-desc.c: Regenerate.
2167         * mep-asm.c: Regenerate.
2168         * mep-desc.c: Regenerate.
2169         * mt-desc.c: Regenerate.
2170         * or1k-desc.c: Regenerate.
2171         * xc16x-desc.c: Regenerate.
2172         * xstormy16-desc.c: Regenerate.
2173
2174 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
2175
2176         * riscv-opc.c (riscv_ext_version_table): The table used to store
2177         all information about the supported spec and the corresponding ISA
2178         versions.  Currently, only Zicsr is supported to verify the
2179         correctness of Z sub extension settings.  Others will be supported
2180         in the future patches.
2181         (struct isa_spec_t, isa_specs): List for all supported ISA spec
2182         classes and the corresponding strings.
2183         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
2184         spec class by giving a ISA spec string.
2185         * riscv-opc.c (struct priv_spec_t): New structure.
2186         (struct priv_spec_t priv_specs): List for all supported privilege spec
2187         classes and the corresponding strings.
2188         (riscv_get_priv_spec_class): New function.  Get the corresponding
2189         privilege spec class by giving a spec string.
2190         (riscv_get_priv_spec_name): New function.  Get the corresponding
2191         privilege spec string by giving a CSR version class.
2192         * riscv-dis.c: Updated since DECLARE_CSR is changed.
2193         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
2194         according to the chosen version.  Build a hash table riscv_csr_hash to
2195         store the valid CSR for the chosen pirv verison.  Dump the direct
2196         CSR address rather than it's name if it is invalid.
2197         (parse_riscv_dis_option_without_args): New function.  Parse the options
2198         without arguments.
2199         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
2200         parse the options without arguments first, and then handle the options
2201         with arguments.  Add the new option -Mpriv-spec, which has argument.
2202         * riscv-dis.c (print_riscv_disassembler_options): Add description
2203         about the new OBJDUMP option.
2204
2205 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
2206
2207         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
2208         WC values on POWER10 sync, dcbf  and wait instructions.
2209         (insert_pl, extract_pl): New functions.
2210         (L2OPT, LS, WC): Use insert_ls and extract_ls.
2211         (LS3): New , 3-bit L for sync.
2212         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
2213         (SC2, PL): New, 2-bit SC and PL for sync and wait.
2214         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
2215         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
2216         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
2217         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
2218         <wait>: Enable PL operand on POWER10.
2219         <dcbf>: Enable L3OPT operand on POWER10.
2220         <sync>: Enable SC2 operand on POWER10.
2221
2222 2020-05-19  Stafford Horne  <shorne@gmail.com>
2223
2224         PR 25184
2225         * or1k-asm.c: Regenerate.
2226         * or1k-desc.c: Regenerate.
2227         * or1k-desc.h: Regenerate.
2228         * or1k-dis.c: Regenerate.
2229         * or1k-ibld.c: Regenerate.
2230         * or1k-opc.c: Regenerate.
2231         * or1k-opc.h: Regenerate.
2232         * or1k-opinst.c: Regenerate.
2233
2234 2020-05-11  Alan Modra  <amodra@gmail.com>
2235
2236         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
2237         xsmaxcqp, xsmincqp.
2238
2239 2020-05-11  Alan Modra  <amodra@gmail.com>
2240
2241         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
2242         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
2243
2244 2020-05-11  Alan Modra  <amodra@gmail.com>
2245
2246         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
2247
2248 2020-05-11  Alan Modra  <amodra@gmail.com>
2249
2250         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
2251         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
2252
2253 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2254
2255         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
2256         mnemonics.
2257
2258 2020-05-11  Alan Modra  <amodra@gmail.com>
2259
2260         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
2261         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
2262         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
2263         (prefix_opcodes): Add xxeval.
2264
2265 2020-05-11  Alan Modra  <amodra@gmail.com>
2266
2267         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
2268         xxgenpcvwm, xxgenpcvdm.
2269
2270 2020-05-11  Alan Modra  <amodra@gmail.com>
2271
2272         * ppc-opc.c (MP, VXVAM_MASK): Define.
2273         (VXVAPS_MASK): Use VXVA_MASK.
2274         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
2275         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
2276         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
2277         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
2278
2279 2020-05-11  Alan Modra  <amodra@gmail.com>
2280             Peter Bergner  <bergner@linux.ibm.com>
2281
2282         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
2283         New functions.
2284         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
2285         YMSK2, XA6a, XA6ap, XB6a entries.
2286         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
2287         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
2288         (PPCVSX4): Define.
2289         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
2290         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
2291         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
2292         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
2293         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
2294         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
2295         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
2296         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
2297         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
2298         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
2299         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
2300         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
2301         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
2302         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
2303
2304 2020-05-11  Alan Modra  <amodra@gmail.com>
2305
2306         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
2307         (insert_xts, extract_xts): New functions.
2308         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
2309         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
2310         (VXRC_MASK, VXSH_MASK): Define.
2311         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
2312         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
2313         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
2314         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
2315         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
2316         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
2317         xxblendvh, xxblendvw, xxblendvd, xxpermx.
2318
2319 2020-05-11  Alan Modra  <amodra@gmail.com>
2320
2321         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
2322         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
2323         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
2324         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
2325         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
2326
2327 2020-05-11  Alan Modra  <amodra@gmail.com>
2328
2329         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
2330         (XTP, DQXP, DQXP_MASK): Define.
2331         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
2332         (prefix_opcodes): Add plxvp and pstxvp.
2333
2334 2020-05-11  Alan Modra  <amodra@gmail.com>
2335
2336         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
2337         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
2338         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
2339
2340 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2341
2342         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
2343
2344 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2345
2346         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
2347         (L1OPT): Define.
2348         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
2349
2350 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2351
2352         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
2353
2354 2020-05-11  Alan Modra  <amodra@gmail.com>
2355
2356         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
2357
2358 2020-05-11  Alan Modra  <amodra@gmail.com>
2359
2360         * ppc-dis.c (ppc_opts): Add "power10" entry.
2361         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
2362         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
2363
2364 2020-05-11  Nick Clifton  <nickc@redhat.com>
2365
2366         * po/fr.po: Updated French translation.
2367
2368 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
2369
2370         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
2371         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
2372         (operand_general_constraint_met_p): validate
2373         AARCH64_OPND_UNDEFINED.
2374         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
2375         for FLD_imm16_2.
2376         * aarch64-asm-2.c: Regenerated.
2377         * aarch64-dis-2.c: Regenerated.
2378         * aarch64-opc-2.c: Regenerated.
2379
2380 2020-04-29  Nick Clifton  <nickc@redhat.com>
2381
2382         PR 22699
2383         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
2384         and SETRC insns.
2385
2386 2020-04-29  Nick Clifton  <nickc@redhat.com>
2387
2388         * po/sv.po: Updated Swedish translation.
2389
2390 2020-04-29  Nick Clifton  <nickc@redhat.com>
2391
2392         PR 22699
2393         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
2394         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
2395         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
2396         IMM0_8U case.
2397
2398 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
2399
2400         PR 25848
2401         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
2402         cmpi only on m68020up and cpu32.
2403
2404 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
2405
2406         * aarch64-asm.c (aarch64_ins_none): New.
2407         * aarch64-asm.h (ins_none): New declaration.
2408         * aarch64-dis.c (aarch64_ext_none): New.
2409         * aarch64-dis.h (ext_none): New declaration.
2410         * aarch64-opc.c (aarch64_print_operand): Update case for
2411         AARCH64_OPND_BARRIER_PSB.
2412         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2413         (AARCH64_OPERANDS): Update inserter/extracter for
2414         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2415         * aarch64-asm-2.c: Regenerated.
2416         * aarch64-dis-2.c: Regenerated.
2417         * aarch64-opc-2.c: Regenerated.
2418
2419 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
2420
2421         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2422         (aarch64_feature_ras, RAS): Likewise.
2423         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2424         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2425         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2426         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2427         * aarch64-asm-2.c: Regenerated.
2428         * aarch64-dis-2.c: Regenerated.
2429         * aarch64-opc-2.c: Regenerated.
2430
2431 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
2432
2433         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2434         (print_insn_neon): Support disassembly of conditional
2435         instructions.
2436
2437 2020-02-16  David Faust  <david.faust@oracle.com>
2438
2439         * bpf-desc.c: Regenerate.
2440         * bpf-desc.h: Likewise.
2441         * bpf-opc.c: Regenerate.
2442         * bpf-opc.h: Likewise.
2443
2444 2020-04-07  Lili Cui  <lili.cui@intel.com>
2445
2446         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2447         (prefix_table): New instructions (see prefixes above).
2448         (rm_table): Likewise
2449         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2450         CPU_ANY_TSXLDTRK_FLAGS.
2451         (cpu_flags): Add CpuTSXLDTRK.
2452         * i386-opc.h (enum): Add CpuTSXLDTRK.
2453         (i386_cpu_flags): Add cputsxldtrk.
2454         * i386-opc.tbl: Add XSUSPLDTRK insns.
2455         * i386-init.h: Regenerate.
2456         * i386-tbl.h: Likewise.
2457
2458 2020-04-02  Lili Cui  <lili.cui@intel.com>
2459
2460         * i386-dis.c (prefix_table): New instructions serialize.
2461         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2462         CPU_ANY_SERIALIZE_FLAGS.
2463         (cpu_flags): Add CpuSERIALIZE.
2464         * i386-opc.h (enum): Add CpuSERIALIZE.
2465         (i386_cpu_flags): Add cpuserialize.
2466         * i386-opc.tbl: Add SERIALIZE insns.
2467         * i386-init.h: Regenerate.
2468         * i386-tbl.h: Likewise.
2469
2470 2020-03-26  Alan Modra  <amodra@gmail.com>
2471
2472         * disassemble.h (opcodes_assert): Declare.
2473         (OPCODES_ASSERT): Define.
2474         * disassemble.c: Don't include assert.h.  Include opintl.h.
2475         (opcodes_assert): New function.
2476         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2477         (bfd_h8_disassemble): Reduce size of data array.  Correctly
2478         calculate maxlen.  Omit insn decoding when insn length exceeds
2479         maxlen.  Exit from nibble loop when looking for E, before
2480         accessing next data byte.  Move processing of E outside loop.
2481         Replace tests of maxlen in loop with assertions.
2482
2483 2020-03-26  Alan Modra  <amodra@gmail.com>
2484
2485         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
2486
2487 2020-03-25  Alan Modra  <amodra@gmail.com>
2488
2489         * z80-dis.c (suffix): Init mybuf.
2490
2491 2020-03-22  Alan Modra  <amodra@gmail.com>
2492
2493         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2494         successflly read from section.
2495
2496 2020-03-22  Alan Modra  <amodra@gmail.com>
2497
2498         * arc-dis.c (find_format): Use ISO C string concatenation rather
2499         than line continuation within a string.  Don't access needs_limm
2500         before testing opcode != NULL.
2501
2502 2020-03-22  Alan Modra  <amodra@gmail.com>
2503
2504         * ns32k-dis.c (print_insn_arg): Update comment.
2505         (print_insn_ns32k): Reduce size of index_offset array, and
2506         initialize, passing -1 to print_insn_arg for args that are not
2507         an index.  Don't exit arg loop early.  Abort on bad arg number.
2508
2509 2020-03-22  Alan Modra  <amodra@gmail.com>
2510
2511         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2512         * s12z-opc.c: Formatting.
2513         (operands_f): Return an int.
2514         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2515         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2516         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2517         (exg_sex_discrim): Likewise.
2518         (create_immediate_operand, create_bitfield_operand),
2519         (create_register_operand_with_size, create_register_all_operand),
2520         (create_register_all16_operand, create_simple_memory_operand),
2521         (create_memory_operand, create_memory_auto_operand): Don't
2522         segfault on malloc failure.
2523         (z_ext24_decode): Return an int status, negative on fail, zero
2524         on success.
2525         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2526         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2527         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2528         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2529         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2530         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2531         (loop_primitive_decode, shift_decode, psh_pul_decode),
2532         (bit_field_decode): Similarly.
2533         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
2534         to return value, update callers.
2535         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2536         Don't segfault on NULL operand.
2537         (decode_operation): Return OP_INVALID on first fail.
2538         (decode_s12z): Check all reads, returning -1 on fail.
2539
2540 2020-03-20  Alan Modra  <amodra@gmail.com>
2541
2542         * metag-dis.c (print_insn_metag): Don't ignore status from
2543         read_memory_func.
2544
2545 2020-03-20  Alan Modra  <amodra@gmail.com>
2546
2547         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2548         Initialize parts of buffer not written when handling a possible
2549         2-byte insn at end of section.  Don't attempt decoding of such
2550         an insn by the 4-byte machinery.
2551
2552 2020-03-20  Alan Modra  <amodra@gmail.com>
2553
2554         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2555         partially filled buffer.  Prevent lookup of 4-byte insns when
2556         only VLE 2-byte insns are possible due to section size.  Print
2557         ".word" rather than ".long" for 2-byte leftovers.
2558
2559 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
2560
2561         PR 25641
2562         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2563
2564 2020-03-13  Jan Beulich  <jbeulich@suse.com>
2565
2566         * i386-dis.c (X86_64_0D): Rename to ...
2567         (X86_64_0E): ... this.
2568
2569 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
2570
2571         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2572         * Makefile.in: Regenerated.
2573
2574 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2575
2576         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2577         3-operand pseudos.
2578         * i386-tbl.h: Re-generate.
2579
2580 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2581
2582         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2583         vprot*, vpsha*, and vpshl*.
2584         * i386-tbl.h: Re-generate.
2585
2586 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2587
2588         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2589         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2590         * i386-tbl.h: Re-generate.
2591
2592 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2593
2594         * i386-gen.c (set_bitfield): Ignore zero-length field names.
2595         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2596         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2597         * i386-tbl.h: Re-generate.
2598
2599 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2600
2601         * i386-gen.c (struct template_arg, struct template_instance,
2602         struct template_param, struct template, templates,
2603         parse_template, expand_templates): New.
2604         (process_i386_opcodes): Various local variables moved to
2605         expand_templates. Call parse_template and expand_templates.
2606         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2607         * i386-tbl.h: Re-generate.
2608
2609 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2610
2611         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2612         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2613         register and memory source templates. Replace VexW= by VexW*
2614         where applicable.
2615         * i386-tbl.h: Re-generate.
2616
2617 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2618
2619         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2620         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2621         * i386-tbl.h: Re-generate.
2622
2623 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2624
2625         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2626         * i386-tbl.h: Re-generate.
2627
2628 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2629
2630         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2631         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2632         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2633         VexW0 on SSE2AVX variants.
2634         (vmovq): Drop NoRex64 from XMM/XMM variants.
2635         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2636         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2637         applicable use VexW0.
2638         * i386-tbl.h: Re-generate.
2639
2640 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2641
2642         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2643         * i386-opc.h (Rex64): Delete.
2644         (struct i386_opcode_modifier): Remove rex64 field.
2645         * i386-opc.tbl (crc32): Drop Rex64.
2646         Replace Rex64 with Size64 everywhere else.
2647         * i386-tbl.h: Re-generate.
2648
2649 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2650
2651         * i386-dis.c (OP_E_memory): Exclude recording of used address
2652         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2653         addressed memory operands for MPX insns.
2654
2655 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2656
2657         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2658         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2659         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2660         (ptwrite): Split into non-64-bit and 64-bit forms.
2661         * i386-tbl.h: Re-generate.
2662
2663 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2664
2665         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2666         template.
2667         * i386-tbl.h: Re-generate.
2668
2669 2020-03-04  Jan Beulich  <jbeulich@suse.com>
2670
2671         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2672         (prefix_table): Move vmmcall here. Add vmgexit.
2673         (rm_table): Replace vmmcall entry by prefix_table[] escape.
2674         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2675         (cpu_flags): Add CpuSEV_ES entry.
2676         * i386-opc.h (CpuSEV_ES): New.
2677         (union i386_cpu_flags): Add cpusev_es field.
2678         * i386-opc.tbl (vmgexit): New.
2679         * i386-init.h, i386-tbl.h: Re-generate.
2680
2681 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
2682
2683         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2684         with MnemonicSize.
2685         * i386-opc.h (IGNORESIZE): New.
2686         (DEFAULTSIZE): Likewise.
2687         (IgnoreSize): Removed.
2688         (DefaultSize): Likewise.
2689         (MnemonicSize): New.
2690         (i386_opcode_modifier): Replace ignoresize/defaultsize with
2691         mnemonicsize.
2692         * i386-opc.tbl (IgnoreSize): New.
2693         (DefaultSize): Likewise.
2694         * i386-tbl.h: Regenerated.
2695
2696 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
2697
2698         PR 25627
2699         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2700         instructions.
2701
2702 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
2703
2704         PR gas/25622
2705         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2706         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2707         * i386-tbl.h: Regenerated.
2708
2709 2020-02-26  Alan Modra  <amodra@gmail.com>
2710
2711         * aarch64-asm.c: Indent labels correctly.
2712         * aarch64-dis.c: Likewise.
2713         * aarch64-gen.c: Likewise.
2714         * aarch64-opc.c: Likewise.
2715         * alpha-dis.c: Likewise.
2716         * i386-dis.c: Likewise.
2717         * nds32-asm.c: Likewise.
2718         * nfp-dis.c: Likewise.
2719         * visium-dis.c: Likewise.
2720
2721 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
2722
2723         * arc-regs.h (int_vector_base): Make it available for all ARC
2724         CPUs.
2725
2726 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
2727
2728         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2729         changed.
2730
2731 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
2732
2733         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2734         c.mv/c.li if rs1 is zero.
2735
2736 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
2737
2738         * i386-gen.c (cpu_flag_init): Replace CpuABM with
2739         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
2740         CPU_POPCNT_FLAGS.
2741         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
2742         * i386-opc.h (CpuABM): Removed.
2743         (CpuPOPCNT): New.
2744         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
2745         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2746         popcnt.  Remove CpuABM from lzcnt.
2747         * i386-init.h: Regenerated.
2748         * i386-tbl.h: Likewise.
2749
2750 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2751
2752         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2753         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2754         VexW1 instead of open-coding them.
2755         * i386-tbl.h: Re-generate.
2756
2757 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2758
2759         * i386-opc.tbl (AddrPrefixOpReg): Define.
2760         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2761         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2762         templates. Drop NoRex64.
2763         * i386-tbl.h: Re-generate.
2764
2765 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2766
2767         PR gas/6518
2768         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2769         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2770         into Intel syntax instance (with Unpsecified) and AT&T one
2771         (without).
2772         (vcvtneps2bf16): Likewise, along with folding the two so far
2773         separate ones.
2774         * i386-tbl.h: Re-generate.
2775
2776 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
2777
2778         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2779         CPU_ANY_SSE4A_FLAGS.
2780
2781 2020-02-17  Alan Modra  <amodra@gmail.com>
2782
2783         * i386-gen.c (cpu_flag_init): Correct last change.
2784
2785 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
2786
2787         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
2788         CPU_ANY_SSE4_FLAGS.
2789
2790 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
2791
2792         * i386-opc.tbl (movsx): Remove Intel syntax comments.
2793         (movzx): Likewise.
2794
2795 2020-02-14  Jan Beulich  <jbeulich@suse.com>
2796
2797         PR gas/25438
2798         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2799         destination for Cpu64-only variant.
2800         (movzx): Fold patterns.
2801         * i386-tbl.h: Re-generate.
2802
2803 2020-02-13  Jan Beulich  <jbeulich@suse.com>
2804
2805         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2806         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2807         CPU_ANY_SSE4_FLAGS entry.
2808         * i386-init.h: Re-generate.
2809
2810 2020-02-12  Jan Beulich  <jbeulich@suse.com>
2811
2812         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2813         with Unspecified, making the present one AT&T syntax only.
2814         * i386-tbl.h: Re-generate.
2815
2816 2020-02-12  Jan Beulich  <jbeulich@suse.com>
2817
2818         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2819         * i386-tbl.h: Re-generate.
2820
2821 2020-02-12  Jan Beulich  <jbeulich@suse.com>
2822
2823         PR gas/24546
2824         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2825         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2826         Amd64 and Intel64 templates.
2827         (call, jmp): Likewise for far indirect variants. Dro
2828         Unspecified.
2829         * i386-tbl.h: Re-generate.
2830
2831 2020-02-11  Jan Beulich  <jbeulich@suse.com>
2832
2833         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2834         * i386-opc.h (ShortForm): Delete.
2835         (struct i386_opcode_modifier): Remove shortform field.
2836         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2837         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2838         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2839         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2840         Drop ShortForm.
2841         * i386-tbl.h: Re-generate.
2842
2843 2020-02-11  Jan Beulich  <jbeulich@suse.com>
2844
2845         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2846         fucompi): Drop ShortForm from operand-less templates.
2847         * i386-tbl.h: Re-generate.
2848
2849 2020-02-11  Alan Modra  <amodra@gmail.com>
2850
2851         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2852         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2853         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2854         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2855         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2856
2857 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
2858
2859         * arm-dis.c (print_insn_cde): Define 'V' parse character.
2860         (cde_opcodes): Add VCX* instructions.
2861
2862 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
2863             Matthew Malcomson  <matthew.malcomson@arm.com>
2864
2865         * arm-dis.c (struct cdeopcode32): New.
2866         (CDE_OPCODE): New macro.
2867         (cde_opcodes): New disassembly table.
2868         (regnames): New option to table.
2869         (cde_coprocs): New global variable.
2870         (print_insn_cde): New
2871         (print_insn_thumb32): Use print_insn_cde.
2872         (parse_arm_disassembler_options): Parse coprocN args.
2873
2874 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
2875
2876         PR gas/25516
2877         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2878         with ISA64.
2879         * i386-opc.h (AMD64): Removed.
2880         (Intel64): Likewose.
2881         (AMD64): New.
2882         (INTEL64): Likewise.
2883         (INTEL64ONLY): Likewise.
2884         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2885         * i386-opc.tbl (Amd64): New.
2886         (Intel64): Likewise.
2887         (Intel64Only): Likewise.
2888         Replace AMD64 with Amd64.  Update sysenter/sysenter with
2889         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
2890         * i386-tbl.h: Regenerated.
2891
2892 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
2893
2894         PR 25469
2895         * z80-dis.c: Add support for GBZ80 opcodes.
2896
2897 2020-02-04  Alan Modra  <amodra@gmail.com>
2898
2899         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2900
2901 2020-02-03  Alan Modra  <amodra@gmail.com>
2902
2903         * m32c-ibld.c: Regenerate.
2904
2905 2020-02-01  Alan Modra  <amodra@gmail.com>
2906
2907         * frv-ibld.c: Regenerate.
2908
2909 2020-01-31  Jan Beulich  <jbeulich@suse.com>
2910
2911         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2912         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2913         (OP_E_memory): Replace xmm_mdq_mode case label by
2914         vex_scalar_w_dq_mode one.
2915         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2916
2917 2020-01-31  Jan Beulich  <jbeulich@suse.com>
2918
2919         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2920         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2921         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2922         (intel_operand_size): Drop vex_w_dq_mode case label.
2923
2924 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
2925
2926         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2927         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2928
2929 2020-01-30  Alan Modra  <amodra@gmail.com>
2930
2931         * m32c-ibld.c: Regenerate.
2932
2933 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
2934
2935         * bpf-opc.c: Regenerate.
2936
2937 2020-01-30  Jan Beulich  <jbeulich@suse.com>
2938
2939         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2940         (dis386): Use them to replace C2/C3 table entries.
2941         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2942         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2943         ones. Use Size64 instead of DefaultSize on Intel64 ones.
2944         * i386-tbl.h: Re-generate.
2945
2946 2020-01-30  Jan Beulich  <jbeulich@suse.com>
2947
2948         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2949         forms.
2950         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2951         DefaultSize.
2952         * i386-tbl.h: Re-generate.
2953
2954 2020-01-30  Alan Modra  <amodra@gmail.com>
2955
2956         * tic4x-dis.c (tic4x_dp): Make unsigned.
2957
2958 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
2959             Jan Beulich  <jbeulich@suse.com>
2960
2961         PR binutils/25445
2962         * i386-dis.c (MOVSXD_Fixup): New function.
2963         (movsxd_mode): New enum.
2964         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2965         (intel_operand_size): Handle movsxd_mode.
2966         (OP_E_register): Likewise.
2967         (OP_G): Likewise.
2968         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2969         register on movsxd.  Add movsxd with 16-bit destination register
2970         for AMD64 and Intel64 ISAs.
2971         * i386-tbl.h: Regenerated.
2972
2973 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
2974
2975         PR 25403
2976         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2977         * aarch64-asm-2.c: Regenerate
2978         * aarch64-dis-2.c: Likewise.
2979         * aarch64-opc-2.c: Likewise.
2980
2981 2020-01-21  Jan Beulich  <jbeulich@suse.com>
2982
2983         * i386-opc.tbl (sysret): Drop DefaultSize.
2984         * i386-tbl.h: Re-generate.
2985
2986 2020-01-21  Jan Beulich  <jbeulich@suse.com>
2987
2988         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2989         Dword.
2990         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2991         * i386-tbl.h: Re-generate.
2992
2993 2020-01-20  Nick Clifton  <nickc@redhat.com>
2994
2995         * po/de.po: Updated German translation.
2996         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2997         * po/uk.po: Updated Ukranian translation.
2998
2999 2020-01-20  Alan Modra  <amodra@gmail.com>
3000
3001         * hppa-dis.c (fput_const): Remove useless cast.
3002
3003 2020-01-20  Alan Modra  <amodra@gmail.com>
3004
3005         * arm-dis.c (print_insn_arm): Wrap 'T' value.
3006
3007 2020-01-18  Nick Clifton  <nickc@redhat.com>
3008
3009         * configure: Regenerate.
3010         * po/opcodes.pot: Regenerate.
3011
3012 2020-01-18  Nick Clifton  <nickc@redhat.com>
3013
3014         Binutils 2.34 branch created.
3015
3016 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
3017
3018         * opintl.h: Fix spelling error (seperate).
3019
3020 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
3021
3022         * i386-opc.tbl: Add {vex} pseudo prefix.
3023         * i386-tbl.h: Regenerated.
3024
3025 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
3026
3027         PR 25376
3028         * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
3029         (neon_opcodes): Likewise.
3030         (select_arm_features): Make sure we enable MVE bits when selecting
3031         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
3032         any architecture.
3033
3034 2020-01-16  Jan Beulich  <jbeulich@suse.com>
3035
3036         * i386-opc.tbl: Drop stale comment from XOP section.
3037
3038 2020-01-16  Jan Beulich  <jbeulich@suse.com>
3039
3040         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
3041         (extractps): Add VexWIG to SSE2AVX forms.
3042         * i386-tbl.h: Re-generate.
3043
3044 2020-01-16  Jan Beulich  <jbeulich@suse.com>
3045
3046         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
3047         Size64 from and use VexW1 on SSE2AVX forms.
3048         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
3049         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
3050         * i386-tbl.h: Re-generate.
3051
3052 2020-01-15  Alan Modra  <amodra@gmail.com>
3053
3054         * tic4x-dis.c (tic4x_version): Make unsigned long.
3055         (optab, optab_special, registernames): New file scope vars.
3056         (tic4x_print_register): Set up registernames rather than
3057         malloc'd registertable.
3058         (tic4x_disassemble): Delete optable and optable_special.  Use
3059         optab and optab_special instead.  Throw away old optab,
3060         optab_special and registernames when info->mach changes.
3061
3062 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
3063
3064         PR 25377
3065         * z80-dis.c (suffix): Use .db instruction to generate double
3066         prefix.
3067
3068 2020-01-14  Alan Modra  <amodra@gmail.com>
3069
3070         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
3071         values to unsigned before shifting.
3072
3073 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
3074
3075         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
3076         flow instructions.
3077         (print_insn_thumb16, print_insn_thumb32): Likewise.
3078         (print_insn): Initialize the insn info.
3079         * i386-dis.c (print_insn): Initialize the insn info fields, and
3080         detect jumps.
3081
3082 2020-01-13  Claudiu Zissulescu <claziss@gmail.com>
3083
3084         * arc-opc.c (C_NE): Make it required.
3085
3086 2020-01-13  Claudiu Zissulescu <claziss@gmail.com>
3087
3088         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
3089         reserved register name.
3090
3091 2020-01-13  Alan Modra  <amodra@gmail.com>
3092
3093         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
3094         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
3095
3096 2020-01-13  Alan Modra  <amodra@gmail.com>
3097
3098         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
3099         result of wasm_read_leb128 in a uint64_t and check that bits
3100         are not lost when copying to other locals.  Use uint32_t for
3101         most locals.  Use PRId64 when printing int64_t.
3102
3103 2020-01-13  Alan Modra  <amodra@gmail.com>
3104
3105         * score-dis.c: Formatting.
3106         * score7-dis.c: Formatting.
3107
3108 2020-01-13  Alan Modra  <amodra@gmail.com>
3109
3110         * score-dis.c (print_insn_score48): Use unsigned variables for
3111         unsigned values.  Don't left shift negative values.
3112         (print_insn_score32): Likewise.
3113         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
3114
3115 2020-01-13  Alan Modra  <amodra@gmail.com>
3116
3117         * tic4x-dis.c (tic4x_print_register): Remove dead code.
3118
3119 2020-01-13  Alan Modra  <amodra@gmail.com>
3120
3121         * fr30-ibld.c: Regenerate.
3122
3123 2020-01-13  Alan Modra  <amodra@gmail.com>
3124
3125         * xgate-dis.c (print_insn): Don't left shift signed value.
3126         (ripBits): Formatting, use 1u.
3127
3128 2020-01-10  Alan Modra  <amodra@gmail.com>
3129
3130         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
3131         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
3132
3133 2020-01-10  Alan Modra  <amodra@gmail.com>
3134
3135         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
3136         and XRREG value earlier to avoid a shift with negative exponent.
3137         * m10200-dis.c (disassemble): Similarly.
3138
3139 2020-01-09  Nick Clifton  <nickc@redhat.com>
3140
3141         PR 25224
3142         * z80-dis.c (ld_ii_ii): Use correct cast.
3143
3144 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
3145
3146         PR 25224
3147         * z80-dis.c (ld_ii_ii): Use character constant when checking
3148         opcode byte value.
3149
3150 2020-01-09  Jan Beulich  <jbeulich@suse.com>
3151
3152         * i386-dis.c (SEP_Fixup): New.
3153         (SEP): Define.
3154         (dis386_twobyte): Use it for sysenter/sysexit.
3155         (enum x86_64_isa): Change amd64 enumerator to value 1.
3156         (OP_J): Compare isa64 against intel64 instead of amd64.
3157         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
3158         forms.
3159         * i386-tbl.h: Re-generate.
3160
3161 2020-01-08  Alan Modra  <amodra@gmail.com>
3162
3163         * z8k-dis.c: Include libiberty.h
3164         (instr_data_s): Make max_fetched unsigned.
3165         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
3166         Don't exceed byte_info bounds.
3167         (output_instr): Make num_bytes unsigned.
3168         (unpack_instr): Likewise for nibl_count and loop.
3169         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
3170         idx unsigned.
3171         * z8k-opc.h: Regenerate.
3172
3173 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
3174
3175         * arc-tbl.h (llock): Use 'LLOCK' as class.
3176         (llockd): Likewise.
3177         (scond): Use 'SCOND' as class.
3178         (scondd): Likewise.
3179         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
3180         (scondd): Likewise.
3181
3182 2020-01-06  Alan Modra  <amodra@gmail.com>
3183
3184         * m32c-ibld.c: Regenerate.
3185
3186 2020-01-06  Alan Modra  <amodra@gmail.com>
3187
3188         PR 25344
3189         * z80-dis.c (suffix): Don't use a local struct buffer copy.
3190         Peek at next byte to prevent recursion on repeated prefix bytes.
3191         Ensure uninitialised "mybuf" is not accessed.
3192         (print_insn_z80): Don't zero n_fetch and n_used here,..
3193         (print_insn_z80_buf): ..do it here instead.
3194
3195 2020-01-04  Alan Modra  <amodra@gmail.com>
3196
3197         * m32r-ibld.c: Regenerate.
3198
3199 2020-01-04  Alan Modra  <amodra@gmail.com>
3200
3201         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
3202
3203 2020-01-04  Alan Modra  <amodra@gmail.com>
3204
3205         * crx-dis.c (match_opcode): Avoid shift left of signed value.
3206
3207 2020-01-04  Alan Modra  <amodra@gmail.com>
3208
3209         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
3210
3211 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3212
3213         * aarch64-tbl.h (aarch64_opcode_table): Use
3214         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
3215
3216 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3217
3218         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
3219         forms of SUDOT and USDOT.
3220
3221 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3222
3223         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
3224         uzip{1,2}.
3225         * aarch64-dis-2.c: Re-generate.
3226
3227 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3228
3229         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
3230         FMMLA encoding.
3231         * aarch64-dis-2.c: Re-generate.
3232
3233 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
3234
3235         * z80-dis.c: Add support for eZ80 and Z80 instructions.
3236
3237 2020-01-01  Alan Modra  <amodra@gmail.com>
3238
3239         Update year range in copyright notice of all files.
3240
3241 For older changes see ChangeLog-2019
3242 \f
3243 Copyright (C) 2020 Free Software Foundation, Inc.
3244
3245 Copying and distribution of this file, with or without modification,
3246 are permitted in any medium without royalty provided the copyright
3247 notice and this notice are preserved.
3248
3249 Local Variables:
3250 mode: change-log
3251 left-margin: 8
3252 fill-column: 74
3253 version-control: never
3254 End: