1 2020-11-09 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
3 * aarch64-opc.c (aarch64_print_operand): Support operand AARCH64_OPND_Rt_LS64
5 * aarch64-tbl.h (struct aarch64_opcode): Update _LS64_INSN instructions with
7 * aarch64-asm-2.c: Regenerated.
8 * aarch64-dis-2.c: Regenerated.
9 * aarch64-opc-2.c: Regenerated.
11 2020-11-06 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
13 * aarch64-tbl.h (PAC): Handle for PAC feature.
14 (PAC_INSN): New PAC instruction.
15 (struct aarch64_opcode): Move PAC instructions from V8_3_INSN to
18 2020-11-04 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
20 * aarch64-opc.c: Add RAS 1.1 new system registers: ERXPFGCTL_EL1,
21 ERXPFGCDN_EL1, ERXMISC2_EL1, ERXMISC3_EL1 and ERXPFGF_EL1.
23 2020-11-03 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
25 * aarch64-tbl.h (QL_X2NIL): New qualifier for 64-byte stores.
26 (LS64): Handler with +ls64 feature flags.
27 (_LS64_INSN): New instruction group macro.
28 (struct aarch64_opcode): Add LS64 instructions.
29 * aarch64-asm-2.c: Regenerated.
30 * aarch64-dis-2.c: Regenerated.
31 * aarch64-opc-2.c: Regenerated.
33 2020-10-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
35 * aarch65-tbl.h (struct aarch64_opcode): New instruction WFIT.
36 * aarch64-asm-2.c: Regenerated.
37 * aarch64-dis-2.c: Regenerated.
38 * aarch64-opc-2.c: Regenerated.
40 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
42 * aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out.
43 * aarch64-tbl.h (CSRE): New CSRE feature handler.
44 (_CSRE_INSN): New CSRE instruction type.
45 (struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature.
46 * aarch64-asm-2.c: Regenerated.
47 * aarch64-dis-2.c: Regenerated.
48 * aarch64-opc-2.c: Regenerated.
50 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
52 * aarch64-tbl.h (struct aarch64_opcode): Add new WFET instruction encoding
53 and operand description.
54 * aarch64-asm-2.c: Regenerated.
55 * aarch64-dis-2.c: Regenerated.
56 * aarch64-opc-2.c: Regenerated.
58 2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com>
60 * csky-opc.h (csky_v2_opcodes): Change plsl.u16 to plsl.16.
62 2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com>
64 * csky-dis.c (csky_output_operand): Add handler for
65 OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
66 * csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum.
67 (OPRND_TYPE_IMM5b_VSH): New enum. (csky_v2_opcodes): Fix and add
68 some instructions for VDSPV1.
70 2020-10-26 Lili Cui <lili.cui@intel.com>
72 * i386-dis.c: Change "XV" to print "{vex}" pseudo prefix.
74 2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
76 * aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter.
77 * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter
79 * aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor.
80 * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor
82 * aarch64-opc.c (aarch64_print_operand): New options table
83 aarch64_barrier_dsb_nxs_options.
84 * aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs.
85 * aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier
86 Armv8.7-a instruction.
87 * aarch64-asm-2.c: Regenerated.
88 * aarch64-dis-2.c: Regenerated.
89 * aarch64-opc-2.c: Regenerated.
91 2020-10-22 H.J. Lu <hongjiu.lu@intel.com>
93 * po/es.po: Remove the duplicated entry.
95 2020-10-20 Dr. David Alan Gilbert <dgilbert@redhat.com>
97 * po/es.po: Fix printf format.
99 2020-10-20 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
101 * i386-dis.c (rm_table): Add tlbsync, snp, invlpgb.
102 * i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS,
103 CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS.
104 Add CPU_ZNVER3_FLAGS.
105 (cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
106 * i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
107 * i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate,
108 rmpupdate, rmpadjust.
109 * i386-init.h: Re-generated.
110 * i386-tbl.h: Re-generated.
112 2020-10-16 Lili Cui <lili.cui@intel.com>
114 * i386-opc.tbl: Rename CpuVEX_PREFIX to PseudoVexPrefix
115 and move it from cpu_flags to opcode_modifiers.
116 Use VexW0 and VexVVVV in the AVX-VNNI instructions.
117 * i386-gen.c: Likewise.
118 * i386-opc.h: Likewise.
119 * i386-opc.h: Likewise.
120 * i386-init.h: Regenerated.
121 * i386-tbl.h: Likewise.
123 2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
125 * aarch64-tbl.h (ARMV8_7): New macro.
127 2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
128 Lili Cui <lili.cui@intel.com>
130 * i386-dis.c (PREFIX_VEX_0F3850): New.
131 (PREFIX_VEX_0F3851): Likewise.
132 (PREFIX_VEX_0F3852): Likewise.
133 (PREFIX_VEX_0F3853): Likewise.
134 (VEX_W_0F3850_P_2): Likewise.
135 (VEX_W_0F3851_P_2): Likewise.
136 (VEX_W_0F3852_P_2): Likewise.
137 (VEX_W_0F3853_P_2): Likewise.
138 (prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851,
139 PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853.
140 (vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2,
141 VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2.
142 (putop): Add support for "XV" to print "{vex3}" pseudo prefix.
143 * i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in
144 CPU_UNKNOWN_FLAGS. Add CPU_AVX_VNNI_FLAGS and
145 CPU_ANY_AVX_VNNI_FLAGS.
146 (cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX.
147 * i386-opc.h (CpuAVX_VNNI): New.
148 (CpuVEX_PREFIX): Likewise.
149 (i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix.
150 * i386-opc.tbl: Add Intel AVX VNNI instructions.
151 * i386-init.h: Regenerated.
152 * i386-tbl.h: Likewise.
154 2020-10-14 Lili Cui <lili.cui@intel.com>
155 H.J. Lu <hongjiu.lu@intel.com>
157 * i386-dis.c (PREFIX_0F3A0F): New.
158 (MOD_0F3A0F_PREFIX_1): Likewise.
159 (REG_0F3A0F_PREFIX_1_MOD_3): Likewise.
160 (RM_0F3A0F_P_1_MOD_3_REG_0): Likewise.
161 (prefix_table): Add PREFIX_0F3A0F.
162 (mod_table): Add MOD_0F3A0F_PREFIX_1.
163 (reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3.
164 (rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0.
165 * i386-gen.c (cpu_flag_init): Add HRESET_FLAGS,
166 CPU_ANY_HRESET_FLAGS.
167 (cpu_flags): Add CpuHRESET.
168 (output_i386_opcode): Allow 4 byte base_opcode.
169 * i386-opc.h (enum): Add CpuHRESET.
170 (i386_cpu_flags): Add cpuhreset.
171 * i386-opc.tbl: Add Intel HRESET instruction.
172 * i386-init.h: Regenerate.
173 * i386-tbl.h: Likewise.
175 2020-10-14 Lili Cui <lili.cui@intel.com>
177 * i386-dis.c (enum): Add
178 PREFIX_MOD_3_0F01_REG_5_RM_4,
179 PREFIX_MOD_3_0F01_REG_5_RM_5,
180 PREFIX_MOD_3_0F01_REG_5_RM_6,
181 PREFIX_MOD_3_0F01_REG_5_RM_7,
182 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
183 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
184 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
185 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
186 X86_64_0FC7_REG_6_MOD_3_PREFIX_1.
187 (prefix_table): New instructions (see prefixes above).
189 * i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS,
191 (cpu_flags): Add CpuUINTR.
192 * i386-opc.h (enum): Add CpuUINTR.
193 (i386_cpu_flags): Add cpuuintr.
194 * i386-opc.tbl: Add UINTR insns.
195 * i386-init.h: Regenerate.
196 * i386-tbl.h: Likewise.
198 2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
200 * i386-gen.c (process_i386_opcode_modifier): Return 1 for
201 non-VEX/EVEX/prefix encoding.
202 (output_i386_opcode): Fail if non-VEX/EVEX/prefix base_opcode
204 * i386-opc.tbl: Replace the prefix byte in non-VEX/EVEX
205 base_opcode with PREFIX_0X66, PREFIX_0XF2 or PREFIX_0XF3.
206 * i386-tbl.h: Regenerated.
208 2020-10-13 H.J. Lu <hongjiu.lu@intel.com>
210 * i386-gen.c (opcode_modifiers): Replace VexOpcode with
212 * i386-opc.h (VexOpcode): Renamed to ...
213 (OpcodePrefix): This.
215 (PREFIX_0X66): Likewise.
216 (PREFIX_0XF2): Likewise.
217 (PREFIX_0XF3): Likewise.
218 * i386-opc.tbl (Prefix_0X66): New.
219 (Prefix_0XF2): Likewise.
220 (Prefix_0XF3): Likewise.
221 Replace VexOpcode= with OpcodePrefix=. Use Prefix_0X66 on xorpd.
222 Use Prefix_0XF3 on cvtdq2pd. Use Prefix_0XF2 on cvtpd2dq.
223 * i386-tbl.h: Regenerated.
225 2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
227 * aarch64-opc.c: Add BRBE system registers.
229 2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
231 * aarch64-opc.c: New CSRE system registers defined.
233 2020-10-05 Samanta Navarro <ferivoz@riseup.net>
235 * cgen-asm.c: Fix spelling mistakes.
236 * cgen-dis.c: Fix spelling mistakes.
237 * tic30-dis.c: Fix spelling mistakes.
239 2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
242 * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
244 2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
247 * i386-dis.c (print_insn): Clear modrm if not needed.
248 (putop): Check need_modrm for modrm.mod != 3. Don't check
249 need_modrm for modrm.mod == 3.
251 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
253 * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
254 TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
255 TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
256 TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
257 TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
258 TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
259 TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
260 TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
261 WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
262 TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
263 TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
264 TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVDARCCTLR,
265 TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
266 TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
268 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
270 * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
272 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
274 * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
275 TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
277 2020-09-26 Alan Modra <amodra@gmail.com>
279 * csky-opc.h: Formatting.
280 (GENERAL_REG_BANK): Correct spelling. Update use throughout file.
281 (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
283 (get_register_number): Likewise.
284 * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
286 2020-09-24 Lili Cui <lili.cui@intel.com>
289 * i386-dis.c (enum): Put MOD_VEX_0F38* together.
291 2020-09-24 Andrew Burgess <andrew.burgess@embecosm.com>
293 * csky-dis.c (csky_output_operand): Enclose body of if in curly
296 2020-09-24 Lili Cui <lili.cui@intel.com>
298 * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
299 PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
300 X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
301 X86_64_0F01_REG_1_RM_7_P_2.
302 (prefix_table): Likewise.
303 (x86_64_table): Likewise.
304 (rm_table): Likewise.
305 * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
306 and CPU_ANY_TDX_FLAGS.
307 (cpu_flags): Add CpuTDX.
308 * i386-opc.h (enum): Add CpuTDX.
309 (i386_cpu_flags): Add cputdx.
310 * i386-opc.tbl: Add TDX insns.
311 * i386-init.h: Regenerate.
312 * i386-tbl.h: Likewise.
314 2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
316 * csky-dis.c (using_abi): New.
317 (parse_csky_dis_options): New function.
318 (get_gr_name): New function.
319 (get_cr_name): New function.
320 (csky_output_operand): Use get_gr_name and get_cr_name to
321 disassemble and add handle of OPRND_TYPE_IMM5b_LS.
322 (print_insn_csky): Parse disassembler options.
323 * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
324 (GENARAL_REG_BANK): Define.
325 (REG_SUPPORT_ALL): Define.
326 (REG_SUPPORT_ALL): New.
328 (REG_SUPPORT_A): Define.
329 (REG_SUPPORT_B): Define.
330 (REG_SUPPORT_C): Define.
331 (REG_SUPPORT_D): Define.
332 (REG_SUPPORT_E): Define.
333 (csky_abiv1_general_regs): New.
334 (csky_abiv1_control_regs): New.
335 (csky_abiv2_general_regs): New.
336 (csky_abiv2_control_regs): New.
337 (get_register_name): New function.
338 (get_register_number): New function.
339 (csky_get_general_reg_name): New function.
340 (csky_get_general_regno): New function.
341 (csky_get_control_reg_name): New function.
342 (csky_get_control_regno): New function.
343 (csky_v2_opcodes): Prefer two oprerans format for bclri and
344 bseti, strengthen the operands legality check of addc, zext
347 2020-09-23 Lili Cui <lili.cui@intel.com>
349 * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
350 MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
351 MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
352 MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
353 PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
354 (reg_table): New instructions (see prefixes above).
355 (prefix_table): Likewise.
356 (three_byte_table): Likewise.
357 (mod_table): Likewise
358 * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
359 CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
360 (cpu_flags): Likewise.
361 (operand_type_init): Likewise.
362 * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
363 (i386_cpu_flags): Add cpukl and cpuwide_kl.
364 * i386-opc.tbl: Add KL and WIDE_KL insns.
365 * i386-init.h: Regenerate.
366 * i386-tbl.h: Likewise.
368 2020-09-21 Alan Modra <amodra@gmail.com>
370 * rx-dis.c (flag_names): Add missing comma.
371 (register_names, flag_names, double_register_names),
372 (double_register_high_names, double_register_low_names),
373 (double_control_register_names, double_condition_names): Remove
376 2020-09-18 David Faust <david.faust@oracle.com>
378 * bpf-desc.c: Regenerate.
379 * bpf-desc.h: Likewise.
380 * bpf-opc.c: Likewise.
381 * bpf-opc.h: Likewise.
383 2020-09-16 Andrew Burgess <andrew.burgess@embecosm.com>
385 * csky-dis.c (csky_get_disassembler): Don't return NULL when there
388 2020-09-16 Alan Modra <amodra@gmail.com>
390 * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
392 2020-09-10 Nick Clifton <nickc@redhat.com>
394 * ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
395 for hidden, local, no-type symbols.
396 (disassemble_init_powerpc): Point the symbol_is_valid field in the
397 info structure at the new function.
399 2020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
401 * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
402 * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
405 2020-09-10 Nick Clifton <nickc@redhat.com>
407 * csky-dis.c (csky_output_operand): Coerce the immediate values to
408 long before printing.
410 2020-09-10 Alan Modra <amodra@gmail.com>
412 * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
414 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
416 * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
419 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
421 * csky-dis.c (csky_output_operand): Add handlers for
422 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
423 OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
424 to support FPUV3 instructions.
425 * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
426 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
427 OPRND_TYPE_DFLOAT_FMOVI.
428 (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
429 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
430 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
431 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
432 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
433 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
434 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
435 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
436 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
437 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
438 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
439 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
440 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
441 (csky_v2_opcodes): Add FPUV3 instructions.
443 2020-09-08 Alex Coplan <alex.coplan@arm.com>
445 * aarch64-dis.c (print_operands): Pass CPU features to
446 aarch64_print_operand().
447 * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
448 preferred disassembly of system registers.
449 (SR_RNG): Refactor to use new SR_FEAT2 macro.
455 (SR_EXPAND_ELx): New.
456 (SR_EXPAND_EL12): New.
457 (aarch64_sys_regs): Specify which registers are only on
458 A-profile, add R-profile system registers.
462 (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
465 2020-09-08 Alex Coplan <alex.coplan@arm.com>
467 * aarch64-tbl.h (aarch64_feature_v8_r): New.
470 (aarch64_opcode_table): Add dfb.
471 * aarch64-opc-2.c: Regenerate.
472 * aarch64-asm-2.c: Regenerate.
473 * aarch64-dis-2.c: Regenerate.
475 2020-09-08 Alex Coplan <alex.coplan@arm.com>
477 * aarch64-dis.c (arch_variant): New.
478 (determine_disassembling_preference): Disassemble according to
480 (select_aarch64_variant): New.
481 (print_insn_aarch64): Set feature set.
483 2020-09-02 Alan Modra <amodra@gmail.com>
485 * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
486 (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
487 (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
488 (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
489 (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
490 (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
491 (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
492 for value parameter and update code to suit.
493 (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
494 (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
496 2020-09-02 Alan Modra <amodra@gmail.com>
498 * i386-dis.c (OP_E_memory): Don't cast to signed type when
500 (get32, get32s): Use unsigned types in shift expressions.
502 2020-09-02 Alan Modra <amodra@gmail.com>
504 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
506 2020-09-02 Alan Modra <amodra@gmail.com>
508 * crx-dis.c: Whitespace.
509 (print_arg): Use unsigned type for longdisp and mask variables,
510 and for left shift constant.
512 2020-09-02 Alan Modra <amodra@gmail.com>
514 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
515 * bpf-ibld.c: Regenerate.
516 * epiphany-ibld.c: Regenerate.
517 * fr30-ibld.c: Regenerate.
518 * frv-ibld.c: Regenerate.
519 * ip2k-ibld.c: Regenerate.
520 * iq2000-ibld.c: Regenerate.
521 * lm32-ibld.c: Regenerate.
522 * m32c-ibld.c: Regenerate.
523 * m32r-ibld.c: Regenerate.
524 * mep-ibld.c: Regenerate.
525 * mt-ibld.c: Regenerate.
526 * or1k-ibld.c: Regenerate.
527 * xc16x-ibld.c: Regenerate.
528 * xstormy16-ibld.c: Regenerate.
530 2020-09-02 Alan Modra <amodra@gmail.com>
532 * bfin-dis.c (MASKBITS): Use SIGNBIT.
534 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
536 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
537 to CSKYV2_ISA_3E3R3 instruction set.
539 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
541 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
543 2020-09-01 Alan Modra <amodra@gmail.com>
545 * mep-ibld.c: Regenerate.
547 2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
549 * csky-dis.c (csky_output_operand): Assign dis_info.value for
552 2020-08-30 Alan Modra <amodra@gmail.com>
554 * cr16-dis.c: Formatting.
555 (parameter): Delete struct typedef. Use dwordU instead
557 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
559 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
561 2020-08-29 Alan Modra <amodra@gmail.com>
564 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
565 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
567 2020-08-28 Alan Modra <amodra@gmail.com>
571 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
572 (extract_normal): Likewise.
573 (insert_normal): Likewise, and move past zero length test.
574 (put_insn_int_value): Handle mask for zero length, use 1UL.
575 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
576 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
577 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
578 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
580 2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
582 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
583 (csky_dis_info): Add member isa.
584 (csky_find_inst_info): Skip instructions that do not belong to
586 (csky_get_disassembler): Get infomation from attribute section.
587 (print_insn_csky): Set defualt ISA flag.
588 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
589 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
590 isa_flag32'type to unsigned 64 bits.
592 2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
594 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
596 2020-08-26 David Faust <david.faust@oracle.com>
598 * bpf-desc.c: Regenerate.
599 * bpf-desc.h: Likewise.
600 * bpf-opc.c: Likewise.
601 * bpf-opc.h: Likewise.
602 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
603 ISA when appropriate.
605 2020-08-25 Alan Modra <amodra@gmail.com>
608 * vax-dis.c (parse_disassembler_options): Always add at least one
609 to entry_addr_total_slots.
611 2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
613 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
614 in other CPUs to speed up disassembling.
615 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
616 Change plsli.u16 to plsli.16, change sync's operand format.
618 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
620 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
622 2020-08-21 Nick Clifton <nickc@redhat.com>
624 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
627 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
629 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
631 2020-08-19 Alan Modra <amodra@gmail.com>
633 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
636 2020-08-18 Peter Bergner <bergner@linux.ibm.com>
638 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
639 <xvcvbf16spn>: ...to this.
641 2020-08-12 Alex Coplan <alex.coplan@arm.com>
643 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
645 2020-08-12 Nick Clifton <nickc@redhat.com>
647 * po/sr.po: Updated Serbian translation.
649 2020-08-11 Alan Modra <amodra@gmail.com>
651 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
653 2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
655 * aarch64-opc.c (aarch64_print_operand):
656 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
657 (aarch64_sys_reg_supported_p): Function removed.
658 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
659 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
662 2020-08-10 Alan Modra <amodra@gmail.com>
664 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
667 2020-08-10 Alan Modra <amodra@gmail.com>
669 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
670 Enable icbt for power5, miso for power8.
672 2020-08-10 Alan Modra <amodra@gmail.com>
674 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
675 mtvsrd, and similarly for mfvsrd.
677 2020-08-04 Christian Groessler <chris@groessler.org>
678 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
680 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
681 opcodes (special "out" to absolute address).
682 * z8k-opc.h: Regenerate.
684 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
687 * i386-opc.h (Prefix_Disp8): New.
688 (Prefix_Disp16): Likewise.
689 (Prefix_Disp32): Likewise.
690 (Prefix_Load): Likewise.
691 (Prefix_Store): Likewise.
692 (Prefix_VEX): Likewise.
693 (Prefix_VEX3): Likewise.
694 (Prefix_EVEX): Likewise.
695 (Prefix_REX): Likewise.
696 (Prefix_NoOptimize): Likewise.
697 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
698 * i386-tbl.h: Regenerated.
700 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
702 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
703 default case with abort() instead of printing an error message and
704 continuing, to avoid a maybe-uninitialized warning.
706 2020-07-24 Nick Clifton <nickc@redhat.com>
708 * po/de.po: Updated German translation.
710 2020-07-21 Jan Beulich <jbeulich@suse.com>
712 * i386-dis.c (OP_E_memory): Revert previous change.
714 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
717 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
718 without base nor index registers.
720 2020-07-15 Jan Beulich <jbeulich@suse.com>
722 * i386-dis.c (putop): Move 'V' and 'W' handling.
724 2020-07-15 Jan Beulich <jbeulich@suse.com>
726 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
727 construct for push/pop of register.
728 (putop): Honor cond when handling 'P'. Drop handling of plain
731 2020-07-15 Jan Beulich <jbeulich@suse.com>
733 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
734 description. Drop '&' description. Use P for push of immediate,
735 pushf/popf, enter, and leave. Use %LP for lret/retf.
736 (dis386_twobyte): Use P for push/pop of fs/gs.
737 (reg_table): Use P for push/pop. Use @ for near call/jmp.
738 (x86_64_table): Use P for far call/jmp.
739 (putop): Drop handling of 'U' and '&'. Move and adjust handling
740 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
742 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
743 and dqw_mode (unconditional).
745 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
748 * i386-dis.c (OP_E_memory): Without base nor index registers,
749 32-bit displacement to 64 bits.
751 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
753 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
754 faulty double register pair is detected.
756 2020-07-14 Jan Beulich <jbeulich@suse.com>
758 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
760 2020-07-14 Jan Beulich <jbeulich@suse.com>
762 * i386-dis.c (OP_R, Rm): Delete.
763 (MOD_0F24, MOD_0F26): Rename to ...
764 (X86_64_0F24, X86_64_0F26): ... respectively.
765 (dis386): Update 'L' and 'Z' comments.
766 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
768 (mod_table): Move opcode 0F24 and 0F26 entries ...
769 (x86_64_table): ... here.
770 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
773 2020-07-14 Jan Beulich <jbeulich@suse.com>
775 * i386-dis.c (Rd, Rdq, MaskR): Delete.
776 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
777 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
778 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
779 MOD_EVEX_0F387C): New enumerators.
780 (reg_table): Use Edq for rdssp.
781 (prefix_table): Use Edq for incssp.
782 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
783 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
784 ktest*, and kshift*. Use Edq / MaskE for kmov*.
785 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
786 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
787 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
788 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
789 0F3828_P_1 and 0F3838_P_1.
790 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
791 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
793 2020-07-14 Jan Beulich <jbeulich@suse.com>
795 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
796 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
797 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
798 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
799 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
800 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
801 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
802 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
803 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
804 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
805 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
806 (reg_table, prefix_table, three_byte_table, vex_table,
807 vex_len_table, mod_table, rm_table): Replace / remove respective
809 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
810 of PREFIX_DATA in used_prefixes.
812 2020-07-14 Jan Beulich <jbeulich@suse.com>
814 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
815 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
816 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
817 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
818 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
819 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
820 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
821 VEX_W_0F3A33_L_0): Delete.
822 (dis386): Adjust "BW" description.
823 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
824 0F3A31, 0F3A32, and 0F3A33.
825 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
827 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
830 2020-07-14 Jan Beulich <jbeulich@suse.com>
832 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
833 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
834 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
835 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
836 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
837 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
838 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
839 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
840 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
841 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
842 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
843 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
844 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
845 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
846 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
847 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
848 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
849 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
850 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
851 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
852 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
853 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
854 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
855 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
856 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
857 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
858 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
859 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
860 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
861 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
862 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
863 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
864 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
865 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
866 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
867 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
868 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
869 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
870 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
871 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
872 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
873 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
874 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
875 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
876 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
877 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
878 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
879 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
880 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
881 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
882 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
883 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
884 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
885 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
886 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
887 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
888 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
889 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
890 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
891 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
892 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
893 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
894 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
895 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
896 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
897 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
898 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
899 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
900 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
901 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
902 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
903 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
904 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
905 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
906 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
907 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
908 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
909 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
910 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
911 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
912 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
913 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
914 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
915 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
916 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
917 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
918 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
919 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
920 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
921 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
922 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
923 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
924 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
925 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
926 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
927 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
928 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
929 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
930 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
931 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
932 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
933 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
934 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
935 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
936 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
937 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
938 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
939 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
940 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
941 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
942 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
943 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
944 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
945 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
946 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
947 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
948 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
949 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
950 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
951 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
952 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
953 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
954 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
955 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
956 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
957 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
958 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
959 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
960 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
961 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
962 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
963 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
964 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
965 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
966 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
967 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
968 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
969 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
970 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
971 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
972 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
973 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
974 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
975 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
976 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
977 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
978 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
979 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
980 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
981 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
982 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
983 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
984 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
985 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
986 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
987 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
988 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
989 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
990 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
991 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
992 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
993 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
994 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
995 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
996 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
997 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
998 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
999 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
1000 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1001 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1002 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
1003 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
1004 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
1005 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
1006 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
1007 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
1008 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
1009 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
1010 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
1011 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
1012 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
1013 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
1014 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
1015 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
1016 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
1017 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
1018 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
1019 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
1020 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
1021 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
1022 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1023 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
1024 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1025 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1026 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
1027 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
1028 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
1029 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
1030 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
1031 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1032 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
1033 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1034 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1035 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1036 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
1037 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
1038 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
1039 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
1040 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
1041 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
1042 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
1043 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
1044 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
1045 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
1046 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
1047 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
1048 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
1049 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
1050 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
1051 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
1052 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
1053 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
1054 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
1055 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
1056 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
1057 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
1058 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
1059 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
1060 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
1061 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
1062 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
1063 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
1064 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
1065 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
1066 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
1067 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
1068 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
1069 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
1070 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
1071 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
1072 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
1073 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
1074 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
1075 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
1076 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
1077 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
1078 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
1079 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
1080 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
1081 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
1082 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
1083 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1084 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
1085 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
1086 EVEX_W_0F3A72_P_2): Rename to ...
1087 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
1088 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
1089 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
1090 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
1091 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
1092 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
1093 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
1094 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
1095 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
1096 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
1097 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
1098 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
1099 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
1100 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
1101 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
1102 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
1103 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
1104 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
1105 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
1106 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
1107 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
1108 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
1109 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
1110 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
1111 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
1112 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
1113 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
1114 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
1115 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
1116 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
1117 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
1118 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
1119 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
1120 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
1121 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
1122 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
1123 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
1124 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
1125 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
1126 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
1127 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
1128 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
1129 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
1130 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
1131 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
1132 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
1133 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
1134 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
1135 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
1136 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
1137 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
1138 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
1139 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
1140 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
1141 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
1142 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
1143 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
1144 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
1145 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
1146 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
1147 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
1148 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
1149 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
1150 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
1151 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
1152 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
1153 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
1154 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
1155 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
1156 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
1157 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
1158 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
1160 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
1161 vex_w_table, mod_table): Replace / remove respective entries.
1162 (print_insn): Move up dp->prefix_requirement handling. Handle
1164 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
1165 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
1166 Replace / remove respective entries.
1168 2020-07-14 Jan Beulich <jbeulich@suse.com>
1170 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
1171 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
1172 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
1173 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
1174 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
1176 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1177 0F2C, 0F2D, 0F2E, and 0F2F.
1178 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
1181 2020-07-14 Jan Beulich <jbeulich@suse.com>
1183 * i386-dis.c (OP_VexR, VexScalarR): New.
1184 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
1185 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
1186 need_vex_reg): Delete.
1187 (prefix_table): Replace VexScalar by VexScalarR and
1188 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1189 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1190 (vex_len_table): Replace EXqVexScalarS by EXqS.
1191 (get_valid_dis386): Don't set need_vex_reg.
1192 (print_insn): Don't initialize need_vex_reg.
1193 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
1194 q_scalar_swap_mode cases.
1195 (OP_EX): Don't check for d_scalar_swap_mode and
1197 (OP_VEX): Done check need_vex_reg.
1198 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
1199 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1200 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1202 2020-07-14 Jan Beulich <jbeulich@suse.com>
1204 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
1205 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
1206 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
1207 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
1208 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
1209 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
1210 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
1211 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
1212 (vex_table): Replace Vex128 by Vex.
1213 (vex_len_table): Likewise. Adjust referenced enum names.
1214 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
1215 referenced enum names.
1216 (OP_VEX): Drop vex128_mode and vex256_mode cases.
1217 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
1219 2020-07-14 Jan Beulich <jbeulich@suse.com>
1221 * i386-dis.c (dis386): "LW" description now applies to "DQ".
1222 (putop): Handle "DQ". Don't handle "LW" anymore.
1223 (prefix_table, mod_table): Replace %LW by %DQ.
1224 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
1226 2020-07-14 Jan Beulich <jbeulich@suse.com>
1228 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
1229 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
1230 d_scalar_swap_mode case handling. Move shift adjsutment into
1231 the case its applicable to.
1233 2020-07-14 Jan Beulich <jbeulich@suse.com>
1235 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
1236 (EXbScalar, EXwScalar): Fold to ...
1237 (EXbwUnit): ... this.
1238 (b_scalar_mode, w_scalar_mode): Fold to ...
1239 (bw_unit_mode): ... this.
1240 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
1241 w_scalar_mode handling by bw_unit_mode one.
1242 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
1244 * i386-dis-evex-prefix.h: ... here.
1246 2020-07-14 Jan Beulich <jbeulich@suse.com>
1248 * i386-dis.c (PCMPESTR_Fixup): Delete.
1249 (dis386): Adjust "LQ" description.
1250 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
1251 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
1252 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
1253 vpcmpestrm, and vpcmpestri.
1254 (putop): Honor "cond" when handling LQ.
1255 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
1256 vcvtsi2ss and vcvtusi2ss.
1257 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
1258 vcvtsi2sd and vcvtusi2sd.
1260 2020-07-14 Jan Beulich <jbeulich@suse.com>
1262 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
1263 (simd_cmp_op): Add const.
1264 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
1265 (CMP_Fixup): Handle VEX case.
1266 (prefix_table): Replace VCMP by CMP.
1267 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
1269 2020-07-14 Jan Beulich <jbeulich@suse.com>
1271 * i386-dis.c (MOVBE_Fixup): Delete.
1273 (prefix_table): Use Mv for movbe entries.
1275 2020-07-14 Jan Beulich <jbeulich@suse.com>
1277 * i386-dis.c (CRC32_Fixup): Delete.
1278 (prefix_table): Use Eb/Ev for crc32 entries.
1280 2020-07-14 Jan Beulich <jbeulich@suse.com>
1282 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
1283 Conditionalize invocations of "USED_REX (0)".
1285 2020-07-14 Jan Beulich <jbeulich@suse.com>
1287 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
1288 CH, DH, BH, AX, DX): Delete.
1289 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
1290 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
1291 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
1293 2020-07-10 Lili Cui <lili.cui@intel.com>
1295 * i386-dis.c (TMM): New.
1298 (MVexSIBMEM): Likewise.
1299 (tmm_mode): Likewise.
1300 (vex_sibmem_mode): Likewise.
1301 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
1302 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
1303 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
1304 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
1305 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
1306 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
1307 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
1308 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
1309 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
1310 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
1311 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
1312 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
1313 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
1314 (PREFIX_VEX_0F3849_X86_64): Likewise.
1315 (PREFIX_VEX_0F384B_X86_64): Likewise.
1316 (PREFIX_VEX_0F385C_X86_64): Likewise.
1317 (PREFIX_VEX_0F385E_X86_64): Likewise.
1318 (X86_64_VEX_0F3849): Likewise.
1319 (X86_64_VEX_0F384B): Likewise.
1320 (X86_64_VEX_0F385C): Likewise.
1321 (X86_64_VEX_0F385E): Likewise.
1322 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
1323 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
1324 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
1325 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
1326 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
1327 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
1328 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
1329 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
1330 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
1331 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
1332 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
1333 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
1334 (VEX_W_0F3849_X86_64_P_0): Likewise.
1335 (VEX_W_0F3849_X86_64_P_2): Likewise.
1336 (VEX_W_0F3849_X86_64_P_3): Likewise.
1337 (VEX_W_0F384B_X86_64_P_1): Likewise.
1338 (VEX_W_0F384B_X86_64_P_2): Likewise.
1339 (VEX_W_0F384B_X86_64_P_3): Likewise.
1340 (VEX_W_0F385C_X86_64_P_1): Likewise.
1341 (VEX_W_0F385E_X86_64_P_0): Likewise.
1342 (VEX_W_0F385E_X86_64_P_1): Likewise.
1343 (VEX_W_0F385E_X86_64_P_2): Likewise.
1344 (VEX_W_0F385E_X86_64_P_3): Likewise.
1345 (names_tmm): Likewise.
1346 (att_names_tmm): Likewise.
1347 (intel_operand_size): Handle void_mode.
1348 (OP_XMM): Handle tmm_mode.
1351 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
1352 CpuAMX_BF16 and CpuAMX_TILE.
1353 (operand_type_shorthands): Add RegTMM.
1354 (operand_type_init): Likewise.
1355 (operand_types): Add Tmmword.
1356 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1357 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1358 * i386-opc.h (CpuAMX_INT8): New.
1359 (CpuAMX_BF16): Likewise.
1360 (CpuAMX_TILE): Likewise.
1362 (Tmmword): Likewise.
1363 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
1364 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
1365 (i386_operand_type): Add tmmword.
1366 * i386-opc.tbl: Add AMX instructions.
1367 * i386-reg.tbl: Add AMX registers.
1368 * i386-init.h: Regenerated.
1369 * i386-tbl.h: Likewise.
1371 2020-07-08 Jan Beulich <jbeulich@suse.com>
1373 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1374 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1376 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1377 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1379 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1380 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1381 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1382 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1383 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1384 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1385 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1386 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1387 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1388 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1389 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1390 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1391 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1392 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1393 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1394 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1395 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1396 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1397 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1398 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1399 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1400 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1401 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1402 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1403 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1404 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1405 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1406 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1407 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1408 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1409 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1410 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1411 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1412 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1413 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1414 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1415 (reg_table): Re-order XOP entries. Adjust their operands.
1416 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1417 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1418 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1419 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1420 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1421 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1422 entries by references ...
1423 (vex_len_table): ... to resepctive new entries here. For several
1424 new and existing entries reference ...
1425 (vex_w_table): ... new entries here.
1426 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1428 2020-07-08 Jan Beulich <jbeulich@suse.com>
1430 * i386-dis.c (XMVexScalarI4): Define.
1431 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1432 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1433 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1434 (vex_len_table): Move scalar FMA4 entries ...
1435 (prefix_table): ... here.
1436 (OP_REG_VexI4): Handle scalar_mode.
1437 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1438 * i386-tbl.h: Re-generate.
1440 2020-07-08 Jan Beulich <jbeulich@suse.com>
1442 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1443 Vex_2src_2): Delete.
1444 (OP_VexW, VexW): New.
1445 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1446 for shifts and rotates by register.
1448 2020-07-08 Jan Beulich <jbeulich@suse.com>
1450 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1451 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1452 OP_EX_VexReg): Delete.
1453 (OP_VexI4, VexI4): New.
1454 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1455 (prefix_table): ... here.
1456 (print_insn): Drop setting of vex_w_done.
1458 2020-07-08 Jan Beulich <jbeulich@suse.com>
1460 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1461 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1462 (xop_table): Replace operands of 4-operand insns.
1463 (OP_REG_VexI4): Move VEX.W based operand swaping here.
1465 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
1467 * arc-opc.c (insert_rbd): New function.
1470 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1473 2020-07-07 Jan Beulich <jbeulich@suse.com>
1475 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1476 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1477 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1478 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1480 (putop): Handle "BW".
1481 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1482 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1484 * i386-dis-evex-prefix.h: ... here.
1486 2020-07-06 Jan Beulich <jbeulich@suse.com>
1488 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1489 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1490 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1491 VEX_W_0FXOP_09_83): New enumerators.
1492 (xop_table): Reference the above.
1493 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1494 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1495 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1496 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1498 2020-07-06 Jan Beulich <jbeulich@suse.com>
1500 * i386-dis.c (EVEX_W_0F3838_P_1,
1501 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1502 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1503 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1504 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1505 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1506 (putop): Centralize management of last[]. Delete SAVE_LAST.
1507 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1508 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1509 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1510 * i386-dis-evex-prefix.h: here.
1512 2020-07-06 Jan Beulich <jbeulich@suse.com>
1514 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1515 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1516 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1517 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1519 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1520 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1521 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1522 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1523 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1524 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1525 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1526 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1527 these, respectively.
1528 * i386-dis-evex-len.h: Adjust comments.
1529 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1530 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1531 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1532 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1533 MOD_EVEX_0F385B_P_2_W_1 table entries.
1534 * i386-dis-evex-w.h: Reference mod_table[] for
1535 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1538 2020-07-06 Jan Beulich <jbeulich@suse.com>
1540 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1541 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1543 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1544 Likewise. Mark 256-bit entries invalid.
1546 2020-07-06 Jan Beulich <jbeulich@suse.com>
1548 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1549 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1550 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1551 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1552 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1553 PREFIX_EVEX_0F382B): Delete.
1554 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1555 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1556 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1557 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1558 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1560 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1561 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1562 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1563 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1565 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1566 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1567 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1568 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1569 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1570 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1571 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1572 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1573 PREFIX_EVEX_0F382B): Remove table entries.
1574 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1575 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1576 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1578 2020-07-06 Jan Beulich <jbeulich@suse.com>
1580 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1581 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1583 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1584 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1585 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1586 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1589 2020-07-06 Jan Beulich <jbeulich@suse.com>
1591 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1592 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1593 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1594 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1595 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1596 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1597 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1598 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1599 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1602 2020-07-06 Jan Beulich <jbeulich@suse.com>
1604 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1605 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1606 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1608 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1610 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1612 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1614 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1616 2020-07-06 Jan Beulich <jbeulich@suse.com>
1618 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1619 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1620 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1621 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1622 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1623 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1624 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1625 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1626 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1627 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1628 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1629 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1630 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1631 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1632 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1633 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1634 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1635 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1636 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1637 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1638 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1639 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1640 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1641 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1642 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1643 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1644 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1645 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1646 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1647 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1648 (prefix_table): Add EXxEVexR to FMA table entries.
1649 (OP_Rounding): Move abort() invocation.
1650 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1651 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1652 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1653 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1654 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1655 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1656 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1657 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1658 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1659 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1661 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1662 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1663 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1664 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1665 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1666 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1667 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1668 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1669 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1670 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1671 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1672 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1673 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1674 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1675 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1676 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1677 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1678 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1679 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1680 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1681 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1682 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1683 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1684 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1685 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1686 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1687 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1688 Delete table entries.
1689 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1690 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1691 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1694 2020-07-06 Jan Beulich <jbeulich@suse.com>
1696 * i386-dis.c (EXqScalarS): Delete.
1697 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1698 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1700 2020-07-06 Jan Beulich <jbeulich@suse.com>
1702 * i386-dis.c (safe-ctype.h): Include.
1703 (EXdScalar, EXqScalar): Delete.
1704 (d_scalar_mode, q_scalar_mode): Delete.
1705 (prefix_table, vex_len_table): Use EXxmm_md in place of
1706 EXdScalar and EXxmm_mq in place of EXqScalar.
1707 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1708 d_scalar_mode and q_scalar_mode.
1709 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1710 (vmovsd): Use EXxmm_mq.
1712 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1715 * arc-dis.c: Fix spelling mistake.
1716 * po/opcodes.pot: Regenerate.
1718 2020-07-06 Nick Clifton <nickc@redhat.com>
1720 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1721 * po/uk.po: Updated Ukranian translation.
1723 2020-07-04 Nick Clifton <nickc@redhat.com>
1725 * configure: Regenerate.
1726 * po/opcodes.pot: Regenerate.
1728 2020-07-04 Nick Clifton <nickc@redhat.com>
1730 Binutils 2.35 branch created.
1732 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1734 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1735 * i386-opc.h (VexSwapSources): New.
1736 (i386_opcode_modifier): Add vexswapsources.
1737 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1738 with two source operands swapped.
1739 * i386-tbl.h: Regenerated.
1741 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1743 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1744 unprivileged CSR can also be initialized.
1746 2020-06-29 Alan Modra <amodra@gmail.com>
1748 * arm-dis.c: Use C style comments.
1749 * cr16-opc.c: Likewise.
1750 * ft32-dis.c: Likewise.
1751 * moxie-opc.c: Likewise.
1752 * tic54x-dis.c: Likewise.
1753 * s12z-opc.c: Remove useless comment.
1754 * xgate-dis.c: Likewise.
1756 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1758 * i386-opc.tbl: Add a blank line.
1760 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1762 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1763 (VecSIB128): Renamed to ...
1765 (VecSIB256): Renamed to ...
1767 (VecSIB512): Renamed to ...
1769 (VecSIB): Renamed to ...
1771 (i386_opcode_modifier): Replace vecsib with sib.
1772 * i386-opc.tbl (VecSIB128): New.
1773 (VecSIB256): Likewise.
1774 (VecSIB512): Likewise.
1775 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1776 and VecSIB512, respectively.
1778 2020-06-26 Jan Beulich <jbeulich@suse.com>
1780 * i386-dis.c: Adjust description of I macro.
1781 (x86_64_table): Drop use of I.
1782 (float_mem): Replace use of I.
1783 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1785 2020-06-26 Jan Beulich <jbeulich@suse.com>
1787 * i386-dis.c: (print_insn): Avoid straight assignment to
1788 priv.orig_sizeflag when processing -M sub-options.
1790 2020-06-25 Jan Beulich <jbeulich@suse.com>
1792 * i386-dis.c: Adjust description of J macro.
1793 (dis386, x86_64_table, mod_table): Replace J.
1794 (putop): Remove handling of J.
1796 2020-06-25 Jan Beulich <jbeulich@suse.com>
1798 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1800 2020-06-25 Jan Beulich <jbeulich@suse.com>
1802 * i386-dis.c: Adjust description of "LQ" macro.
1803 (dis386_twobyte): Use LQ for sysret.
1804 (putop): Adjust handling of LQ.
1806 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1808 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1809 * riscv-dis.c: Include elfxx-riscv.h.
1811 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1813 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1815 2020-06-17 Lili Cui <lili.cui@intel.com>
1817 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1819 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1822 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1823 * i386-opc.tbl: Likewise.
1824 * i386-tbl.h: Regenerated.
1826 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1828 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1830 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1832 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1833 (SR_CORE): Likewise.
1834 (SR_FEAT): Likewise.
1836 (SR_V8_1): Likewise.
1837 (SR_V8_2): Likewise.
1838 (SR_V8_3): Likewise.
1839 (SR_V8_4): Likewise.
1842 (SR_SSBS): Likewise.
1844 (SR_ID_PFR2): Likewise.
1845 (SR_PROFILE): Likewise.
1846 (SR_MEMTAG): Likewise.
1847 (SR_SCXTNUM): Likewise.
1848 (aarch64_sys_regs): Refactor to store feature information in the table.
1849 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1850 that now describe their own features.
1851 (aarch64_pstatefield_supported_p): Likewise.
1853 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1855 * i386-dis.c (prefix_table): Fix a typo in comments.
1857 2020-06-09 Jan Beulich <jbeulich@suse.com>
1859 * i386-dis.c (rex_ignored): Delete.
1860 (ckprefix): Drop rex_ignored initialization.
1861 (get_valid_dis386): Drop setting of rex_ignored.
1862 (print_insn): Drop checking of rex_ignored. Don't record data
1863 size prefix as used with VEX-and-alike encodings.
1865 2020-06-09 Jan Beulich <jbeulich@suse.com>
1867 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1868 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1869 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1870 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1871 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1872 VEX_0F12, and VEX_0F16.
1873 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1874 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1875 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1876 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1877 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1878 MOD_VEX_0F16_PREFIX_2 entries.
1880 2020-06-09 Jan Beulich <jbeulich@suse.com>
1882 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1883 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1884 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1885 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1886 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1887 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1888 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1889 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1890 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1891 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1892 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1893 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1894 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1895 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1896 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1897 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1898 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1899 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1900 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1901 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1902 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1903 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1904 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1905 EVEX_W_0FC6_P_2): Delete.
1906 (print_insn): Add EVEX.W vs embedded prefix consistency check
1907 to prefix validation.
1908 * i386-dis-evex.h (evex_table): Don't further descend for
1909 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1910 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1912 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1913 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1914 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1915 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1916 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1917 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1918 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1919 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1920 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1921 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1922 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1923 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1924 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1925 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1926 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1927 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1928 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1929 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1930 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1931 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1932 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1933 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1934 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1935 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1936 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1937 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1938 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1940 2020-06-09 Jan Beulich <jbeulich@suse.com>
1942 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1943 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1944 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1946 (print_insn): Drop pointless check against bad_opcode. Split
1947 prefix validation into legacy and VEX-and-alike parts.
1948 (putop): Re-work 'X' macro handling.
1950 2020-06-09 Jan Beulich <jbeulich@suse.com>
1952 * i386-dis.c (MOD_0F51): Rename to ...
1953 (MOD_0F50): ... this.
1955 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1957 * arm-dis.c (arm_opcodes): Add dfb.
1958 (thumb32_opcodes): Add dfb.
1960 2020-06-08 Jan Beulich <jbeulich@suse.com>
1962 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1964 2020-06-06 Alan Modra <amodra@gmail.com>
1966 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1968 2020-06-05 Alan Modra <amodra@gmail.com>
1970 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1971 size is large enough.
1973 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1975 * disassemble.c (disassemble_init_for_target): Set endian_code for
1977 * bpf-desc.c: Regenerate.
1978 * bpf-opc.c: Likewise.
1979 * bpf-dis.c: Likewise.
1981 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1983 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1984 (cgen_put_insn_value): Likewise.
1985 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1986 * cgen-dis.in (print_insn): Likewise.
1987 * cgen-ibld.in (insert_1): Likewise.
1988 (insert_1): Likewise.
1989 (insert_insn_normal): Likewise.
1990 (extract_1): Likewise.
1991 * bpf-dis.c: Regenerate.
1992 * bpf-ibld.c: Likewise.
1993 * bpf-ibld.c: Likewise.
1994 * cgen-dis.in: Likewise.
1995 * cgen-ibld.in: Likewise.
1996 * cgen-opc.c: Likewise.
1997 * epiphany-dis.c: Likewise.
1998 * epiphany-ibld.c: Likewise.
1999 * fr30-dis.c: Likewise.
2000 * fr30-ibld.c: Likewise.
2001 * frv-dis.c: Likewise.
2002 * frv-ibld.c: Likewise.
2003 * ip2k-dis.c: Likewise.
2004 * ip2k-ibld.c: Likewise.
2005 * iq2000-dis.c: Likewise.
2006 * iq2000-ibld.c: Likewise.
2007 * lm32-dis.c: Likewise.
2008 * lm32-ibld.c: Likewise.
2009 * m32c-dis.c: Likewise.
2010 * m32c-ibld.c: Likewise.
2011 * m32r-dis.c: Likewise.
2012 * m32r-ibld.c: Likewise.
2013 * mep-dis.c: Likewise.
2014 * mep-ibld.c: Likewise.
2015 * mt-dis.c: Likewise.
2016 * mt-ibld.c: Likewise.
2017 * or1k-dis.c: Likewise.
2018 * or1k-ibld.c: Likewise.
2019 * xc16x-dis.c: Likewise.
2020 * xc16x-ibld.c: Likewise.
2021 * xstormy16-dis.c: Likewise.
2022 * xstormy16-ibld.c: Likewise.
2024 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
2026 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
2027 (print_insn_): Handle instruction endian.
2028 * bpf-dis.c: Regenerate.
2029 * bpf-desc.c: Regenerate.
2030 * epiphany-dis.c: Likewise.
2031 * epiphany-desc.c: Likewise.
2032 * fr30-dis.c: Likewise.
2033 * fr30-desc.c: Likewise.
2034 * frv-dis.c: Likewise.
2035 * frv-desc.c: Likewise.
2036 * ip2k-dis.c: Likewise.
2037 * ip2k-desc.c: Likewise.
2038 * iq2000-dis.c: Likewise.
2039 * iq2000-desc.c: Likewise.
2040 * lm32-dis.c: Likewise.
2041 * lm32-desc.c: Likewise.
2042 * m32c-dis.c: Likewise.
2043 * m32c-desc.c: Likewise.
2044 * m32r-dis.c: Likewise.
2045 * m32r-desc.c: Likewise.
2046 * mep-dis.c: Likewise.
2047 * mep-desc.c: Likewise.
2048 * mt-dis.c: Likewise.
2049 * mt-desc.c: Likewise.
2050 * or1k-dis.c: Likewise.
2051 * or1k-desc.c: Likewise.
2052 * xc16x-dis.c: Likewise.
2053 * xc16x-desc.c: Likewise.
2054 * xstormy16-dis.c: Likewise.
2055 * xstormy16-desc.c: Likewise.
2057 2020-06-03 Nick Clifton <nickc@redhat.com>
2059 * po/sr.po: Updated Serbian translation.
2061 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
2063 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
2064 (riscv_get_priv_spec_class): Likewise.
2066 2020-06-01 Alan Modra <amodra@gmail.com>
2068 * bpf-desc.c: Regenerate.
2070 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
2071 David Faust <david.faust@oracle.com>
2073 * bpf-desc.c: Regenerate.
2074 * bpf-opc.h: Likewise.
2075 * bpf-opc.c: Likewise.
2076 * bpf-dis.c: Likewise.
2078 2020-05-28 Alan Modra <amodra@gmail.com>
2080 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
2083 2020-05-28 Alan Modra <amodra@gmail.com>
2085 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
2087 (print_insn_ns32k): Revert last change.
2089 2020-05-28 Nick Clifton <nickc@redhat.com>
2091 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
2094 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
2096 Fix extraction of signed constants in nios2 disassembler (again).
2098 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
2099 extractions of signed fields.
2101 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2103 * s390-opc.txt: Relocate vector load/store instructions with
2104 additional alignment parameter and change architecture level
2105 constraint from z14 to z13.
2107 2020-05-21 Alan Modra <amodra@gmail.com>
2109 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
2110 * sparc-dis.c: Likewise.
2111 * tic4x-dis.c: Likewise.
2112 * xtensa-dis.c: Likewise.
2113 * bpf-desc.c: Regenerate.
2114 * epiphany-desc.c: Regenerate.
2115 * fr30-desc.c: Regenerate.
2116 * frv-desc.c: Regenerate.
2117 * ip2k-desc.c: Regenerate.
2118 * iq2000-desc.c: Regenerate.
2119 * lm32-desc.c: Regenerate.
2120 * m32c-desc.c: Regenerate.
2121 * m32r-desc.c: Regenerate.
2122 * mep-asm.c: Regenerate.
2123 * mep-desc.c: Regenerate.
2124 * mt-desc.c: Regenerate.
2125 * or1k-desc.c: Regenerate.
2126 * xc16x-desc.c: Regenerate.
2127 * xstormy16-desc.c: Regenerate.
2129 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
2131 * riscv-opc.c (riscv_ext_version_table): The table used to store
2132 all information about the supported spec and the corresponding ISA
2133 versions. Currently, only Zicsr is supported to verify the
2134 correctness of Z sub extension settings. Others will be supported
2135 in the future patches.
2136 (struct isa_spec_t, isa_specs): List for all supported ISA spec
2137 classes and the corresponding strings.
2138 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
2139 spec class by giving a ISA spec string.
2140 * riscv-opc.c (struct priv_spec_t): New structure.
2141 (struct priv_spec_t priv_specs): List for all supported privilege spec
2142 classes and the corresponding strings.
2143 (riscv_get_priv_spec_class): New function. Get the corresponding
2144 privilege spec class by giving a spec string.
2145 (riscv_get_priv_spec_name): New function. Get the corresponding
2146 privilege spec string by giving a CSR version class.
2147 * riscv-dis.c: Updated since DECLARE_CSR is changed.
2148 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
2149 according to the chosen version. Build a hash table riscv_csr_hash to
2150 store the valid CSR for the chosen pirv verison. Dump the direct
2151 CSR address rather than it's name if it is invalid.
2152 (parse_riscv_dis_option_without_args): New function. Parse the options
2154 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
2155 parse the options without arguments first, and then handle the options
2156 with arguments. Add the new option -Mpriv-spec, which has argument.
2157 * riscv-dis.c (print_riscv_disassembler_options): Add description
2158 about the new OBJDUMP option.
2160 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
2162 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
2163 WC values on POWER10 sync, dcbf and wait instructions.
2164 (insert_pl, extract_pl): New functions.
2165 (L2OPT, LS, WC): Use insert_ls and extract_ls.
2166 (LS3): New , 3-bit L for sync.
2167 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
2168 (SC2, PL): New, 2-bit SC and PL for sync and wait.
2169 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
2170 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
2171 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
2172 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
2173 <wait>: Enable PL operand on POWER10.
2174 <dcbf>: Enable L3OPT operand on POWER10.
2175 <sync>: Enable SC2 operand on POWER10.
2177 2020-05-19 Stafford Horne <shorne@gmail.com>
2180 * or1k-asm.c: Regenerate.
2181 * or1k-desc.c: Regenerate.
2182 * or1k-desc.h: Regenerate.
2183 * or1k-dis.c: Regenerate.
2184 * or1k-ibld.c: Regenerate.
2185 * or1k-opc.c: Regenerate.
2186 * or1k-opc.h: Regenerate.
2187 * or1k-opinst.c: Regenerate.
2189 2020-05-11 Alan Modra <amodra@gmail.com>
2191 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
2194 2020-05-11 Alan Modra <amodra@gmail.com>
2196 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
2197 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
2199 2020-05-11 Alan Modra <amodra@gmail.com>
2201 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
2203 2020-05-11 Alan Modra <amodra@gmail.com>
2205 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
2206 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
2208 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2210 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
2213 2020-05-11 Alan Modra <amodra@gmail.com>
2215 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
2216 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
2217 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
2218 (prefix_opcodes): Add xxeval.
2220 2020-05-11 Alan Modra <amodra@gmail.com>
2222 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
2223 xxgenpcvwm, xxgenpcvdm.
2225 2020-05-11 Alan Modra <amodra@gmail.com>
2227 * ppc-opc.c (MP, VXVAM_MASK): Define.
2228 (VXVAPS_MASK): Use VXVA_MASK.
2229 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
2230 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
2231 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
2232 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
2234 2020-05-11 Alan Modra <amodra@gmail.com>
2235 Peter Bergner <bergner@linux.ibm.com>
2237 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
2239 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
2240 YMSK2, XA6a, XA6ap, XB6a entries.
2241 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
2242 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
2244 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
2245 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
2246 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
2247 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
2248 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
2249 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
2250 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
2251 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
2252 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
2253 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
2254 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
2255 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
2256 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
2257 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
2259 2020-05-11 Alan Modra <amodra@gmail.com>
2261 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
2262 (insert_xts, extract_xts): New functions.
2263 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
2264 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
2265 (VXRC_MASK, VXSH_MASK): Define.
2266 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
2267 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
2268 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
2269 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
2270 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
2271 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
2272 xxblendvh, xxblendvw, xxblendvd, xxpermx.
2274 2020-05-11 Alan Modra <amodra@gmail.com>
2276 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
2277 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
2278 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
2279 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
2280 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
2282 2020-05-11 Alan Modra <amodra@gmail.com>
2284 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
2285 (XTP, DQXP, DQXP_MASK): Define.
2286 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
2287 (prefix_opcodes): Add plxvp and pstxvp.
2289 2020-05-11 Alan Modra <amodra@gmail.com>
2291 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
2292 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
2293 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
2295 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2297 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
2299 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2301 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
2303 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
2305 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2307 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
2309 2020-05-11 Alan Modra <amodra@gmail.com>
2311 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
2313 2020-05-11 Alan Modra <amodra@gmail.com>
2315 * ppc-dis.c (ppc_opts): Add "power10" entry.
2316 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
2317 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
2319 2020-05-11 Nick Clifton <nickc@redhat.com>
2321 * po/fr.po: Updated French translation.
2323 2020-04-30 Alex Coplan <alex.coplan@arm.com>
2325 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
2326 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
2327 (operand_general_constraint_met_p): validate
2328 AARCH64_OPND_UNDEFINED.
2329 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
2331 * aarch64-asm-2.c: Regenerated.
2332 * aarch64-dis-2.c: Regenerated.
2333 * aarch64-opc-2.c: Regenerated.
2335 2020-04-29 Nick Clifton <nickc@redhat.com>
2338 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
2341 2020-04-29 Nick Clifton <nickc@redhat.com>
2343 * po/sv.po: Updated Swedish translation.
2345 2020-04-29 Nick Clifton <nickc@redhat.com>
2348 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
2349 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
2350 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
2353 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
2356 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
2357 cmpi only on m68020up and cpu32.
2359 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2361 * aarch64-asm.c (aarch64_ins_none): New.
2362 * aarch64-asm.h (ins_none): New declaration.
2363 * aarch64-dis.c (aarch64_ext_none): New.
2364 * aarch64-dis.h (ext_none): New declaration.
2365 * aarch64-opc.c (aarch64_print_operand): Update case for
2366 AARCH64_OPND_BARRIER_PSB.
2367 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2368 (AARCH64_OPERANDS): Update inserter/extracter for
2369 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2370 * aarch64-asm-2.c: Regenerated.
2371 * aarch64-dis-2.c: Regenerated.
2372 * aarch64-opc-2.c: Regenerated.
2374 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2376 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2377 (aarch64_feature_ras, RAS): Likewise.
2378 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2379 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2380 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2381 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2382 * aarch64-asm-2.c: Regenerated.
2383 * aarch64-dis-2.c: Regenerated.
2384 * aarch64-opc-2.c: Regenerated.
2386 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
2388 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2389 (print_insn_neon): Support disassembly of conditional
2392 2020-02-16 David Faust <david.faust@oracle.com>
2394 * bpf-desc.c: Regenerate.
2395 * bpf-desc.h: Likewise.
2396 * bpf-opc.c: Regenerate.
2397 * bpf-opc.h: Likewise.
2399 2020-04-07 Lili Cui <lili.cui@intel.com>
2401 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2402 (prefix_table): New instructions (see prefixes above).
2403 (rm_table): Likewise
2404 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2405 CPU_ANY_TSXLDTRK_FLAGS.
2406 (cpu_flags): Add CpuTSXLDTRK.
2407 * i386-opc.h (enum): Add CpuTSXLDTRK.
2408 (i386_cpu_flags): Add cputsxldtrk.
2409 * i386-opc.tbl: Add XSUSPLDTRK insns.
2410 * i386-init.h: Regenerate.
2411 * i386-tbl.h: Likewise.
2413 2020-04-02 Lili Cui <lili.cui@intel.com>
2415 * i386-dis.c (prefix_table): New instructions serialize.
2416 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2417 CPU_ANY_SERIALIZE_FLAGS.
2418 (cpu_flags): Add CpuSERIALIZE.
2419 * i386-opc.h (enum): Add CpuSERIALIZE.
2420 (i386_cpu_flags): Add cpuserialize.
2421 * i386-opc.tbl: Add SERIALIZE insns.
2422 * i386-init.h: Regenerate.
2423 * i386-tbl.h: Likewise.
2425 2020-03-26 Alan Modra <amodra@gmail.com>
2427 * disassemble.h (opcodes_assert): Declare.
2428 (OPCODES_ASSERT): Define.
2429 * disassemble.c: Don't include assert.h. Include opintl.h.
2430 (opcodes_assert): New function.
2431 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2432 (bfd_h8_disassemble): Reduce size of data array. Correctly
2433 calculate maxlen. Omit insn decoding when insn length exceeds
2434 maxlen. Exit from nibble loop when looking for E, before
2435 accessing next data byte. Move processing of E outside loop.
2436 Replace tests of maxlen in loop with assertions.
2438 2020-03-26 Alan Modra <amodra@gmail.com>
2440 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
2442 2020-03-25 Alan Modra <amodra@gmail.com>
2444 * z80-dis.c (suffix): Init mybuf.
2446 2020-03-22 Alan Modra <amodra@gmail.com>
2448 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2449 successflly read from section.
2451 2020-03-22 Alan Modra <amodra@gmail.com>
2453 * arc-dis.c (find_format): Use ISO C string concatenation rather
2454 than line continuation within a string. Don't access needs_limm
2455 before testing opcode != NULL.
2457 2020-03-22 Alan Modra <amodra@gmail.com>
2459 * ns32k-dis.c (print_insn_arg): Update comment.
2460 (print_insn_ns32k): Reduce size of index_offset array, and
2461 initialize, passing -1 to print_insn_arg for args that are not
2462 an index. Don't exit arg loop early. Abort on bad arg number.
2464 2020-03-22 Alan Modra <amodra@gmail.com>
2466 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2467 * s12z-opc.c: Formatting.
2468 (operands_f): Return an int.
2469 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2470 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2471 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2472 (exg_sex_discrim): Likewise.
2473 (create_immediate_operand, create_bitfield_operand),
2474 (create_register_operand_with_size, create_register_all_operand),
2475 (create_register_all16_operand, create_simple_memory_operand),
2476 (create_memory_operand, create_memory_auto_operand): Don't
2477 segfault on malloc failure.
2478 (z_ext24_decode): Return an int status, negative on fail, zero
2480 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2481 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2482 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2483 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2484 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2485 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2486 (loop_primitive_decode, shift_decode, psh_pul_decode),
2487 (bit_field_decode): Similarly.
2488 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
2489 to return value, update callers.
2490 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2491 Don't segfault on NULL operand.
2492 (decode_operation): Return OP_INVALID on first fail.
2493 (decode_s12z): Check all reads, returning -1 on fail.
2495 2020-03-20 Alan Modra <amodra@gmail.com>
2497 * metag-dis.c (print_insn_metag): Don't ignore status from
2500 2020-03-20 Alan Modra <amodra@gmail.com>
2502 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2503 Initialize parts of buffer not written when handling a possible
2504 2-byte insn at end of section. Don't attempt decoding of such
2505 an insn by the 4-byte machinery.
2507 2020-03-20 Alan Modra <amodra@gmail.com>
2509 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2510 partially filled buffer. Prevent lookup of 4-byte insns when
2511 only VLE 2-byte insns are possible due to section size. Print
2512 ".word" rather than ".long" for 2-byte leftovers.
2514 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2517 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2519 2020-03-13 Jan Beulich <jbeulich@suse.com>
2521 * i386-dis.c (X86_64_0D): Rename to ...
2522 (X86_64_0E): ... this.
2524 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2526 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2527 * Makefile.in: Regenerated.
2529 2020-03-09 Jan Beulich <jbeulich@suse.com>
2531 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2533 * i386-tbl.h: Re-generate.
2535 2020-03-09 Jan Beulich <jbeulich@suse.com>
2537 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2538 vprot*, vpsha*, and vpshl*.
2539 * i386-tbl.h: Re-generate.
2541 2020-03-09 Jan Beulich <jbeulich@suse.com>
2543 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2544 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2545 * i386-tbl.h: Re-generate.
2547 2020-03-09 Jan Beulich <jbeulich@suse.com>
2549 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2550 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2551 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2552 * i386-tbl.h: Re-generate.
2554 2020-03-09 Jan Beulich <jbeulich@suse.com>
2556 * i386-gen.c (struct template_arg, struct template_instance,
2557 struct template_param, struct template, templates,
2558 parse_template, expand_templates): New.
2559 (process_i386_opcodes): Various local variables moved to
2560 expand_templates. Call parse_template and expand_templates.
2561 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2562 * i386-tbl.h: Re-generate.
2564 2020-03-06 Jan Beulich <jbeulich@suse.com>
2566 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2567 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2568 register and memory source templates. Replace VexW= by VexW*
2570 * i386-tbl.h: Re-generate.
2572 2020-03-06 Jan Beulich <jbeulich@suse.com>
2574 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2575 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2576 * i386-tbl.h: Re-generate.
2578 2020-03-06 Jan Beulich <jbeulich@suse.com>
2580 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2581 * i386-tbl.h: Re-generate.
2583 2020-03-06 Jan Beulich <jbeulich@suse.com>
2585 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2586 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2587 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2588 VexW0 on SSE2AVX variants.
2589 (vmovq): Drop NoRex64 from XMM/XMM variants.
2590 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2591 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2592 applicable use VexW0.
2593 * i386-tbl.h: Re-generate.
2595 2020-03-06 Jan Beulich <jbeulich@suse.com>
2597 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2598 * i386-opc.h (Rex64): Delete.
2599 (struct i386_opcode_modifier): Remove rex64 field.
2600 * i386-opc.tbl (crc32): Drop Rex64.
2601 Replace Rex64 with Size64 everywhere else.
2602 * i386-tbl.h: Re-generate.
2604 2020-03-06 Jan Beulich <jbeulich@suse.com>
2606 * i386-dis.c (OP_E_memory): Exclude recording of used address
2607 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2608 addressed memory operands for MPX insns.
2610 2020-03-06 Jan Beulich <jbeulich@suse.com>
2612 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2613 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2614 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2615 (ptwrite): Split into non-64-bit and 64-bit forms.
2616 * i386-tbl.h: Re-generate.
2618 2020-03-06 Jan Beulich <jbeulich@suse.com>
2620 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2622 * i386-tbl.h: Re-generate.
2624 2020-03-04 Jan Beulich <jbeulich@suse.com>
2626 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2627 (prefix_table): Move vmmcall here. Add vmgexit.
2628 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2629 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2630 (cpu_flags): Add CpuSEV_ES entry.
2631 * i386-opc.h (CpuSEV_ES): New.
2632 (union i386_cpu_flags): Add cpusev_es field.
2633 * i386-opc.tbl (vmgexit): New.
2634 * i386-init.h, i386-tbl.h: Re-generate.
2636 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2638 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2640 * i386-opc.h (IGNORESIZE): New.
2641 (DEFAULTSIZE): Likewise.
2642 (IgnoreSize): Removed.
2643 (DefaultSize): Likewise.
2644 (MnemonicSize): New.
2645 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2647 * i386-opc.tbl (IgnoreSize): New.
2648 (DefaultSize): Likewise.
2649 * i386-tbl.h: Regenerated.
2651 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2654 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2657 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2660 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2661 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2662 * i386-tbl.h: Regenerated.
2664 2020-02-26 Alan Modra <amodra@gmail.com>
2666 * aarch64-asm.c: Indent labels correctly.
2667 * aarch64-dis.c: Likewise.
2668 * aarch64-gen.c: Likewise.
2669 * aarch64-opc.c: Likewise.
2670 * alpha-dis.c: Likewise.
2671 * i386-dis.c: Likewise.
2672 * nds32-asm.c: Likewise.
2673 * nfp-dis.c: Likewise.
2674 * visium-dis.c: Likewise.
2676 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2678 * arc-regs.h (int_vector_base): Make it available for all ARC
2681 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2683 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2686 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2688 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2689 c.mv/c.li if rs1 is zero.
2691 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2693 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2694 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2696 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2697 * i386-opc.h (CpuABM): Removed.
2699 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2700 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2701 popcnt. Remove CpuABM from lzcnt.
2702 * i386-init.h: Regenerated.
2703 * i386-tbl.h: Likewise.
2705 2020-02-17 Jan Beulich <jbeulich@suse.com>
2707 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2708 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2709 VexW1 instead of open-coding them.
2710 * i386-tbl.h: Re-generate.
2712 2020-02-17 Jan Beulich <jbeulich@suse.com>
2714 * i386-opc.tbl (AddrPrefixOpReg): Define.
2715 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2716 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2717 templates. Drop NoRex64.
2718 * i386-tbl.h: Re-generate.
2720 2020-02-17 Jan Beulich <jbeulich@suse.com>
2723 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2724 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2725 into Intel syntax instance (with Unpsecified) and AT&T one
2727 (vcvtneps2bf16): Likewise, along with folding the two so far
2729 * i386-tbl.h: Re-generate.
2731 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2733 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2734 CPU_ANY_SSE4A_FLAGS.
2736 2020-02-17 Alan Modra <amodra@gmail.com>
2738 * i386-gen.c (cpu_flag_init): Correct last change.
2740 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2742 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2745 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2747 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2750 2020-02-14 Jan Beulich <jbeulich@suse.com>
2753 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2754 destination for Cpu64-only variant.
2755 (movzx): Fold patterns.
2756 * i386-tbl.h: Re-generate.
2758 2020-02-13 Jan Beulich <jbeulich@suse.com>
2760 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2761 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2762 CPU_ANY_SSE4_FLAGS entry.
2763 * i386-init.h: Re-generate.
2765 2020-02-12 Jan Beulich <jbeulich@suse.com>
2767 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2768 with Unspecified, making the present one AT&T syntax only.
2769 * i386-tbl.h: Re-generate.
2771 2020-02-12 Jan Beulich <jbeulich@suse.com>
2773 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2774 * i386-tbl.h: Re-generate.
2776 2020-02-12 Jan Beulich <jbeulich@suse.com>
2779 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2780 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2781 Amd64 and Intel64 templates.
2782 (call, jmp): Likewise for far indirect variants. Dro
2784 * i386-tbl.h: Re-generate.
2786 2020-02-11 Jan Beulich <jbeulich@suse.com>
2788 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2789 * i386-opc.h (ShortForm): Delete.
2790 (struct i386_opcode_modifier): Remove shortform field.
2791 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2792 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2793 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2794 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2796 * i386-tbl.h: Re-generate.
2798 2020-02-11 Jan Beulich <jbeulich@suse.com>
2800 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2801 fucompi): Drop ShortForm from operand-less templates.
2802 * i386-tbl.h: Re-generate.
2804 2020-02-11 Alan Modra <amodra@gmail.com>
2806 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2807 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2808 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2809 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2810 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2812 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2814 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2815 (cde_opcodes): Add VCX* instructions.
2817 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2818 Matthew Malcomson <matthew.malcomson@arm.com>
2820 * arm-dis.c (struct cdeopcode32): New.
2821 (CDE_OPCODE): New macro.
2822 (cde_opcodes): New disassembly table.
2823 (regnames): New option to table.
2824 (cde_coprocs): New global variable.
2825 (print_insn_cde): New
2826 (print_insn_thumb32): Use print_insn_cde.
2827 (parse_arm_disassembler_options): Parse coprocN args.
2829 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2832 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2834 * i386-opc.h (AMD64): Removed.
2835 (Intel64): Likewose.
2837 (INTEL64): Likewise.
2838 (INTEL64ONLY): Likewise.
2839 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2840 * i386-opc.tbl (Amd64): New.
2841 (Intel64): Likewise.
2842 (Intel64Only): Likewise.
2843 Replace AMD64 with Amd64. Update sysenter/sysenter with
2844 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2845 * i386-tbl.h: Regenerated.
2847 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2850 * z80-dis.c: Add support for GBZ80 opcodes.
2852 2020-02-04 Alan Modra <amodra@gmail.com>
2854 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2856 2020-02-03 Alan Modra <amodra@gmail.com>
2858 * m32c-ibld.c: Regenerate.
2860 2020-02-01 Alan Modra <amodra@gmail.com>
2862 * frv-ibld.c: Regenerate.
2864 2020-01-31 Jan Beulich <jbeulich@suse.com>
2866 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2867 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2868 (OP_E_memory): Replace xmm_mdq_mode case label by
2869 vex_scalar_w_dq_mode one.
2870 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2872 2020-01-31 Jan Beulich <jbeulich@suse.com>
2874 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2875 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2876 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2877 (intel_operand_size): Drop vex_w_dq_mode case label.
2879 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2881 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2882 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2884 2020-01-30 Alan Modra <amodra@gmail.com>
2886 * m32c-ibld.c: Regenerate.
2888 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2890 * bpf-opc.c: Regenerate.
2892 2020-01-30 Jan Beulich <jbeulich@suse.com>
2894 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2895 (dis386): Use them to replace C2/C3 table entries.
2896 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2897 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2898 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2899 * i386-tbl.h: Re-generate.
2901 2020-01-30 Jan Beulich <jbeulich@suse.com>
2903 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2905 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2907 * i386-tbl.h: Re-generate.
2909 2020-01-30 Alan Modra <amodra@gmail.com>
2911 * tic4x-dis.c (tic4x_dp): Make unsigned.
2913 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2914 Jan Beulich <jbeulich@suse.com>
2917 * i386-dis.c (MOVSXD_Fixup): New function.
2918 (movsxd_mode): New enum.
2919 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2920 (intel_operand_size): Handle movsxd_mode.
2921 (OP_E_register): Likewise.
2923 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2924 register on movsxd. Add movsxd with 16-bit destination register
2925 for AMD64 and Intel64 ISAs.
2926 * i386-tbl.h: Regenerated.
2928 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2931 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2932 * aarch64-asm-2.c: Regenerate
2933 * aarch64-dis-2.c: Likewise.
2934 * aarch64-opc-2.c: Likewise.
2936 2020-01-21 Jan Beulich <jbeulich@suse.com>
2938 * i386-opc.tbl (sysret): Drop DefaultSize.
2939 * i386-tbl.h: Re-generate.
2941 2020-01-21 Jan Beulich <jbeulich@suse.com>
2943 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2945 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2946 * i386-tbl.h: Re-generate.
2948 2020-01-20 Nick Clifton <nickc@redhat.com>
2950 * po/de.po: Updated German translation.
2951 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2952 * po/uk.po: Updated Ukranian translation.
2954 2020-01-20 Alan Modra <amodra@gmail.com>
2956 * hppa-dis.c (fput_const): Remove useless cast.
2958 2020-01-20 Alan Modra <amodra@gmail.com>
2960 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2962 2020-01-18 Nick Clifton <nickc@redhat.com>
2964 * configure: Regenerate.
2965 * po/opcodes.pot: Regenerate.
2967 2020-01-18 Nick Clifton <nickc@redhat.com>
2969 Binutils 2.34 branch created.
2971 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2973 * opintl.h: Fix spelling error (seperate).
2975 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2977 * i386-opc.tbl: Add {vex} pseudo prefix.
2978 * i386-tbl.h: Regenerated.
2980 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2983 * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2984 (neon_opcodes): Likewise.
2985 (select_arm_features): Make sure we enable MVE bits when selecting
2986 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2989 2020-01-16 Jan Beulich <jbeulich@suse.com>
2991 * i386-opc.tbl: Drop stale comment from XOP section.
2993 2020-01-16 Jan Beulich <jbeulich@suse.com>
2995 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2996 (extractps): Add VexWIG to SSE2AVX forms.
2997 * i386-tbl.h: Re-generate.
2999 2020-01-16 Jan Beulich <jbeulich@suse.com>
3001 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
3002 Size64 from and use VexW1 on SSE2AVX forms.
3003 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
3004 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
3005 * i386-tbl.h: Re-generate.
3007 2020-01-15 Alan Modra <amodra@gmail.com>
3009 * tic4x-dis.c (tic4x_version): Make unsigned long.
3010 (optab, optab_special, registernames): New file scope vars.
3011 (tic4x_print_register): Set up registernames rather than
3012 malloc'd registertable.
3013 (tic4x_disassemble): Delete optable and optable_special. Use
3014 optab and optab_special instead. Throw away old optab,
3015 optab_special and registernames when info->mach changes.
3017 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
3020 * z80-dis.c (suffix): Use .db instruction to generate double
3023 2020-01-14 Alan Modra <amodra@gmail.com>
3025 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
3026 values to unsigned before shifting.
3028 2020-01-13 Thomas Troeger <tstroege@gmx.de>
3030 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
3032 (print_insn_thumb16, print_insn_thumb32): Likewise.
3033 (print_insn): Initialize the insn info.
3034 * i386-dis.c (print_insn): Initialize the insn info fields, and
3037 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
3039 * arc-opc.c (C_NE): Make it required.
3041 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
3043 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
3044 reserved register name.
3046 2020-01-13 Alan Modra <amodra@gmail.com>
3048 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
3049 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
3051 2020-01-13 Alan Modra <amodra@gmail.com>
3053 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
3054 result of wasm_read_leb128 in a uint64_t and check that bits
3055 are not lost when copying to other locals. Use uint32_t for
3056 most locals. Use PRId64 when printing int64_t.
3058 2020-01-13 Alan Modra <amodra@gmail.com>
3060 * score-dis.c: Formatting.
3061 * score7-dis.c: Formatting.
3063 2020-01-13 Alan Modra <amodra@gmail.com>
3065 * score-dis.c (print_insn_score48): Use unsigned variables for
3066 unsigned values. Don't left shift negative values.
3067 (print_insn_score32): Likewise.
3068 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
3070 2020-01-13 Alan Modra <amodra@gmail.com>
3072 * tic4x-dis.c (tic4x_print_register): Remove dead code.
3074 2020-01-13 Alan Modra <amodra@gmail.com>
3076 * fr30-ibld.c: Regenerate.
3078 2020-01-13 Alan Modra <amodra@gmail.com>
3080 * xgate-dis.c (print_insn): Don't left shift signed value.
3081 (ripBits): Formatting, use 1u.
3083 2020-01-10 Alan Modra <amodra@gmail.com>
3085 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
3086 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
3088 2020-01-10 Alan Modra <amodra@gmail.com>
3090 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
3091 and XRREG value earlier to avoid a shift with negative exponent.
3092 * m10200-dis.c (disassemble): Similarly.
3094 2020-01-09 Nick Clifton <nickc@redhat.com>
3097 * z80-dis.c (ld_ii_ii): Use correct cast.
3099 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
3102 * z80-dis.c (ld_ii_ii): Use character constant when checking
3105 2020-01-09 Jan Beulich <jbeulich@suse.com>
3107 * i386-dis.c (SEP_Fixup): New.
3109 (dis386_twobyte): Use it for sysenter/sysexit.
3110 (enum x86_64_isa): Change amd64 enumerator to value 1.
3111 (OP_J): Compare isa64 against intel64 instead of amd64.
3112 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
3114 * i386-tbl.h: Re-generate.
3116 2020-01-08 Alan Modra <amodra@gmail.com>
3118 * z8k-dis.c: Include libiberty.h
3119 (instr_data_s): Make max_fetched unsigned.
3120 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
3121 Don't exceed byte_info bounds.
3122 (output_instr): Make num_bytes unsigned.
3123 (unpack_instr): Likewise for nibl_count and loop.
3124 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
3126 * z8k-opc.h: Regenerate.
3128 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
3130 * arc-tbl.h (llock): Use 'LLOCK' as class.
3132 (scond): Use 'SCOND' as class.
3134 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
3137 2020-01-06 Alan Modra <amodra@gmail.com>
3139 * m32c-ibld.c: Regenerate.
3141 2020-01-06 Alan Modra <amodra@gmail.com>
3144 * z80-dis.c (suffix): Don't use a local struct buffer copy.
3145 Peek at next byte to prevent recursion on repeated prefix bytes.
3146 Ensure uninitialised "mybuf" is not accessed.
3147 (print_insn_z80): Don't zero n_fetch and n_used here,..
3148 (print_insn_z80_buf): ..do it here instead.
3150 2020-01-04 Alan Modra <amodra@gmail.com>
3152 * m32r-ibld.c: Regenerate.
3154 2020-01-04 Alan Modra <amodra@gmail.com>
3156 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
3158 2020-01-04 Alan Modra <amodra@gmail.com>
3160 * crx-dis.c (match_opcode): Avoid shift left of signed value.
3162 2020-01-04 Alan Modra <amodra@gmail.com>
3164 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
3166 2020-01-03 Jan Beulich <jbeulich@suse.com>
3168 * aarch64-tbl.h (aarch64_opcode_table): Use
3169 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
3171 2020-01-03 Jan Beulich <jbeulich@suse.com>
3173 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
3174 forms of SUDOT and USDOT.
3176 2020-01-03 Jan Beulich <jbeulich@suse.com>
3178 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
3180 * aarch64-dis-2.c: Re-generate.
3182 2020-01-03 Jan Beulich <jbeulich@suse.com>
3184 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
3186 * aarch64-dis-2.c: Re-generate.
3188 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
3190 * z80-dis.c: Add support for eZ80 and Z80 instructions.
3192 2020-01-01 Alan Modra <amodra@gmail.com>
3194 Update year range in copyright notice of all files.
3196 For older changes see ChangeLog-2019
3198 Copyright (C) 2020 Free Software Foundation, Inc.
3200 Copying and distribution of this file, with or without modification,
3201 are permitted in any medium without royalty provided the copyright
3202 notice and this notice are preserved.
3208 version-control: never