1 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
3 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
4 sve_size_bh iclass encode.
5 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
6 sve_size_bh iclass decode.
8 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
10 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
11 sve_size_sd2 iclass encode.
12 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
13 sve_size_sd2 iclass decode.
14 * aarch64-opc.c (fields): Handle SVE_sz2 field.
15 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
17 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
19 * aarch64-asm-2.c: Regenerated.
20 * aarch64-dis-2.c: Regenerated.
21 * aarch64-opc-2.c: Regenerated.
22 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
24 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
25 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
27 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
29 * aarch64-asm-2.c: Regenerated.
30 * aarch64-dis-2.c: Regenerated.
31 * aarch64-opc-2.c: Regenerated.
32 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
34 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
35 (fields): Handle SVE_i3l and SVE_i3h2 fields.
36 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
38 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
40 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
42 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
43 sve_size_hsd2 iclass encode.
44 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
45 sve_size_hsd2 iclass decode.
46 * aarch64-opc.c (fields): Handle SVE_size field.
47 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
49 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
51 * aarch64-asm-2.c: Regenerated.
52 * aarch64-dis-2.c: Regenerated.
53 * aarch64-opc-2.c: Regenerated.
54 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
56 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
57 (fields): Handle SVE_rot3 field.
58 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
59 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
61 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
63 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
66 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
69 (aarch64_feature_sve2, aarch64_feature_sve2aes,
70 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
71 aarch64_feature_sve2bitperm): New feature sets.
72 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
73 for feature set addresses.
74 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
75 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
77 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
78 Faraz Shahbazker <fshahbazker@wavecomp.com>
80 * mips-dis.c (mips_calculate_combination_ases): Add ISA
81 argument and set ASE_EVA_R6 appropriately.
82 (set_default_mips_dis_options): Pass ISA to above.
83 (parse_mips_dis_option): Likewise.
84 * mips-opc.c (EVAR6): New macro.
85 (mips_builtin_opcodes): Add llwpe, scwpe.
87 2019-05-01 Sudakshina Das <sudi.das@arm.com>
89 * aarch64-asm-2.c: Regenerated.
90 * aarch64-dis-2.c: Regenerated.
91 * aarch64-opc-2.c: Regenerated.
92 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
93 AARCH64_OPND_TME_UIMM16.
94 (aarch64_print_operand): Likewise.
95 * aarch64-tbl.h (QL_IMM_NIL): New.
98 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
100 2019-04-29 John Darrington <john@darrington.wattle.id.au>
102 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
104 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
105 Faraz Shahbazker <fshahbazker@wavecomp.com>
107 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
109 2019-04-24 John Darrington <john@darrington.wattle.id.au>
111 * s12z-opc.h: Add extern "C" bracketing to help
112 users who wish to use this interface in c++ code.
114 2019-04-24 John Darrington <john@darrington.wattle.id.au>
116 * s12z-opc.c (bm_decode): Handle bit map operations with the
119 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
121 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
122 specifier. Add entries for VLDR and VSTR of system registers.
123 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
124 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
125 of %J and %K format specifier.
127 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
129 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
130 Add new entries for VSCCLRM instruction.
131 (print_insn_coprocessor): Handle new %C format control code.
133 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
135 * arm-dis.c (enum isa): New enum.
136 (struct sopcode32): New structure.
137 (coprocessor_opcodes): change type of entries to struct sopcode32 and
138 set isa field of all current entries to ANY.
139 (print_insn_coprocessor): Change type of insn to struct sopcode32.
140 Only match an entry if its isa field allows the current mode.
142 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
144 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
146 (print_insn_thumb32): Add logic to print %n CLRM register list.
148 2019-04-15 Sudakshina Das <sudi.das@arm.com>
150 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
153 2019-04-15 Sudakshina Das <sudi.das@arm.com>
155 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
156 (print_insn_thumb32): Edit the switch case for %Z.
158 2019-04-15 Sudakshina Das <sudi.das@arm.com>
160 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
162 2019-04-15 Sudakshina Das <sudi.das@arm.com>
164 * arm-dis.c (thumb32_opcodes): New instruction bfl.
166 2019-04-15 Sudakshina Das <sudi.das@arm.com>
168 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
170 2019-04-15 Sudakshina Das <sudi.das@arm.com>
172 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
173 Arm register with r13 and r15 unpredictable.
174 (thumb32_opcodes): New instructions for bfx and bflx.
176 2019-04-15 Sudakshina Das <sudi.das@arm.com>
178 * arm-dis.c (thumb32_opcodes): New instructions for bf.
180 2019-04-15 Sudakshina Das <sudi.das@arm.com>
182 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
184 2019-04-15 Sudakshina Das <sudi.das@arm.com>
186 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
188 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
190 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
192 2019-04-12 John Darrington <john@darrington.wattle.id.au>
194 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
195 "optr". ("operator" is a reserved word in c++).
197 2019-04-11 Sudakshina Das <sudi.das@arm.com>
199 * aarch64-opc.c (aarch64_print_operand): Add case for
201 (verify_constraints): Likewise.
202 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
203 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
204 to accept Rt|SP as first operand.
205 (AARCH64_OPERANDS): Add new Rt_SP.
206 * aarch64-asm-2.c: Regenerated.
207 * aarch64-dis-2.c: Regenerated.
208 * aarch64-opc-2.c: Regenerated.
210 2019-04-11 Sudakshina Das <sudi.das@arm.com>
212 * aarch64-asm-2.c: Regenerated.
213 * aarch64-dis-2.c: Likewise.
214 * aarch64-opc-2.c: Likewise.
215 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
217 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
219 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
221 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
223 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
224 * i386-init.h: Regenerated.
226 2019-04-07 Alan Modra <amodra@gmail.com>
228 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
229 op_separator to control printing of spaces, comma and parens
230 rather than need_comma, need_paren and spaces vars.
232 2019-04-07 Alan Modra <amodra@gmail.com>
235 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
236 (print_insn_neon, print_insn_arm): Likewise.
238 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
240 * i386-dis-evex.h (evex_table): Updated to support BF16
242 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
243 and EVEX_W_0F3872_P_3.
244 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
245 (cpu_flags): Add bitfield for CpuAVX512_BF16.
246 * i386-opc.h (enum): Add CpuAVX512_BF16.
247 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
248 * i386-opc.tbl: Add AVX512 BF16 instructions.
249 * i386-init.h: Regenerated.
250 * i386-tbl.h: Likewise.
252 2019-04-05 Alan Modra <amodra@gmail.com>
254 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
255 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
256 to favour printing of "-" branch hint when using the "y" bit.
257 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
259 2019-04-05 Alan Modra <amodra@gmail.com>
261 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
262 opcode until first operand is output.
264 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
267 * ppc-opc.c (valid_bo_pre_v2): Add comments.
268 (valid_bo_post_v2): Add support for 'at' branch hints.
269 (insert_bo): Only error on branch on ctr.
270 (get_bo_hint_mask): New function.
271 (insert_boe): Add new 'branch_taken' formal argument. Add support
272 for inserting 'at' branch hints.
273 (extract_boe): Add new 'branch_taken' formal argument. Add support
274 for extracting 'at' branch hints.
275 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
276 (BOE): Delete operand.
277 (BOM, BOP): New operands.
279 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
280 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
281 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
282 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
283 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
284 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
285 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
286 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
287 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
288 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
289 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
290 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
291 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
292 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
293 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
294 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
295 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
296 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
297 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
298 bttarl+>: New extended mnemonics.
300 2019-03-28 Alan Modra <amodra@gmail.com>
303 * ppc-opc.c (BTF): Define.
304 (powerpc_opcodes): Use for mtfsb*.
305 * ppc-dis.c (print_insn_powerpc): Print fields with both
306 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
308 2019-03-25 Tamar Christina <tamar.christina@arm.com>
310 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
311 (mapping_symbol_for_insn): Implement new algorithm.
312 (print_insn): Remove duplicate code.
314 2019-03-25 Tamar Christina <tamar.christina@arm.com>
316 * aarch64-dis.c (print_insn_aarch64):
319 2019-03-25 Tamar Christina <tamar.christina@arm.com>
321 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
324 2019-03-25 Tamar Christina <tamar.christina@arm.com>
326 * aarch64-dis.c (last_stop_offset): New.
327 (print_insn_aarch64): Use stop_offset.
329 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
332 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
334 * i386-init.h: Regenerated.
336 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
339 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
340 vmovdqu16, vmovdqu32 and vmovdqu64.
341 * i386-tbl.h: Regenerated.
343 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
345 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
346 from vstrszb, vstrszh, and vstrszf.
348 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
350 * s390-opc.txt: Add instruction descriptions.
352 2019-02-08 Jim Wilson <jimw@sifive.com>
354 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
357 2019-02-07 Tamar Christina <tamar.christina@arm.com>
359 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
361 2019-02-07 Tamar Christina <tamar.christina@arm.com>
364 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
365 * aarch64-opc.c (verify_elem_sd): New.
366 (fields): Add FLD_sz entr.
367 * aarch64-tbl.h (_SIMD_INSN): New.
368 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
369 fmulx scalar and vector by element isns.
371 2019-02-07 Nick Clifton <nickc@redhat.com>
373 * po/sv.po: Updated Swedish translation.
375 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
377 * s390-mkopc.c (main): Accept arch13 as cpu string.
378 * s390-opc.c: Add new instruction formats and instruction opcode
380 * s390-opc.txt: Add new arch13 instructions.
382 2019-01-25 Sudakshina Das <sudi.das@arm.com>
384 * aarch64-tbl.h (QL_LDST_AT): Update macro.
385 (aarch64_opcode): Change encoding for stg, stzg
387 * aarch64-asm-2.c: Regenerated.
388 * aarch64-dis-2.c: Regenerated.
389 * aarch64-opc-2.c: Regenerated.
391 2019-01-25 Sudakshina Das <sudi.das@arm.com>
393 * aarch64-asm-2.c: Regenerated.
394 * aarch64-dis-2.c: Likewise.
395 * aarch64-opc-2.c: Likewise.
396 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
398 2019-01-25 Sudakshina Das <sudi.das@arm.com>
399 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
401 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
402 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
403 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
404 * aarch64-dis.h (ext_addr_simple_2): Likewise.
405 * aarch64-opc.c (operand_general_constraint_met_p): Remove
406 case for ldstgv_indexed.
407 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
408 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
409 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
410 * aarch64-asm-2.c: Regenerated.
411 * aarch64-dis-2.c: Regenerated.
412 * aarch64-opc-2.c: Regenerated.
414 2019-01-23 Nick Clifton <nickc@redhat.com>
416 * po/pt_BR.po: Updated Brazilian Portuguese translation.
418 2019-01-21 Nick Clifton <nickc@redhat.com>
420 * po/de.po: Updated German translation.
421 * po/uk.po: Updated Ukranian translation.
423 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
424 * mips-dis.c (mips_arch_choices): Fix typo in
425 gs464, gs464e and gs264e descriptors.
427 2019-01-19 Nick Clifton <nickc@redhat.com>
429 * configure: Regenerate.
430 * po/opcodes.pot: Regenerate.
432 2018-06-24 Nick Clifton <nickc@redhat.com>
436 2019-01-09 John Darrington <john@darrington.wattle.id.au>
438 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
440 -dis.c (opr_emit_disassembly): Do not omit an index if it is
443 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
445 * configure: Regenerate.
447 2019-01-07 Alan Modra <amodra@gmail.com>
449 * configure: Regenerate.
450 * po/POTFILES.in: Regenerate.
452 2019-01-03 John Darrington <john@darrington.wattle.id.au>
454 * s12z-opc.c: New file.
455 * s12z-opc.h: New file.
456 * s12z-dis.c: Removed all code not directly related to display
457 of instructions. Used the interface provided by the new files
459 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
460 * Makefile.in: Regenerate.
461 * configure.ac (bfd_s12z_arch): Correct the dependencies.
462 * configure: Regenerate.
464 2019-01-01 Alan Modra <amodra@gmail.com>
466 Update year range in copyright notice of all files.
468 For older changes see ChangeLog-2018
470 Copyright (C) 2019 Free Software Foundation, Inc.
472 Copying and distribution of this file, with or without modification,
473 are permitted in any medium without royalty provided the copyright
474 notice and this notice are preserved.
480 version-control: never