1 2023-07-03 Nick Clifton <nickc@redhat.com>
3 * configure: Regenerate.
4 * po/opcodes.pot: Regenerate.
6 2023-07-03 Nick Clifton <nickc@redhat.com>
10 2023-05-23 Nick Clifton <nickc@redhat.com>
12 * po/sv.po: Updated translation.
14 2023-04-21 Tom Tromey <tromey@adacore.com>
16 * i386-dis.c (OP_J): Check result of get16.
18 2023-04-12 Claudiu Zissulescu <claziss@synopsys.com>
20 * arc-tbl.h: Remove vadds2, vadds2h, vadds4h, vaddsubs,
21 vaddsubs2h, vaddsubs4h, vsubadds, vsubadds2h, vsubadds4h, vsubs2,
22 vsubs2h, and vsubs4h instructions.
24 2023-04-11 Nick Clifton <nickc@redhat.com>
27 * nfp-dis.c (init_nfp6000_priv): Check that the output section
30 2023-03-15 Nick Clifton <nickc@redhat.com>
33 * mep-dis.c: Regenerate.
35 2023-03-15 Nick Clifton <nickc@redhat.com>
38 * arm-dis.c (get_sym_code_type): Check for non-ELF symbols.
40 2023-02-28 Richard Ball <richard.ball@arm.com>
42 * aarch64-opc.c: Add MEC system registers.
44 2023-01-03 Nick Clifton <nickc@redhat.com>
46 * po/de.po: Updated German translation.
47 * po/ro.po: Updated Romainian translation.
48 * po/uk.po: Updated Ukrainian translation.
50 2022-12-31 Nick Clifton <nickc@redhat.com>
52 * 2.40 branch created.
54 2022-11-22 Shahab Vahedi <shahab@synopsys.com>
56 * arc-regs.h: Change isa_config address to 0xc1.
57 isa_config exists for ARC700 and ARCV2 and not ARCALL.
59 2022-10-31 Yoshinori Sato <ysato@users.sourceforge.jp>
61 * rx-decode.opc: Switch arguments of the MVTACGU insn.
62 * rx-decode.c: Regenerate.
64 2022-09-22 Yoshinori Sato <ysato@users.sourceforge.jp>
66 * sh-dis.c (print_insn_sh): Enforce bit7 of LDC Rm,Rn_BANK and STC
67 Rm_BANK,Rn is always 1.
69 2022-07-21 Peter Bergner <bergner@linux.ibm.com>
71 * ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines.
72 (P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4,
73 xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8,
74 xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp,
75 xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp,
76 xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn,
77 xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them.
79 2022-07-18 Claudiu Zissulescu <claziss@synopsys.com>
81 * disassemble.c (disassemble_init_for_target): Set
82 created_styled_output for ARC based targets.
83 * arc-dis.c (find_format_from_table): Use fprintf_styled_ftype
84 instead of fprintf_ftype throughout.
85 (find_format): Likewise.
86 (print_flags): Likewise.
87 (print_insn_arc): Likewise.
89 2022-07-08 Nick Clifton <nickc@redhat.com>
91 * 2.39 branch created.
93 2022-07-04 Marcus Nilsson <brainbomb@gmail.com>
95 * disassemble.c: (disassemble_init_for_target): Set
96 created_styled_output for AVR based targets.
97 * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype
98 instead of fprintf_ftype throughout.
99 (avr_operand): Pass in and fill disassembler_style when
102 2022-04-07 Andreas Krebbel <krebbel@linux.ibm.com>
104 * s390-mkopc.c (main): Enable z16 as CPU string in the opcode
107 2022-03-16 Simon Marchi <simon.marchi@efficios.com>
109 * configure.ac: Handle bfd_amdgcn_arch.
110 * configure: Re-generate.
112 2022-03-06 Sagar Patel <sagarmp@cs.unc.edu>
113 Maciej W. Rozycki <macro@orcam.me.uk>
115 * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
116 for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
117 * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
120 2022-02-17 Nick Clifton <nickc@redhat.com>
122 * po/sr.po: Updated Serbian translation.
124 2022-02-14 Sergei Trofimovich <siarheit@google.com>
126 * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
127 * microblaze-opc.h: Follow 'fsqrt' rename.
129 2022-01-24 Nick Clifton <nickc@redhat.com>
131 * po/ro.po: Updated Romanian translation.
132 * po/uk.po: Updated Ukranian translation.
134 2022-01-22 Nick Clifton <nickc@redhat.com>
136 * configure: Regenerate.
137 * po/opcodes.pot: Regenerate.
139 2022-01-22 Nick Clifton <nickc@redhat.com>
141 * 2.38 release branch created.
143 2022-01-17 Nick Clifton <nickc@redhat.com>
145 * Makefile.in: Regenerate.
146 * po/opcodes.pot: Regenerate.
148 2021-12-02 Marcus Nilsson <brainbomb@gmail.com>
150 * avr-dis.c (avr_operand); Pass in disassemble_info and fill
151 in insn_type on branching instructions.
153 2021-11-25 Andrew Burgess <aburgess@redhat.com>
154 Simon Cook <simon.cook@embecosm.com>
156 * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
157 (riscv_options): New static global.
158 (disassembler_options_riscv): New function.
159 (print_riscv_disassembler_options): Rewrite to use
160 disassembler_options_riscv.
162 2021-11-25 Nick Clifton <nickc@redhat.com>
165 * aarch64-asm.c: Replace assert(0) with real code.
166 * aarch64-dis.c: Likewise.
167 * aarch64-opc.c: Likewise.
169 2021-11-25 Nick Clifton <nickc@redhat.com>
171 * po/fr.po; Updated French translation.
173 2021-10-27 Maciej W. Rozycki <macro@embecosm.com>
175 * Makefile.am: Remove obsolete comment.
176 * configure.ac: Refer `libbfd.la' to link shared BFD library
178 * Makefile.in: Regenerate.
179 * configure: Regenerate.
181 2021-09-27 Nick Alcock <nick.alcock@oracle.com>
183 * configure: Regenerate.
185 2021-09-25 Peter Bergner <bergner@linux.ibm.com>
187 * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
190 2021-09-20 Andrew Burgess <andrew.burgess@embecosm.com>
192 * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
193 before an unknown instruction, '%d' is replaced with the
196 2021-09-02 Nick Clifton <nickc@redhat.com>
199 * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
202 2021-08-17 Shahab Vahedi <shahab@synopsys.com>
204 * arc-regs.h (DEF): Fix the register numbers.
206 2021-08-10 Nick Clifton <nickc@redhat.com>
208 * po/sr.po: Updated Serbian translation.
210 2021-07-26 Chenghua Xu <xuchenghua@loongson.cn>
212 * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
214 2021-06-07 Andreas Krebbel <krebbel@linux.ibm.com>
216 * s390-opc.txt: Add qpaci.
218 2021-07-03 Nick Clifton <nickc@redhat.com>
220 * configure: Regenerate.
221 * po/opcodes.pot: Regenerate.
223 2021-07-03 Nick Clifton <nickc@redhat.com>
225 * 2.37 release branch created.
227 2021-07-02 Alan Modra <amodra@gmail.com>
229 * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
230 (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
231 (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
232 (nds32_opcodes, nds32_operand_fields, nds32_keywords),
233 (nds32_keyword_gpr): Move declarations to..
234 * nds32-asm.h: ..here, constifying to match definitions.
236 2021-07-01 Mike Frysinger <vapier@gentoo.org>
238 * Makefile.am (GUILE): New variable.
239 (CGEN): Use $(GUILE).
240 * Makefile.in: Regenerate.
242 2021-07-01 Mike Frysinger <vapier@gentoo.org>
244 * mep-asm.c (macros): Mark static & const.
245 (lookup_macro): Change return & m to const.
246 (expand_macro): Change mac to const.
247 (expand_string): Change pmacro to const.
249 2021-07-01 Mike Frysinger <vapier@gentoo.org>
251 * nds32-asm.c (operand_fields): Rename to ...
252 (nds32_operand_fields): ... this.
253 (keyword_gpr): Rename to ...
254 (nds32_keyword_gpr): ... this.
255 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
256 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
257 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
258 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
259 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
261 (keywords): Rename to ...
262 (nds32_keywords): ... this.
263 * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
264 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
266 2021-07-01 Mike Frysinger <vapier@gentoo.org>
268 * z80-dis.c (opc_ed): Make const.
269 (pref_ed): Make p const.
271 2021-07-01 Mike Frysinger <vapier@gentoo.org>
273 * microblaze-dis.c (get_field_special): Make op const.
274 (read_insn_microblaze): Make opr & op const. Rename opcodes to
276 (print_insn_microblaze): Make op & pop const.
277 (get_insn_microblaze): Make op const. Rename opcodes to
279 (microblaze_get_target_address): Likewise.
280 * microblaze-opc.h (struct op_code_struct): Make const.
281 Rename opcodes to microblaze_opcodes.
283 2021-07-01 Mike Frysinger <vapier@gentoo.org>
285 * aarch64-gen.c (aarch64_opcode_table): Add const.
286 * aarch64-tbl.h (aarch64_opcode_table): Likewise.
288 2021-06-22 Andrew Burgess <andrew.burgess@embecosm.com>
290 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
293 2021-06-22 Alan Modra <amodra@gmail.com>
295 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do
296 print separator for pcrel insns.
298 2021-06-19 Alan Modra <amodra@gmail.com>
300 * vax-dis.c (print_insn_vax): Avoid pointer overflow.
302 2021-06-19 Alan Modra <amodra@gmail.com>
304 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
307 2021-06-17 Alan Modra <amodra@gmail.com>
309 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
312 2021-06-03 Alan Modra <amodra@gmail.com>
315 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
316 Use unsigned int for inst.
318 2021-06-02 Shahab Vahedi <shahab@synopsys.com>
320 * arc-dis.c (arc_option_arg_t): New enumeration.
321 (arc_options): New variable.
322 (disassembler_options_arc): New function.
323 (print_arc_disassembler_options): Reimplement in terms of
324 "disassembler_options_arc".
326 2021-05-29 Alan Modra <amodra@gmail.com>
328 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
329 Don't special case PPC_OPCODE_RAW.
330 (lookup_prefix): Likewise.
331 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
332 (print_insn_powerpc): ..update caller.
333 * ppc-opc.c (EXT): Define.
334 (powerpc_opcodes): Mark extended mnemonics with EXT.
335 (prefix_opcodes, vle_opcodes): Likewise.
336 (XISEL, XISEL_MASK): Add cr field and simplify.
337 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
338 all isel variants to where the base mnemonic belongs. Sort dstt,
341 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
343 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
344 COP3 opcode instructions.
346 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
348 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
349 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
350 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
351 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
352 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
353 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
354 "cop2", and "cop3" entries.
356 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
358 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
359 entries and associated comments.
361 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
363 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
366 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
368 * mips-dis.c (mips_cp1_names_mips): New variable.
369 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
370 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
371 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
372 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
373 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
376 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
378 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
379 handling code over to...
380 <OP_REG_CONTROL>: ... this new case.
381 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
382 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
383 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
384 replacing the `G' operand code with `g'. Update "cftc1" and
385 "cftc2" entries replacing the `E' operand code with `y'.
386 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
387 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
388 entries replacing the `G' operand code with `g'.
390 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
392 * mips-dis.c (mips_cp0_names_r3900): New variable.
393 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
396 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
398 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
399 and "mtthc2" to using the `G' rather than `g' operand code for
400 the coprocessor control register referred.
402 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
404 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
405 entries with each other.
407 2021-05-27 Peter Bergner <bergner@linux.ibm.com>
409 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
411 2021-05-25 Alan Modra <amodra@gmail.com>
413 * cris-desc.c: Regenerate.
414 * cris-desc.h: Regenerate.
415 * cris-opc.h: Regenerate.
416 * po/POTFILES.in: Regenerate.
418 2021-05-24 Mike Frysinger <vapier@gentoo.org>
420 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
421 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
422 (CGEN_CPUS): Add cris.
424 (stamp-cris): New rule.
425 * cgen.sh: Handle desc action.
426 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
427 * Makefile.in, configure: Regenerate.
429 2021-05-18 Job Noorman <mtvec@pm.me>
432 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
435 2021-05-17 Alex Coplan <alex.coplan@arm.com>
437 * arm-dis.c (mve_opcodes): Fix disassembly of
438 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
439 (is_mve_encoding_conflict): MVE vector loads should not match
441 (is_mve_unpredictable): It's not unpredictable to use the same
442 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
444 2021-05-11 Nick Clifton <nickc@redhat.com>
447 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
448 the end of the code buffer.
450 2021-05-06 Stafford Horne <shorne@gmail.com>
453 * or1k-asm.c: Regenerate.
455 2021-05-01 Max Filippov <jcmvbkbc@gmail.com>
457 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
458 info->insn_info_valid.
460 2021-04-26 Jan Beulich <jbeulich@suse.com>
462 * i386-opc.tbl (lea): Add Optimize.
463 * opcodes/i386-tbl.h: Re-generate.
465 2020-04-23 Max Filippov <jcmvbkbc@gmail.com>
467 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
468 of l32r fetch and display referenced literal value.
470 2021-04-23 Max Filippov <jcmvbkbc@gmail.com>
472 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
473 to 4 for literal disassembly.
475 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
477 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
478 for TLBI instruction.
480 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
482 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
485 2021-04-19 Jan Beulich <jbeulich@suse.com>
487 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
489 (convert_mov_to_movewide): Add initializer for "value".
491 2021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
493 * aarch64-opc.c: Add RME system registers.
495 2021-04-16 Lifang Xia <lifang_xia@c-sky.com>
497 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
498 "addi d,CV,z" to "c.mv d,CV".
500 2021-04-12 Alan Modra <amodra@gmail.com>
502 * configure.ac (--enable-checking): Add support.
503 * config.in: Regenerate.
504 * configure: Regenerate.
506 2021-04-09 Tejas Belagod <tejas.belagod@arm.com>
508 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
509 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
511 2021-04-09 Alan Modra <amodra@gmail.com>
513 * ppc-dis.c (struct dis_private): Add "special".
514 (POWERPC_DIALECT): Delete. Replace uses with..
515 (private_data): ..this. New inline function.
516 (disassemble_init_powerpc): Init "special" names.
517 (skip_optional_operands): Add is_pcrel arg, set when detecting R
518 field of prefix instructions.
519 (bsearch_reloc, print_got_plt): New functions.
520 (print_insn_powerpc): For pcrel instructions, print target address
521 and symbol if known, and decode plt and got loads too.
523 2021-04-08 Alan Modra <amodra@gmail.com>
526 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
528 2021-04-08 Alan Modra <amodra@gmail.com>
531 * ppc-opc.c (DCBT_EO): Move earlier.
532 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
533 (powerpc_operands): Add THCT and THDS entries.
534 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
536 2021-04-06 Alan Modra <amodra@gmail.com>
538 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
539 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
540 symbol_at_address_func.
542 2021-04-05 Alan Modra <amodra@gmail.com>
544 * configure.ac: Don't check for limits.h, string.h, strings.h or
546 (AC_ISC_POSIX): Don't invoke.
547 * sysdep.h: Include stdlib.h and string.h unconditionally.
548 * i386-opc.h: Include limits.h unconditionally.
549 * wasm32-dis.c: Likewise.
550 * cgen-opc.c: Don't include alloca-conf.h.
551 * config.in: Regenerate.
552 * configure: Regenerate.
554 2021-04-01 Martin Liska <mliska@suse.cz>
556 * arm-dis.c (strneq): Remove strneq and use startswith.
557 * cr16-dis.c (print_insn_cr16): Likewise.
558 * score-dis.c (streq): Likewise.
560 * score7-dis.c (strneq): Likewise.
562 2021-04-01 Alan Modra <amodra@gmail.com>
565 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
567 2021-03-31 Alan Modra <amodra@gmail.com>
569 * sysdep.h (POISON_BFD_BOOLEAN): Define.
570 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
571 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
572 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
573 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
574 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
575 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
576 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
577 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
578 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
579 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
580 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
581 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
582 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
583 and TRUE with true throughout.
585 2021-03-31 Alan Modra <amodra@gmail.com>
587 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
588 * aarch64-dis.h: Likewise.
589 * aarch64-opc.c: Likewise.
590 * avr-dis.c: Likewise.
591 * csky-dis.c: Likewise.
592 * nds32-asm.c: Likewise.
593 * nds32-dis.c: Likewise.
594 * nfp-dis.c: Likewise.
595 * riscv-dis.c: Likewise.
596 * s12z-dis.c: Likewise.
597 * wasm32-dis.c: Likewise.
599 2021-03-30 Jan Beulich <jbeulich@suse.com>
601 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
602 (i386_seg_prefixes): New.
603 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
604 (i386_seg_prefixes): Declare.
606 2021-03-30 Jan Beulich <jbeulich@suse.com>
608 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
610 2021-03-30 Jan Beulich <jbeulich@suse.com>
612 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
613 * i386-reg.tbl (st): Move down.
614 (st(0)): Delete. Extend comment.
615 * i386-tbl.h: Re-generate.
617 2021-03-29 Jan Beulich <jbeulich@suse.com>
619 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
620 (cmpsd): Move next to cmps.
621 (movsd): Move next to movs.
622 (cmpxchg16b): Move to separate section.
623 (fisttp, fisttpll): Likewise.
624 (monitor, mwait): Likewise.
625 * i386-tbl.h: Re-generate.
627 2021-03-29 Jan Beulich <jbeulich@suse.com>
629 * i386-opc.tbl (psadbw): Add <sse2:comm>.
631 * i386-tbl.h: Re-generate.
633 2021-03-29 Jan Beulich <jbeulich@suse.com>
635 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
636 pclmul, gfni): New templates. Use them wherever possible. Move
637 SSE4.1 pextrw into respective section.
638 * i386-tbl.h: Re-generate.
640 2021-03-29 Jan Beulich <jbeulich@suse.com>
642 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
643 strtoull(). Bump upper loop bound. Widen masks. Sanity check
645 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
646 Convert all of their uses to representation in opcode.
648 2021-03-29 Jan Beulich <jbeulich@suse.com>
650 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
651 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
652 value of None. Shrink operands to 3 bits.
654 2021-03-29 Jan Beulich <jbeulich@suse.com>
656 * i386-gen.c (process_i386_opcode_modifier): New parameter
658 (output_i386_opcode): New local variable "space". Adjust
659 process_i386_opcode_modifier() invocation.
660 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
662 * i386-tbl.h: Re-generate.
664 2021-03-29 Alan Modra <amodra@gmail.com>
666 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
667 (fp_qualifier_p, get_data_pattern): Likewise.
668 (aarch64_get_operand_modifier_from_value): Likewise.
669 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
670 (operand_variant_qualifier_p): Likewise.
671 (qualifier_value_in_range_constraint_p): Likewise.
672 (aarch64_get_qualifier_esize): Likewise.
673 (aarch64_get_qualifier_nelem): Likewise.
674 (aarch64_get_qualifier_standard_value): Likewise.
675 (get_lower_bound, get_upper_bound): Likewise.
676 (aarch64_find_best_match, match_operands_qualifier): Likewise.
677 (aarch64_print_operand): Likewise.
678 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
679 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
680 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
681 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
682 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
683 (print_insn_tic6x): Likewise.
685 2021-03-29 Alan Modra <amodra@gmail.com>
687 * arc-dis.c (extract_operand_value): Correct NULL cast.
688 * frv-opc.h: Regenerate.
690 2021-03-26 Jan Beulich <jbeulich@suse.com>
692 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
694 * i386-tbl.h: Re-generate.
696 2021-03-25 Abid Qadeer <abidh@codesourcery.com>
698 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
699 immediate in br.n instruction.
701 2021-03-25 Jan Beulich <jbeulich@suse.com>
703 * i386-dis.c (XMGatherD, VexGatherD): New.
704 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
705 (print_insn): Check masking for S/G insns.
706 (OP_E_memory): New local variable check_gather. Extend mandatory
707 SIB check. Check register conflicts for (EVEX-encoded) gathers.
708 Extend check for disallowed 16-bit addressing.
709 (OP_VEX): New local variables modrm_reg and sib_index. Convert
710 if()s to switch(). Check register conflicts for (VEX-encoded)
711 gathers. Drop no longer reachable cases.
712 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
715 2021-03-25 Jan Beulich <jbeulich@suse.com>
717 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
718 zeroing-masking without masking.
720 2021-03-25 Jan Beulich <jbeulich@suse.com>
722 * i386-opc.tbl (invlpgb): Fix multi-operand form.
723 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
724 single-operand forms as deprecated.
725 * i386-tbl.h: Re-generate.
727 2021-03-25 Alan Modra <amodra@gmail.com>
730 * ppc-opc.c (XLOCB_MASK): Delete.
731 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
733 (powerpc_opcodes): Accept a BH field on all extended forms of
734 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
736 2021-03-24 Jan Beulich <jbeulich@suse.com>
738 * i386-gen.c (output_i386_opcode): Drop processing of
739 opcode_length. Calculate length from base_opcode. Adjust prefix
740 encoding determination.
741 (process_i386_opcodes): Drop output of fake opcode_length.
742 * i386-opc.h (struct insn_template): Drop opcode_length field.
743 * i386-opc.tbl: Drop opcode length field from all templates.
744 * i386-tbl.h: Re-generate.
746 2021-03-24 Jan Beulich <jbeulich@suse.com>
748 * i386-gen.c (process_i386_opcode_modifier): Return void. New
749 parameter "prefix". Drop local variable "regular_encoding".
750 Record prefix setting / check for consistency.
751 (output_i386_opcode): Parse opcode_length and base_opcode
752 earlier. Derive prefix encoding. Drop no longer applicable
753 consistency checking. Adjust process_i386_opcode_modifier()
755 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
757 * i386-tbl.h: Re-generate.
759 2021-03-24 Jan Beulich <jbeulich@suse.com>
761 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
763 * i386-opc.h (Prefix_*): Move #define-s.
764 * i386-opc.tbl: Move pseudo prefix enumerator values to
765 extension opcode field. Introduce pseudopfx template.
766 * i386-tbl.h: Re-generate.
768 2021-03-23 Jan Beulich <jbeulich@suse.com>
770 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
772 * i386-tbl.h: Re-generate.
774 2021-03-23 Jan Beulich <jbeulich@suse.com>
776 * i386-opc.h (struct insn_template): Move cpu_flags field past
778 * i386-tbl.h: Re-generate.
780 2021-03-23 Jan Beulich <jbeulich@suse.com>
782 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
783 * i386-opc.h (OpcodeSpace): New enumerator.
784 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
785 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
786 SPACE_XOP09, SPACE_XOP0A): ... respectively.
787 (struct i386_opcode_modifier): New field opcodespace. Shrink
789 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
790 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
792 * i386-tbl.h: Re-generate.
794 2021-03-22 Martin Liska <mliska@suse.cz>
796 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
797 * arc-dis.c (parse_option): Likewise.
798 * arm-dis.c (parse_arm_disassembler_options): Likewise.
799 * cris-dis.c (print_with_operands): Likewise.
800 * h8300-dis.c (bfd_h8_disassemble): Likewise.
801 * i386-dis.c (print_insn): Likewise.
802 * ia64-gen.c (fetch_insn_class): Likewise.
803 (parse_resource_users): Likewise.
804 (in_iclass): Likewise.
805 (lookup_specifier): Likewise.
806 (insert_opcode_dependencies): Likewise.
807 * mips-dis.c (parse_mips_ase_option): Likewise.
808 (parse_mips_dis_option): Likewise.
809 * s390-dis.c (disassemble_init_s390): Likewise.
810 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
812 2021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
814 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
816 2021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
818 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
819 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
821 2021-03-12 Alan Modra <amodra@gmail.com>
823 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
825 2021-03-11 Jan Beulich <jbeulich@suse.com>
827 * i386-dis.c (OP_XMM): Re-order checks.
829 2021-03-11 Jan Beulich <jbeulich@suse.com>
831 * i386-dis.c (putop): Drop need_vex check when also checking
833 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
836 2021-03-11 Jan Beulich <jbeulich@suse.com>
838 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
839 checks. Move case label past broadcast check.
841 2021-03-10 Jan Beulich <jbeulich@suse.com>
843 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
844 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
845 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
846 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
847 EVEX_W_0F38C7_M_0_L_2): Delete.
848 (REG_EVEX_0F38C7_M_0_L_2): New.
849 (intel_operand_size): Handle VEX and EVEX the same for
850 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
851 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
852 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
853 vex_vsib_q_w_d_mode uses.
854 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
855 0F38A1, and 0F38A3 entries.
856 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
858 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
859 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
862 2021-03-10 Jan Beulich <jbeulich@suse.com>
864 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
865 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
866 MOD_VEX_0FXOP_09_12): Rename to ...
867 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
868 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
869 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
870 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
871 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
872 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
873 (reg_table): Adjust comments.
874 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
875 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
876 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
877 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
878 (vex_len_table): Adjust opcode 0A_12 entry.
879 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
880 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
881 (rm_table): Move hreset entry.
883 2021-03-10 Jan Beulich <jbeulich@suse.com>
885 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
886 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
887 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
888 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
889 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
890 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
891 (get_valid_dis386): Also handle 512-bit vector length when
892 vectoring into vex_len_table[].
893 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
894 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
896 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
897 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
898 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
899 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
902 2021-03-10 Jan Beulich <jbeulich@suse.com>
904 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
905 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
906 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
907 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
909 * i386-dis-evex-len.h (evex_len_table): Likewise.
910 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
912 2021-03-10 Jan Beulich <jbeulich@suse.com>
914 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
915 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
916 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
917 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
918 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
919 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
920 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
921 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
922 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
923 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
924 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
925 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
926 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
927 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
928 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
929 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
930 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
931 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
932 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
933 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
934 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
935 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
936 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
937 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
938 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
939 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
940 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
941 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
942 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
943 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
944 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
945 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
946 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
947 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
948 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
949 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
950 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
951 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
952 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
953 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
954 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
955 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
956 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
957 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
958 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
959 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
960 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
961 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
962 EVEX_W_0F3A43_L_n): New.
963 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
964 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
965 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
966 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
967 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
968 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
969 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
970 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
971 0F385B, 0F38C6, and 0F38C7 entries.
972 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
974 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
975 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
976 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
977 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
979 2021-03-10 Jan Beulich <jbeulich@suse.com>
981 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
982 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
983 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
984 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
985 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
986 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
987 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
988 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
989 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
990 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
991 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
992 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
993 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
994 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
995 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
996 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
997 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
998 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
999 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
1000 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
1001 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
1002 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
1003 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
1004 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
1005 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
1006 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
1007 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
1008 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
1009 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
1010 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
1011 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
1012 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
1013 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
1014 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
1015 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
1016 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
1017 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
1018 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
1019 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
1020 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
1021 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
1022 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
1023 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
1024 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
1025 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
1026 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
1027 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
1028 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
1029 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
1030 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
1031 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
1032 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
1033 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
1034 VEX_W_0F99_P_2_LEN_0): Delete.
1035 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
1036 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
1037 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
1038 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
1039 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
1040 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
1041 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
1042 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
1043 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
1044 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
1045 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
1046 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
1047 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
1048 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
1049 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
1050 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
1051 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
1052 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
1053 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
1054 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
1055 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
1056 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
1057 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
1058 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
1059 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
1060 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
1061 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
1062 (prefix_table): No longer link to vex_len_table[] for opcodes
1063 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
1064 0F92, 0F93, 0F98, and 0F99.
1065 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
1066 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1068 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
1069 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1071 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
1072 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1074 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
1075 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1078 2021-03-10 Jan Beulich <jbeulich@suse.com>
1080 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
1081 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
1082 REG_VEX_0F73_M_0 respectively.
1083 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
1084 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
1085 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
1086 MOD_VEX_0F73_REG_7): Delete.
1087 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
1088 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
1089 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
1090 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
1091 PREFIX_VEX_0F3AF0_L_0 respectively.
1092 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
1093 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
1094 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
1095 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
1096 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
1097 VEX_LEN_0F38F7): New.
1098 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
1099 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
1100 0F72, and 0F73. No longer link to vex_len_table[] for opcode
1102 (prefix_table): No longer link to vex_len_table[] for opcodes
1103 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1104 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
1105 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
1106 0F38F6, 0F38F7, and 0F3AF0.
1107 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
1108 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1109 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
1112 2021-03-10 Jan Beulich <jbeulich@suse.com>
1114 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1115 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1116 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1117 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1118 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1119 (MOD_0F71, MOD_0F72, MOD_0F73): New.
1120 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1122 (reg_table): No longer link to mod_table[] for opcodes 0F71,
1124 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1127 2021-03-10 Jan Beulich <jbeulich@suse.com>
1129 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1130 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1131 (reg_table): Don't link to mod_table[] where not needed. Add
1132 PREFIX_IGNORED to nop entries.
1133 (prefix_table): Replace PREFIX_OPCODE in nop entries.
1134 (mod_table): Add nop entries next to prefetch ones. Drop
1135 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1136 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1137 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1138 PREFIX_OPCODE from endbr* entries.
1139 (get_valid_dis386): Also consider entry's name when zapping
1141 (print_insn): Handle PREFIX_IGNORED.
1143 2021-03-09 Jan Beulich <jbeulich@suse.com>
1145 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1146 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1148 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1149 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1150 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1151 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1152 (struct i386_opcode_modifier): Delete notrackprefixok,
1153 islockable, hleprefixok, and repprefixok fields. Add prefixok
1155 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1156 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1157 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1158 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1159 Replace HLEPrefixOk.
1160 * opcodes/i386-tbl.h: Re-generate.
1162 2021-03-09 Jan Beulich <jbeulich@suse.com>
1164 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1165 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1167 * opcodes/i386-tbl.h: Re-generate.
1169 2021-03-03 Jan Beulich <jbeulich@suse.com>
1171 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1172 for {} instead of {0}. Don't look for '0'.
1173 * i386-opc.tbl: Drop operand count field. Drop redundant operand
1176 2021-02-19 Nelson Chu <nelson.chu@sifive.com>
1179 * riscv-dis.c (print_insn_args): Updated encoding macros.
1180 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1181 (match_c_addi16sp): Updated encoding macros.
1182 (match_c_lui): Likewise.
1183 (match_c_lui_with_hint): Likewise.
1184 (match_c_addi4spn): Likewise.
1185 (match_c_slli): Likewise.
1186 (match_slli_as_c_slli): Likewise.
1187 (match_c_slli64): Likewise.
1188 (match_srxi_as_c_srxi): Likewise.
1189 (riscv_insn_types): Added .insn css/cl/cs.
1191 2021-02-18 Nelson Chu <nelson.chu@sifive.com>
1193 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1194 (default_priv_spec): Updated type to riscv_spec_class.
1195 (parse_riscv_dis_option): Updated.
1196 * riscv-opc.c: Moved stuff and make the file tidy.
1198 2021-02-17 Alan Modra <amodra@gmail.com>
1200 * wasm32-dis.c: Include limits.h.
1201 (CHAR_BIT): Provide backup define.
1202 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1203 Correct signed overflow checking.
1205 2021-02-16 Jan Beulich <jbeulich@suse.com>
1207 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1208 * i386-tbl.h: Re-generate.
1210 2021-02-16 Jan Beulich <jbeulich@suse.com>
1212 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1214 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1216 2021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
1218 * s390-mkopc.c (main): Accept arch14 as cpu string.
1219 * s390-opc.txt: Add new arch14 instructions.
1221 2021-02-04 Nick Alcock <nick.alcock@oracle.com>
1223 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1225 * configure: Regenerated.
1227 2021-02-08 Mike Frysinger <vapier@gentoo.org>
1229 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1230 * tic54x-opc.c (regs): Rename to ...
1231 (tic54x_regs): ... this.
1232 (mmregs): Rename to ...
1233 (tic54x_mmregs): ... this.
1234 (condition_codes): Rename to ...
1235 (tic54x_condition_codes): ... this.
1236 (cc2_codes): Rename to ...
1237 (tic54x_cc2_codes): ... this.
1238 (cc3_codes): Rename to ...
1239 (tic54x_cc3_codes): ... this.
1240 (status_bits): Rename to ...
1241 (tic54x_status_bits): ... this.
1242 (misc_symbols): Rename to ...
1243 (tic54x_misc_symbols): ... this.
1245 2021-02-04 Nelson Chu <nelson.chu@sifive.com>
1247 * riscv-opc.c (MASK_RVB_IMM): Removed.
1248 (riscv_opcodes): Removed zb* instructions.
1249 (riscv_ext_version_table): Removed versions for zb*.
1251 2021-01-26 Alan Modra <amodra@gmail.com>
1253 * i386-gen.c (parse_template): Ensure entire template_instance
1256 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1258 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1259 (riscv_fpr_names_abi): Likewise.
1260 (riscv_opcodes): Likewise.
1261 (riscv_insn_types): Likewise.
1263 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1265 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1267 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1269 * riscv-dis.c: Comments tidy and improvement.
1270 * riscv-opc.c: Likewise.
1272 2021-01-13 Alan Modra <amodra@gmail.com>
1274 * Makefile.in: Regenerate.
1276 2021-01-12 H.J. Lu <hongjiu.lu@intel.com>
1279 * configure.ac: Use GNU_MAKE_JOBSERVER.
1280 * aclocal.m4: Regenerated.
1281 * configure: Likewise.
1283 2021-01-12 Nick Clifton <nickc@redhat.com>
1285 * po/sr.po: Updated Serbian translation.
1287 2021-01-11 H.J. Lu <hongjiu.lu@intel.com>
1290 * configure: Regenerated.
1292 2021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1294 * aarch64-asm-2.c: Regenerate.
1295 * aarch64-dis-2.c: Likewise.
1296 * aarch64-opc-2.c: Likewise.
1297 * aarch64-opc.c (aarch64_print_operand):
1298 Delete handling of AARCH64_OPND_CSRE_CSR.
1299 * aarch64-tbl.h (aarch64_feature_csre): Delete.
1301 (_CSRE_INSN): Likewise.
1302 (aarch64_opcode_table): Delete csr.
1304 2021-01-11 Nick Clifton <nickc@redhat.com>
1306 * po/de.po: Updated German translation.
1307 * po/fr.po: Updated French translation.
1308 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1309 * po/sv.po: Updated Swedish translation.
1310 * po/uk.po: Updated Ukranian translation.
1312 2021-01-09 H.J. Lu <hongjiu.lu@intel.com>
1314 * configure: Regenerated.
1316 2021-01-09 Nick Clifton <nickc@redhat.com>
1318 * configure: Regenerate.
1319 * po/opcodes.pot: Regenerate.
1321 2021-01-09 Nick Clifton <nickc@redhat.com>
1323 * 2.36 release branch crated.
1325 2021-01-08 Peter Bergner <bergner@linux.ibm.com>
1327 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1328 (DW, (XRC_MASK): Define.
1329 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1331 2021-01-09 Alan Modra <amodra@gmail.com>
1333 * configure: Regenerate.
1335 2021-01-08 Nick Clifton <nickc@redhat.com>
1337 * po/sv.po: Updated Swedish translation.
1339 2021-01-08 Nick Clifton <nickc@redhat.com>
1342 * aarch64-dis.c (determine_disassembling_preference): Move call to
1343 aarch64_match_operands_constraint outside of the assertion.
1344 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1345 Replace with a return of FALSE.
1348 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1349 core system register.
1351 2021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1353 * configure: Regenerate.
1355 2021-01-07 Nick Clifton <nickc@redhat.com>
1357 * po/fr.po: Updated French translation.
1359 2021-01-07 Fredrik Noring <noring@nocrew.org>
1361 * m68k-opc.c (chkl): Change minimum architecture requirement to
1364 2021-01-07 Philipp Tomsich <prt@gnu.org>
1366 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1368 2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1369 Jim Wilson <jimw@sifive.com>
1370 Andrew Waterman <andrew@sifive.com>
1371 Maxim Blinov <maxim.blinov@embecosm.com>
1372 Kito Cheng <kito.cheng@sifive.com>
1373 Nelson Chu <nelson.chu@sifive.com>
1375 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1376 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1378 2021-01-01 Alan Modra <amodra@gmail.com>
1380 Update year range in copyright notice of all files.
1382 For older changes see ChangeLog-2020
1384 Copyright (C) 2021-2023 Free Software Foundation, Inc.
1386 Copying and distribution of this file, with or without modification,
1387 are permitted in any medium without royalty provided the copyright
1388 notice and this notice are preserved.
1394 version-control: never